- TF-A - lists.trustedfirmware.org

by Shebu Varghese Kuriakose

Hi All, Trustedfirmware.org community project would like to invite you to the Mbed TLS Virtual Workshop on November 3rd (Tuesday) from 2pm to 6pm GMT. The purpose of the workshop is to bring together the Mbed TLS community including maintainers, contributors and users to discuss * The future direction of the project and * Ways to improve community collaboration The workshop will be hosted in Zoom open to all. The invitation with the zoom link will be send in the Mbed TLS, PSA Crypto* mailing lists in the coming days. Here are some of the proposed agenda topics. Please reply if there is anything else you would like us or you to present during the workshop that will be interesting to the community * Constant-time code * How to be an effective Mbed TLS reviewer * Processes - how does work get scheduled? * Roadmap, Mbed TLS3.0 * PSA Crypto APIs * How Do I contribute my first review. Thanks, Shebu (TrustedFirmware.org Co-Chair, Mbed TLS Technology Manager) * https://lists.trustedfirmware.org/mailman/listinfo/mbed-tls https://lists.trustedfirmware.org/mailman/listinfo/psa-crypto

5 years, 3 months

1
0
0 0

commit 75fab6496e5fce9a11 ("libc: memset: improve performance by avoiding single byte writes") causing BL31 boot failure on Renesas RZ/G2 platforms.

by Biju Das

Hi All, I am porting Renesas RZ/G2M[1] platform to TF-A Master branch(commitid: eeb77da646844) . Initially faced a compilation error [2] which is fixed by using "#define" instead of "static const uint64_t". Then on target, found that BL31 is failed to boot[3], which is fixed by reverting the commit 75fab6496e5fce9a11 ("libc: memset: improve performance by avoiding single byte writes"), see the logs [3]. Q1) Have you seen this issue? Please share your thoughts on this issues. [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz/… [2] https://lists.trustedfirmware.org/pipermail/tf-a/2020-October/000763.html [3] Failure logs ------------ NOTICE: BL2: RZ/G Initial Program Loader(CA57) Rev.2.0.6 NOTICE: BL2: PRR is RZG G2M Ver.1.3 NOTICE: BL2: Board is HiHope RZ/G2M Rev.4.0 NOTICE: BL2: Boot device is QSPI Flash(40MHz) NOTICE: BL2: LCM state is unknown NOTICE: BL2: DDR3200(rev.0.40) NOTICE: BL2: [COLD_BOOT] NOTICE: BL2: DRAM Split is 2ch NOTICE: BL2: QoS is default setting(rev.0.19) NOTICE: BL2: DRAM refresh interval 1.95 usec NOTICE: BL2: Periodic Write DQ Training NOTICE: BL2: CH0: 400000000 - 47fffffff, 2 GiB NOTICE: BL2: CH2: 600000000 - 67fffffff, 2 GiB NOTICE: BL2: FDT at 0xe632a648 NOTICE: BL2: v2.3(release):v2.3-778-g4fd58b045 NOTICE: BL2: Built : 18:14:35, Oct 8 2020 NOTICE: BL2: Normal boot NOTICE: BL2: dst=0xe6328300 src=0x8180000 len=512(0x200) NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800) NOTICE: rcar_file_len: len: 0x0003e000 NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000) NOTICE: rcar_file_len: len: 0x00100000 NOTICE: BL2: dst=0x50000000 src=0x8300000 len=1048576(0x100000) NOTICE: BL2: Booting BL31 [4]Working logs after reverting the commit 75fab6496e5fce9a11 ("libc: memset: improve performance by avoiding single byte writes") -------------------------------------- NOTICE: BL2: RZ/G Initial Program Loader(CA57) Rev.2.0.6 NOTICE: BL2: PRR is RZG G2M Ver.1.3 NOTICE: BL2: Board is HiHope RZ/G2M Rev.4.0 NOTICE: BL2: Boot device is QSPI Flash(40MHz) NOTICE: BL2: LCM state is unknown NOTICE: BL2: DDR3200(rev.0.40) NOTICE: BL2: [COLD_BOOT] NOTICE: BL2: DRAM Split is 2ch NOTICE: BL2: QoS is default setting(rev.0.19) NOTICE: BL2: DRAM refresh interval 1.95 usec NOTICE: BL2: Periodic Write DQ Training NOTICE: BL2: CH0: 400000000 - 47fffffff, 2 GiB NOTICE: BL2: CH2: 600000000 - 67fffffff, 2 GiB NOTICE: BL2: FDT at 0xe632a648 NOTICE: BL2: v2.3(release):v2.3-779-geba02ef39 NOTICE: BL2: Built : 18:16:47, Oct 8 2020 NOTICE: BL2: Normal boot NOTICE: BL2: dst=0xe6328300 src=0x8180000 len=512(0x200) NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800) NOTICE: rcar_file_len: len: 0x0003e000 NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000) NOTICE: rcar_file_len: len: 0x00100000 NOTICE: BL2: dst=0x50000000 src=0x8300000 len=1048576(0x100000) NOTICE: BL2: Booting BL31 U-Boot 2020.10-00535-gd0e9210a2f (Oct 08 2020 - 12:34:09 +0100) CPU: Renesas Electronics R8A774A1 rev 1.3 Model: HopeRun HiHope RZ/G2M with sub board DRAM: 3.9 GiB MMC: mmc@ee100000: 0, mmc@ee160000: 1 Loading Environment from MMC... OK In: serial@e6e88000 Out: serial@e6e88000 Err: serial@e6e88000 Net: eth0: ethernet@e6800000 Hit any key to stop autoboot: 0 Regards, Biju Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

5 years, 3 months

2
20
0 0

Re: [TF-A] commit 75fab6496e5fce9a11 ("libc: memset: improve performance by avoiding single byte writes") causing BL31 boot failure on Renesas RZ/G2 platforms.

by Ash Wilding

Hi Biju, Andre, > sctlr_el3 = 0x0000000030c5183a The MMU is still disabled since we're so early in BL31, so nothing preventing us from making an actual access to physical address 0x0. As Andre already noted: > x30 = 0x0000000000000000 > elr_el3 = 0x0000000000000000 > far_el3 = 0x0000000000000000 It looks like we do have an errant null pointer dereference here. If I had to guess, the I-side successfully fetches a 32-bit word from physical address 0x0, but then fails to decode that bit pattern as a valid opcode. This is reported as "unknown reason", like you're seeing: <quote Arm ARM DDI 0487E.a pp D13-2963> This EC code is used for all exceptions that are not covered by any other EC value. This includes exceptions that are generated in the following situations: - ... - Instruction encodings that are unallocated. - ... </quote> Hope that helps, Ash.

5 years, 3 months

2
1
0 0

Re: [TF-A] commit 75fab6496e5fce9a11 ("libc: memset: improve performance by avoiding single byte writes") causing BL31 boot failure on Renesas RZ/G2 platforms.

by Ash Wilding

From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Ash Wilding via TF-A <TF-A(a)lists.trustedfirmware.org> Date: Sunday, 11 October 2020 at 18:53 <...> It looks like we do have an errant null pointer dereference here. <...> Just to clarify, when I say "null pointer dereference": - you may be trampling over your stack, causing you to pop 0x0 into LR and return there; - you may be trampling over your stack, causing you to pop 0x0 into a GPR that is then BLR'd to; - you may be trampling over some other region of memory containing a function pointer, causing you to load 0x0 into a GPR that is then BLR'd to; - etc. Cheers, Ash.

5 years, 4 months

1
0
0 0

Questions raised about Measured Boot + fTPM test case

by Javier Almansa Sobrino

Hello all, Following up the question raised yesterday during the TF-A Tech Forum with regards to any modification needed on the Linux Kernel to run the test case that I was presenting (Measured Boot + fTPM service), I double checked today and I ran some tests on system and I can confirm that the test case works with the mainline Linux Kernel, with no modification other than enabling the driver on the DTB. The modules involved on the interaction with the fTPM (for this particular example) are: * optee.ko: Allows communication between the REE (unsecure world), the Trusted OS (secure world) and the tee-supplicant (unsecure world). * tpm_ftpm_tee.ko: Module to communicate with a firmware TPM through a char device. This also includes the reference implementation used on the test case. In order to use the fTPM service, the test case makes use of IBM's TPM 2.0 TSS, a user space TSS for TPM 2.0 that uses services provided by the fTPM. I would also like to highlight the following points: A) The test case is only meant to test the ability of the Measured Boot Driver and a TPM 2.0 compliant device to interact with each other. As such, we are not providing an fTPM meant to be used on a production environment. Instead, we are using an existing reference implementation to which we added support for Measured Boot to fulfil our needs for the test and use it as a functional example. The implementation details on how to interact with a particular TPM device (either firmware or discrete) can differ from the ones used on the test case as those details can be platform dependent. For example, we use an OPTEE TA fTPM on this example, but other platforms might use a discrete TPM or an fTPM running on a different Trusted OS. B) As stated on the presentation, we are undergoing internal review of the contributions done for the fTPM service to make it compatible with Measured Boot. Once the review is completed and the changes merged into the TPM repo mainline, we will update the TF-A documentation with instructions on how to download and build all the components to run the tests manually. Please, let me know in case you have any more questions. Best regards, Javier

5 years, 4 months

1
0
0 0

Re: [TF-A] commit 75fab6496e5fce9a11 ("libc: memset: improve performance by avoiding single byte writes") causing BL31 boot failure on Renesas RZ/G2 platforms.

by Alexei Fedorov

Hi Biju, As you work with Renesas platforms, have you also seen "Renesas rcar-gen3: cert_header_sa6 Compilation Issue" which I reported on the mailing list on 10/12/2018 and is still not fixed? tools\renesas\rcar_layout_create\sa6.c has #include <stdint.h> which causes compilation error on Yocto 3.13: | aarch64-poky-linux-gcc -DRCAR_SA0_SIZE=1 -DRCAR_SA6_TYPE=0 -I../../include/lib/stdlib -D=AARCH64 -c -o sa6.o sa6.c | In file included from sa6.c:7:0: | /home/alexei/Work/Yocto_3.13_20181205/build/tmp/work/h3ulcb-poky-linux/arm-tf/2.0+gitAUTOINC+19b56cf4a2_556d7d9e3b-r0/recipe-sysroot-native/usr/lib/aarch64-poky-linux/gcc/aarch64-poky-linux/7.3.0/include/stdint.h:9:16: fatal error: stdint.h: No such file or directory | # include_next <stdint.h> | ^~~~~~~~~~ | compilation terminated. | <builtin>: recipe for target 'sa6.o' failed | make[1]: *** [sa6.o] Error 1 | plat/renesas/rcar/platform.mk:403: recipe for target 'rcar_layout_tool' failed | make: *** [rcar_layout_tool] Error 2 | ERROR: oe_runmake failed There's no compilation error with gcc-arm-8.2-2018.08-i686-mingw32-aarch64-elf tool chain, because compiler searches for <stdint.h> in \gcc-arm-8.2-2018.08-i686-mingw32-aarch64-elf\lib\gcc\aarch64-elf\8.2.1\include finding "stdint.h" with # include_next <stdint.h> and then getting "stdint.h" from gcc-arm-8.2-2018.08-i686-mingw32-aarch64-elf\aarch64-elf\include folder. Trusted Firmware-A Porting Guide reads that "To avoid subtle toolchain behavioral dependencies, the header files provided by the compiler are not used. The software is built with the ``-nostdinc`` flag to ensure no headers are included from the toolchain inadvertently. ", tools\renesas\rcar_layout_create\makefile has flags defined as: CFLAGS += ${DEFINES} CFLAGS += -I../../include/lib/stdlib and adding "-nostdinc" flag will make gcc-arm-8.2-2018.08-i686-mingw32-aarch64-elf compilation fail because ../../include/lib/stdlib is a wrong path (taken from Renesas ARM-TF version 1.5 "tools\dummy_create\makefile") to include\lib\libc\stdint.h for version ARM-TF version 2.0. This issue can be fixed by changing CFLAGS to CFLAGS += -nostdinc \ -I../../../include/lib/libc \ -I../../../include/lib/libc/aarch64 Regards. Alexei. ________________________________ From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Biju Das via TF-A <tf-a(a)lists.trustedfirmware.org> Sent: 09 October 2020 08:12 To: Andre Przywara <Andre.Przywara(a)arm.com>; TF-A(a)lists.trustedfirmware.org <TF-A(a)lists.trustedfirmware.org>; Madhukar Pappireddy <Madhukar.Pappireddy(a)arm.com>; Joanna Farley <Joanna.Farley(a)arm.com> Cc: Marek Vasut <marek.vasut(a)gmail.com>; Chris Paterson <Chris.Paterson2(a)renesas.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj(a)bp.renesas.com> Subject: Re: [TF-A] commit 75fab6496e5fce9a11 ("libc: memset: improve performance by avoiding single byte writes") causing BL31 boot failure on Renesas RZ/G2 platforms. Hi Andre, Thanks for the feedback. > Subject: Re: commit 75fab6496e5fce9a11 ("libc: memset: improve > performance by avoiding single byte writes") causing BL31 boot failure on > Renesas RZ/G2 platforms. > > On 08/10/2020 20:05, Biju Das wrote: > > Hi, > > > I am porting Renesas RZ/G2M[1] platform to TF-A Master > > branch(commitid: eeb77da646844) . Initially faced a compilation error [2] > which is fixed by using "#define" instead of "static const uint64_t". > > What is your exact fix? That compilation error sounds like a more serious > issue, I am scratching my head how such a change would really fix things? Looks like this issue is related to toolchain, I was using aarch64-linux-gcc-7 on U-buntu 18.04 Host toolchain. The compilation is error is fixed by the below changes. #define BL31_RO_BASE BL_CODE_BASE #define BL31_RO_LIMIT BL_CODE_END #define BL31_COHERENT_RAM_BASE BL_COHERENT_RAM_BASE #define BL31_COHERENT_RAM_LIMIT BL_COHERENT_RAM_END The warning fix should not lead to compilation error with the old toolchains. It should be backward compatible to the old toolchains right? Please share your views. > And do you see this with mainline? I tried: Yes > $ make bl31 PLAT=rcar LSI=M3 MBEDTLS_DIR=../mbedtls.git on origin/master > and it built just fine. Thanks for the hint, After using the toolchain[1], I got the same results as your's. it compiles successfully. So the issue is related to using older tool chains. [1] https://developer.arm.com/tools-and-software/open-source-software/developer… > > > Then on target, found that BL31 is failed to boot[3], which is fixed > > by reverting the commit 75fab6496e5fce9a11 > > ("libc: memset: improve performance by avoiding single byte writes"), see > the logs [3]. > > Mmmh, interesting. Can you build with "DEBUG=1" to get more output from > BL31? Sure Will do and provide feedback. > I see some calls to memset() from code in drivers/renesas/rcar. > Can you add some debug prints at the top of memset() to dump the > parameters on each call? To see what breaks it? OK. > Are you using memset on some I/O memory, by any chance? And that > doesn't support all access types, like 64-bit stores? Will check and let you know. Cheers, Biju Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647 -- TF-A mailing list TF-A(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-a

5 years, 4 months

2
2
0 0

Forthcoming Trusted Firmware-A 2.4 release

by Manish Badarkhe

Hi, This is to notify that we are planning to target the Trusted Firmware-A 2.4 release during the second week of November 2020 as part of the regular 6 month cadence. The aim is to consolidate all TF-A work since the 2.3 release. As part of this, a release candidate tag will be created and release activities will commence from Friday 30th Oct 2020 (code freeze date). Essentially we will not merge any major enhancements from this date until the release is made. Please ensure any Pull Requests (PR’s) desired to make the 2.4 release are submitted in good time, to be completed by Tuesday 27th Oct 2020. Any major enhancement PR’s still open after that date will not be merged until after the release Please note, there is no guarantee that all patches under review will be merged before the code freeze date. Any patches that don’t make the code freeze date will complete their review and merge post the release date. Thanks Manish Badarkhe

5 years, 4 months

1
0
0 0

Compilation error with commit "ca661a0092c8ead5ac7df57c55fffcc835d9c0b9"

by Biju Das

Hi All, I am getting compilation error with Mainline TFA on renesas platform for bl31 build. Build command: #make CROSS_COMPILE=aarch64-linux-gnu- bl31 PLAT=rcar LSI=M3 MBEDTLS_DIR=../mbedtls Q1) Have any one see this issue? Please correct me, if I am doing something wrong. On further investigation, the below commit introduced the issue [1] [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/plat/ren… It gives compilation error " error: initializer element is not constant" for BL_CODE_BASE [2] [2] https://elixir.bootlin.com/arm-trusted-firmware/latest/source/plat/renesas/… BL_CODE_BASE gets its value from linker in [3] [3] https://elixir.bootlin.com/arm-trusted-firmware/latest/source/include/commo… If you see [4], the initializer element is not constant [4] https://elixir.bootlin.com/arm-trusted-firmware/latest/source/include/lib/u… Error logs: biju@biju-VirtualBox:~/work/trusted-firmware-a$ CC plat/renesas/rcar/bl31_plat_setup.c plat/renesas/rcar/bl31_plat_setup.c:25:39: error: initializer element is not constant static const uint64_t BL31_RO_BASE = BL_CODE_BASE; ^~~~~~~~~~~~ plat/renesas/rcar/bl31_plat_setup.c:26:40: error: initializer element is not constant static const uint64_t BL31_RO_LIMIT = BL_CODE_END; ^~~~~~~~~~~ plat/renesas/rcar/bl31_plat_setup.c:29:48: error: initializer element is not constant static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; ^~~~~~~~~~~~~~~~~~~~ plat/renesas/rcar/bl31_plat_setup.c:30:49: error: initializer element is not constant static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; ^~~~~~~~~~~~~~~~~~~ Makefile:1109: recipe for target '/home/biju/work/trusted-firmware-a/build/rcar/release/bl31/bl31_plat_setup.o' failed make: *** [/home/biju/work/trusted-firmware-a/build/rcar/release/bl31/bl31_plat_setup.o] Error 1 Regards, Biju Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

5 years, 4 months

1
1
0 0

Re: [TF-A] Query SPD/SPMD behavior with EHF

by Achin Gupta

Hi Sandeep, A few comments inline from a SW architecture/FF-A perspective. > On 5 Oct 2020, at 12:28, Sandeep Tripathy via TF-A <tf-a(a)lists.trustedfirmware.org> wrote: > > Hi Olivier, > Appreciate the details. I have a different perception of G0 > interrupts and their relevance to RAS/ critical events. > Comments in line. > Thanks > Sandeep > > On Fri, Oct 2, 2020 at 6:47 PM Olivier Deprez <Olivier.Deprez(a)arm.com> wrote: >> >> Hi Sandeep, >> >> Here are a few more details. >> The reasoning differs when considering pre-Armv8.4 platforms (1) vs Armv8.4 platforms onwards with secure virtualization enabled (2). >> >> Case (1): >> >> EHF framework unifies EL3 exceptions delivered via different vectors and allows them to be handled in a common way. It is also allowing exception delegation handling to lower secure ELs. This framework although primarily used for RAS, is also used for SDEI and platform EL3 interrupts. EL3's role in this case is about trapping and routing the event to appropriate the component (when the interrupt/exception is not handled solely at EL3). >> >> The interoperability between EHF and a Trusted OS is not accurately defined apart from this guidance in EHF documentation: >> "In order for S-EL1 software to handle Non-secure interrupts while having EHF enabled, the dispatcher must adopt a model where Non-secure interrupts are received at EL3, but are then synchronously handled over to S-EL1." >> >> Until then for the specific RAS handling scenario, this was delegated to a StandaloneMM partition running at S-EL0 (through the SPM-MM implementation) and not necessarily delegated to a TOS. > > Reliability is provided by the feature of G0 interrupt that it can not > be masked by lower ELs. Such interrupt being handled at EL3 or being > delegated to other components does not impact the > reliable feature of G0 interrupt. Sure its handling must be offloaded > to other components to keep EL3 firmware light. But If it were just > about handling an interrupt then it could have been entirely handled > in each state without even requiring an EL3 interrupt type. Reliability in RAS is a different concept. RAS error interrupts do not provide reliability. They report unreliable operation. Routing RAS interrupts to EL3 is an implementation choice called Firmware First Handling (FFH). Indeed, the interrupts could be routed to a lower EL which is called Kernel first handling (KFH). For e.g. an implementation could decide to handle corrected errors Kernel first. Uncorrected errors could be routed to a platform controller instead of firmware or be routed to both. There is no single solution. With FFH, the main requirement is that an uncorrected error must be handled even if the Normal world is not in a position to do so. There are non-technical requirements too but lets not go there. So I don’t think there is a requirement that "no lower EL" should be able to mask the interrupt. EL3/S-EL1 and EL3/S-EL2 are at the same privilege level as far as access to the physical address space is concerned. G0 interrupts could be routed to EL3 but they can be disabled by S-EL1 or S-EL2 by programming the GIC distributor. The main point being that software in all privileged exception levels in the Secure world must be trusted to handle RAS errors in the Normal world. Routing G0 interrupts to EL3 is not a silver bullet. When support for FFH was added to TF-A, there was no use case to put software in S-EL1. This EL is owned by TF-A which deploys a simple shim layer. The EHF was developed with this assumption in mind. If your requirement is to put a Trusted OS in S-EL1 and continue doing RAS error handling, then the requirements of the Trusted OS w.r.t the interrupt routing model must be factored in. Hence, the question about what exactly are your requirements. I can understand the desire to reuse EHF but it cannot come at the cost of not meeting the TOS requirements. It needs a SW architecture discussion first. It might be possible to preempt S-EL1 and route RAS errors to EL3 in some cases. A cooperative model (2) between S-EL1 and EL3 (as Olivier described) is what most Trusted OSs implement today. It would be good to understand why that would not work for RAS. > >> >> In order to better help you, we would need more information on the scenario you intend to achieve, and the environment (Arm architecture version and extensions, GIC version). >> Or maybe your question was out of curiosity for the longer term approach (2) as described below? > > As per sbsa level III spec: sbsa non secure watchdog WS1 (reset) must > be targeted at EL3. The patch in review ref: > https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5495 > And we would want a watchdog interrupt to preempt all execution > context. I would expect the same with any RAS or SDEI critical prio > events. Thanks for pointing this out! SBSA applies to the Server segment. It was reasonable to assume that Secure firmware almost entirely resides in EL3. Hence the guidance. We will look at rewording this in a future release. The intent is that since it is a Non-secure Watchdog, the WS1 signal must not be masked by the Normal world. The BSA applies to all segments. It leaves routing of WS1 implementation defined as long as the Normal world cannot mask it. It could be routed to S-EL1 or S-EL2 if that fulfils the requirement. > Another misc application of our platform is to be able to forcefully > turn off/ halt/ just ping any core at any execution context (S/NS). > These motivated me to leverage EHF. But the idea of dropping EHF in > future designs makes me think now ! > > Our current system is pre Armv8.4. We will stick to case (1). Case > (2) ie SPMD was just my quoricity. However, I felt PSA-FFA may > replace TOS specific SPDs someday. > Making SPMD relevant in this discussion even with pre 8.4 systems. > Because at least the TOS will have to follow one policy. The SPMD is indeed meant to replace TOS specific SPDs. It is meant to cater for the RAS use case as well. From an FF-A perspective, a cooperative approach is simpler. I would like to understand why this would not work for RAS error interrupts as well. Reuse of EHF is an implementation level discussion and I don’t think that is off the table even with (2). > >> >> Case (2): >> >> As a general rule, it is preferred that EL3 reduces its footprint and minimises platform specific handling code. > > Agreed. Applies to case(1) aswell and heavy lifting to be delegated > to lower ELs in either security states. My concern is on 'Taking' the > interrupt handling (mjust)can be delegated. It would certainly be desirable to reuse the EHF. However, it is not possible to delegate the heavy lifting to preempted software in S-EL1 or S-EL2 without significantly increasing their complexity. This is not the current direction of travel of FF-A. > >> EHF framework would most probably not be enabled at all. >> The priority logic provided by the GIC PMR register to mask NS interrupts cannot really work as before because all of trusted EL3/S-EL2 and untrusted S-EL1 SPs can manipulate this register. > > This is a limitation. This can be taken care of by cooperative > software design. ie. S_EL2/S_EL1 will not set PMR out of its range. > And the platform defines what's EL3 priority range. > GIC_LOWEST_EL3_PRI. This falls under the solution space. It would be good to understand what is it you want to run on S-EL1/S-EL2 first. > >> Any secure/non-secure interrupt triggered while running SEL1/SEL0 is trapped first by the S-EL2 firmware (or the so-called SPMC). This translates into SCR_EL3.FIQ/IRQ=0 in the secure world. >> Group1NS interrupts are redirected to SPMD for routing to NWd. >> >> A Group0 interrupt is possibly redirected to a platform driver into an S-EL1 secure partition (e.g. a RAS handling service). >> Hence it does no longer hold true that Group0 interrupts are necessarily qualified as "EL3 interrupts". >> It is still possible to redirect Group0 interrupts from S-EL2 to EL3 and be handled there, but as said, this is a less preferred approach. >> >> Either way when NWd runs (with SCR_EL3.FIQ=1/IRQ=0), a Group1S/Group0 secure interrupt is trapped at EL3 and routed to SPMD then SPMC. >> The SPMC can take the decision to resume the secure partition which registered the corresponding secure INTID. >> >> This design does mean that SDEI interrupt handling would need SPMC and BL31 collaboration and this is something we are working on. > > I understood this scheme. But it means RAS interrupts and other > critical events will always have blackout periods even with proper > software design. RAS interrupts will have blackout periods even if a SMC is handled entirely in EL3. How is routing them to S-EL1 or S-EL2 any different? Afaiu, the RAS architecture spec does not lay down any time limits on by when an error must be reported. All RAS errors are not critical errors. Even critical errors e.g. uncontainable errors report something that has already happened. With unrecoverable errors, ESBs ensure that the problem is contained to a particular EL or Security state. Could you elaborate on what timing requirements you have and why a cooperative model would cause problems? > Whereas with the other routing model scheme the reliability of EHF > handlers can be retained with the constraint of PMR ranges. There may > be something > I am missing. I don’t think “reliability” is an argument here. It is about reusing the EHF in EL3. It is not off the table but we cannot overlook other evolutions in the software and hardware architecture since the EHF was written. Let me know what you think. Cheers, Achin > >> >> Hope this helps. >> >> Regards, >> Olivier. >> >> >> ________________________________________ >> From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Olivier Deprez via TF-A <tf-a(a)lists.trustedfirmware.org> >> Sent: 28 September 2020 14:01 >> To: Sandeep Tripathy; Soby Mathew >> Cc: tf-a(a)lists.trustedfirmware.org; nd >> Subject: Re: [TF-A] Query SPD/SPMD behavior with EHF >> >> Hi Sandeep, >> >> Your question is very valid and we're discussing options internally. >> >> We will come back to you with a consolidated answer shortly. >> >> Regards, >> Olivier. >> >> ________________________________________ >> From: Sandeep Tripathy >> Sent: Monday, September 28, 2020 05:28 >> To: Soby Mathew >> Cc: Dan Handley; tf-a(a)lists.trustedfirmware.org; nd; Olivier Deprez >> Subject: Re: [TF-A] Query SPD/SPMD behavior with EHF >> >> >> Thanks Soby and Dan for confirmation on TSPD. I can see a few more gaps >> in the related area. >> >> "The EL3 interrupts (G0 interrupts) should be able to pre-empt Fast >> SMC i.e. any execution context for that matter ". >> This should apply to all SPDs including SPMD. However I learned from >> @Oliver that SPMD/SPMC design traps FIQs to S_EL2. >> >> In that case a RAS interrupt can be masked by S_EL2 software (eg: >> Hafnium). Probably by design it will be ensured that S_EL2 will never >> mask the physical FIQ ? >> >> S_EL2 FIQ handler will exit to EL3/SPMD by SMC call. And depending on >> the pending interrupt type either it can exit to NWd OR invoke el3 fiq >> vector handler synchronously ? >> >> Are there limitations if we trap fiq to EL3 instead ? >> >> Thanks >> Sandeep >> On Fri, Sep 18, 2020 at 6:26 PM Soby Mathew <Soby.Mathew(a)arm.com> wrote: >>> >>> Hi Sandeep >>> >>>> Except during yielding SMC ‘disable_intr_rm_local(INTR_TYPE_NS, SECUE);’ is in effect. Intention is to avoid NS interrupt preempt secure execution (Fast SMC). >>>> But I think that will also disable G0 interrupt as both NS interrupt and G0 interrupt are on FIQ. >>>> EHF already ensures this by GIC PMR adjustment. So disabling routing model seems unnecessary in this case. >>>> This is my understanding from the code please confirm if this is correct. >>> >>> The EL3 interrupts (G0 interrupts) should be able to pre-empt Fast SMC. Hence the usage of GIC PMR to mask the NS interrupts. As Dan says, the TSP_NS_INTR_ASYNC_PREEMPT predates the EHF design and it seems there is a problem as you describe. >>> >>>> EHF already ensures this by GIC PMR adjustment. So disabling routing model seems unnecessary in this case. >>>> This is my understanding from the code please confirm if this is correct. >>> >>> You are right. Routing model manipulation is not required when EL3 interrupts are present as GIC PMR manipulation should take care of the required behaviour for yielding vs atomic SMC. You also need to ensure it works as expected when EL3 interrupts are not enabled and when EHF is disabled. >>> >>> Best Regards >>> Soby Mathew >>> >>>> -----Original Message----- >>>> From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Sandeep >>>> Tripathy via TF-A >>>> Sent: 17 September 2020 16:53 >>>> To: Dan Handley <Dan.Handley(a)arm.com> >>>> Cc: tf-a(a)lists.trustedfirmware.org >>>> Subject: Re: [TF-A] Query TSPD behavior with EHF >>>> >>>> Hi Dan, >>>> I am not sure if this is mentioned anywhere in any documents but I think >>>> EHF handlers should be able to preempt all execution contexts at lower ELs >>>> and lower ELs should never be able to mask such interrupts. >>>> If the behavioral expectation is set the implementation can be fixed. >>>> >>>> Thanks >>>> Sandeep >>>> >>>> On Thu, Sep 17, 2020 at 7:57 PM Dan Handley via TF-A <tf- >>>> a(a)lists.trustedfirmware.org> wrote: >>>>> >>>>> A correction... >>>>> >>>>>> -----Original Message----- >>>>>> From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Dan >>>>>> Handley via TF-A >>>>>> Sent: 17 September 2020 15:14 >>>>>>>> >>>>>>>> I want to handle something similar in OP-TEED along with EHF >>>>>>>> depending on >>>>>>> what is the expected behavior. >>>>>>>> >>>>>> Hmm, I thought OP-TEED was more like the >>>> TSP_NS_INTR_ASYNC_PREEMPT=0 >>>>>> case, where NS interrupts are routed to S-EL1 while processing a >>>>>> yielding SMC in S- EL1? Perhaps that's a better TSPD config for you to >>>> follow? >>>>>> >>>>> Sorry, if EL3_EXCEPTION_HANDLING=1 then obviously NS interrupts are >>>> routed to EL3 first, but the TSPD re-enables NS interrupts before handing >>>> over to the TSP to handle yielding calls, via a call to >>>> ehf_allow_ns_preemption. >>>>> >>>> >>>> Right, that is the case for yielding SMC handling where both NS interrupts >>>> and EL3/G0 interrupts can preempt the S_EL1/S_EL2 context. >>>> But I would expect the same routing model even for 'Fast SMC' unlike what is >>>> happening in TSPD. >>>> >>>>> Dan. >>>>> >>>>> -- >>>>> TF-A mailing list >>>>> TF-A(a)lists.trustedfirmware.org >>>>> https://lists.trustedfirmware.org/mailman/listinfo/tf-a >>>> -- >>>> TF-A mailing list >>>> TF-A(a)lists.trustedfirmware.org >>>> https://lists.trustedfirmware.org/mailman/listinfo/tf-a >> >> >> -- >> TF-A mailing list >> TF-A(a)lists.trustedfirmware.org >> https://lists.trustedfirmware.org/mailman/listinfo/tf-a > -- > TF-A mailing list > TF-A(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-a

5 years, 4 months

2
1
0 0

Re: [TF-A] Nailgun

by Joanna Farley

Hi Varun, The Arm security support pages provides official responses to questions related to security vulnerabilities. [https://developer.arm.com/support/arm-security-updates] Trustedfirmware.org provides Security Centre pages covering the security incident handling and vulnerability disclosure process for hosted projects. [https://developer.trustedfirmware.org/w/collaboration/security_center/] You can find information regarding Nailgun on the following Arm security support FAQ page [https://developer.arm.com/support/arm-security-updates/speculative-processo…]. If you have further questions then please email arm-security(a)arm.com<mailto:arm-security@arm.com> as mentioned in the Arm security support pages. Joanna From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Varun Wadekar via TF-A <tf-a(a)lists.trustedfirmware.org> Reply to: Varun Wadekar <vwadekar(a)nvidia.com> Date: Monday, 28 September 2020 at 21:53 To: "tf-a(a)lists.trustedfirmware.org" <tf-a(a)lists.trustedfirmware.org> Subject: [TF-A] Nailgun Hi, Recently, I learned about Nailgun [1] – leak information by snooping across privilege boundaries with the help of CoreSight. The proof of concept uses Raspberry Pi3 (uses Cortex A-53 CPUs) platform to demonstrate the exploit. Has anyone reviewed this attack and does it affect other Arm v8 CPUs too? Do we have support in TF-A to disable CoreSight to mitigate against such attacks? Are there any other mitigations against this attack? -Varun [1] https://github.com/ningzhenyu/nailgun

5 years, 4 months

2
1
0 0

2026

2025

2024

2023

2022

2021

2020

2019

2018

TF-A