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TF-A Tech Forum on July 10th 2025 - SMC Fuzzing

by Olivier Deprez

Hi, In the TF-A Tech Forum on July 10th 2025 Mark Dykes from Arm TF-A team will present the topic of SMC Fuzzing with the agenda: Overview of the TF-A fuzzer and its basic implementation in practice. Regards, Olivier. TF-A Tech Forum Thursday Jul 10, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org

2 days, 11 hours

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MISRA Compliance: Request to consider filing deviation for 11.1 (Function Pointer Conversions) in TF-A

by Dhruva Gole

Hello, Background & Justification: MISRA C:2012 Rule 11.1 forbids the conversion from a function pointer to any other type. However, in the context of TF-A, we encounter scenarios where this conversion is necessary and performed with full knowledge of the target architecture and toolchain behavior. A prominent example is in low-level platform code, such as transferring control between bootloader stages or passing function entry points for CPU/core bring-up, where the conversion is unavoidable and well-understood. One such example is the K3 PSCI driver [1] where we pass the k3_sec_entrypoint which is of type uintptr_t, to the ti_sci_proc_set_boot_cfg function where the parameter is of type uint64_t. Another place that triggered the discussions behind this MISRA C issue was the TI AM62L PSCI driver [2] that needs a 16b aligned function pointer. We don't have to go into specific case by case discussion of solving these issues, but just wanted to share example use cases of function pointer conversion. Request: I propose we formally document a project-wide MISRA C:2012 Rule 11.1 deviation, reflecting current and future usage throughout the TF-A codebase. This deviation allows us to balance MISRA objectives with the practical and architectural necessities of TF-A development. Rationale: * Conversions between function pointers and other types are essential in several parts of the TF-A codebase, not limited to one module or file. * Platform-specific code (e.g., power management, bootloader hand-offs) relies on this pattern for correct operation. References: [1] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/ti/k3… [2] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/ti/k3… -- Best regards, Dhruva Gole Texas Instruments Incorporated

3 days, 15 hours

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Context uninitialized assertion failure in xlat_tables_core for ZynqMP

by Michał Kruszewski

Hello, I want to boot Linux on ZynqMP (XCZU15EG). I follow the standard procedure. I have generated FSBL using Vitis. I have compiled bl31 (tag: xilinx-v2025.1). I have a standard boot.bif configuration looking as follows: the_ROM_image: { [bootloader] fsbl.elf [pmufw_image] pmufw.elf [destination_cpu = a53-0, exception_level= el-3, trustzone] bl31.bin [destination_cpu = a53-0, exception_level= el-2, load = 0x10000000] images/u-boot.bin } However, the bl31 reports the following error during the handoff to u-boot: ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:788 BACKTRACE: START: assert 0: F_FUNCTION: 0x2880 1: F_FUNCTION: 0x4cac 2: F_FUNCTION: 0x2628 3: F_FUNCTION: 0x36e0 4: F_FUNCTION: 0x108 5: F_FUNCTION: 0xfffcd8e8 BACKTRACE: END: assert This is an assertion for context being uninitialized in the mmap_add_region_ctx function. /* Static regions must be added before initializing the xlat tables. */ assert(!ctx->initialized); Does anyone have any idea what might be wrong? Best regards, Michał Kruszewski Sent with [Proton Mail](https://proton.me/mail/home) secure email.

3 days, 17 hours

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Canceled event with note: TF-A Tech Forum @ Thu Jul 24, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling the TF-A tech forum on Jul 24th , as no topic planned. Regards, Olivier." TF-A Tech Forum Thursday Jul 24, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 week, 4 days

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TF-A Tech Forum on June 26th 2025 - Building Modern Industrial SoC Support in Arm Trusted Firmware

by Olivier Deprez

Hi, In the TF-A Tech forum on June 26th 2025 Dhruva Gole from Texas Instruments will present: Building Modern Industrial SoC Support in Arm Trusted Firmware Pragmatic Approaches to Power and Clock Management Regards, Olivier. TF-A Tech Forum Thursday Jun 26, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org

2 weeks, 1 day

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Trusted Firmware-A LTS v2.12.4 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.12.4 is now available. This release contains the following patches: e21418b78 feat(errata): implement workaround for DSU-120 erratum 2900952 [1] 648b4f34f fix(cpus): remove accidental alto cpu addition [2] 68453765e feat(cpus): update cpu_check_csv2 check [3] [1] https://review.trustedfirmware.org/q/I87aa440ab5c35121aff703032f5cf7a62d0b0… [2] https://review.trustedfirmware.org/q/I04cb5394a8caf32a69775e6236cb9c09aadf7… [3] https://review.trustedfirmware.org/q/I8473047ed4ad759b7b506161a76774ac21555… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.4/change-log.html Thanks, TF-A LTS team

3 weeks

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Trusted Firmware-A LTS v2.10.18 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.18 is now available. This release contains the following patches: 7323c2d9d feat(errata): implement workaround for DSU-120 erratum 2900952 [1] 39e7f4a7c feat(cpus): update cpu_check_csv2 check [2] [1] https://review.trustedfirmware.org/q/I87aa440ab5c35121aff703032f5cf7a62d0b0… [2] https://review.trustedfirmware.org/q/I8473047ed4ad759b7b506161a76774ac21555… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.18/change-log.html Thanks, TF-A LTS team

3 weeks

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Trusted Firmware-A LTS v2.8.34 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.34 is now available. This release contains the following patches: 3a299d0bf feat(errata): implement workaround for DSU-120 erratum 2900952 [1] ae330d547 feat(cpus): update cpu_check_csv2 check [2] [1] https://review.trustedfirmware.org/q/I87aa440ab5c35121aff703032f5cf7a62d0b0… [2] https://review.trustedfirmware.org/q/I8473047ed4ad759b7b506161a76774ac21555… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.34/change-log.html Thanks, TF-A LTS team

3 weeks

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TF-A - sError Queries

by Jaiprakash Singh

Hi, I have below queries regarding nested sError handling in TF-A, please help. 1. While handling exceptions in EL3, sError is almost unmask most of the time. Any specific reason to keep sError unmasked? For example, while handing nested sError, we can keep sError masked in serror_sp_elx. So that no further sError comes to EL3. And unmask sError when returning to lower ELs. Do you think this will create any problem in the system? 1. In system, sError can happen at any time. At EL3, we have nested sError handling in serror_sp_elx. Do you think we should have similar nested sError handling in serror_sp_el0? If not, what is the reason? 1. Double fault will always lead to unhandled exception. * Can someone help define double fault scenario? * What is the purpose of this patch - https://github.com/ARM-software/arm-trusted-firmware/commit/c72200357aed49f…<https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_ARM-2Dsoftw…> Is purpose only to save esr_el3 register? Thanks Regards, Jaiprakash IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

3 weeks

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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 5 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 5 of 5 defect(s) ** CID 472149: Integer handling issues (NEGATIVE_RETURNS) _____________________________________________________________________________________________ *** CID 472149: Integer handling issues (NEGATIVE_RETURNS) /lib/psci/psci_main.c: 300 in psci_affinity_info() 294 * - the cluster was removed from coherency as part of the CPU shutdown 295 * 296 * In this case the cache maintenace that was performed as part of the 297 * target CPUs shutdown was not seen by the current CPU's cluster. And 298 * so the cache may contain stale data for the target CPU. 299 */ >>> CID 472149: Integer handling issues (NEGATIVE_RETURNS) >>> "target_idx" is passed to a parameter that cannot be negative. 300 flush_cpu_data_by_index(target_idx, 301 psci_svc_cpu_data.aff_info_state); 302 303 return psci_get_aff_info_state_by_idx(target_idx); 304 } 305 ** CID 472148: Memory - corruptions (OVERRUN) _____________________________________________________________________________________________ *** CID 472148: Memory - corruptions (OVERRUN) /lib/psci/psci_main.c: 39 in psci_cpu_on() 33 34 /* Validate the target CPU */ 35 if (!is_valid_mpidr(target_cpu)) { 36 return PSCI_E_INVALID_PARAMS; 37 } 38 >>> CID 472148: Memory - corruptions (OVERRUN) >>> Overrunning callee's array of size 2 by passing argument "target_idx" (which evaluates to 4294967295) in call to "_cpu_data_by_index". 39 ep = get_cpu_data_by_index(target_idx, warmboot_ep_info); 40 /* Validate the lower EL entry point and put it in the entry_point_info */ 41 rc = psci_validate_entry_point(ep, entrypoint, context_id); 42 if (rc != PSCI_E_SUCCESS) { 43 return rc; 44 } ** CID 472147: (OVERRUN) _____________________________________________________________________________________________ *** CID 472147: (OVERRUN) /lib/psci/psci_main.c: 300 in psci_affinity_info() 294 * - the cluster was removed from coherency as part of the CPU shutdown 295 * 296 * In this case the cache maintenace that was performed as part of the 297 * target CPUs shutdown was not seen by the current CPU's cluster. And 298 * so the cache may contain stale data for the target CPU. 299 */ >>> CID 472147: (OVERRUN) >>> Overrunning callee's array of size 2 by passing argument "target_idx" (which evaluates to 4294967295) in call to "_cpu_data_by_index". 300 flush_cpu_data_by_index(target_idx, 301 psci_svc_cpu_data.aff_info_state); 302 303 return psci_get_aff_info_state_by_idx(target_idx); 304 } 305 /lib/psci/psci_main.c: 303 in psci_affinity_info() 297 * target CPUs shutdown was not seen by the current CPU's cluster. And 298 * so the cache may contain stale data for the target CPU. 299 */ 300 flush_cpu_data_by_index(target_idx, 301 psci_svc_cpu_data.aff_info_state); 302 >>> CID 472147: (OVERRUN) >>> Overrunning callee's array of size 2 by passing argument "target_idx" (which evaluates to 4294967295) in call to "psci_get_aff_info_state_by_idx". 303 return psci_get_aff_info_state_by_idx(target_idx); 304 } 305 306 int psci_migrate(u_register_t target_cpu) 307 { 308 int rc; ** CID 472146: Memory - corruptions (OVERRUN) _____________________________________________________________________________________________ *** CID 472146: Memory - corruptions (OVERRUN) /lib/el3_runtime/aarch64/context_debug.c: 107 in report_allocated_memory() 101 if (is_ctx_pauth_supported()) { 102 PRINT_SINGLE_MEM_USAGE_SEP_BLOCK(); 103 } 104 105 PRINT_MEM_USAGE_SEPARATOR(); 106 >>> CID 472146: Memory - corruptions (OVERRUN) >>> Overrunning callee's array of size 2 by passing argument "i" (which evaluates to 7) in call to "cm_get_context_by_index". 107 cpu_context_t *ctx = (cpu_context_t *)cm_get_context_by_index(i, 108 security_state_idx); 109 core_total = sizeof(*ctx); 110 el3_size = sizeof(ctx->el3state_ctx); 111 gp_size = sizeof(ctx->gpregs_ctx); 112 size_other = core_total - (el3_size + gp_size); ** CID 472145: Integer handling issues (NEGATIVE_RETURNS) _____________________________________________________________________________________________ *** CID 472145: Integer handling issues (NEGATIVE_RETURNS) /lib/psci/psci_main.c: 39 in psci_cpu_on() 33 34 /* Validate the target CPU */ 35 if (!is_valid_mpidr(target_cpu)) { 36 return PSCI_E_INVALID_PARAMS; 37 } 38 >>> CID 472145: Integer handling issues (NEGATIVE_RETURNS) >>> "target_idx" is passed to a parameter that cannot be negative. 39 ep = get_cpu_data_by_index(target_idx, warmboot_ep_info); 40 /* Validate the lower EL entry point and put it in the entry_point_info */ 41 rc = psci_validate_entry_point(ep, entrypoint, context_id); 42 if (rc != PSCI_E_SUCCESS) { 43 return rc; 44 } ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

3 weeks

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