- TF-A - lists.trustedfirmware.org

by Ramon Fried

Hi. I'm trying to run on our new platform Linux as BL33, preloaded to DDR. currently simulated over QEMU. I think that BL31 started BL33 in EL0, which cause problems: QEMU outputs this message: (complete log below) Exception return from AArch64 EL3 to AArch64 EL0 PC 0x800080000 What could I have done wrong in the configuration that caused it ? What should I check ? Thanks ! Ramon. NOTICE: Booting Trusted Firmware NOTICE: BL1: v2.5(debug):v2.5-61-g84d7d6a30-dirty NOTICE: BL1: Built : 14:53:02, Nov 21 2021 INFO: BL1: RAM 0x15500000 - 0x15513000 WARNING: BL1: neoverse_n1: CPU workaround for 1946160 was missing! INFO: BL1: Loading BL2 INFO: Using mmap INFO: Using FIP INFO: Loading image id=1 at address 0x14300000 INFO: Image id=1 loaded: 0x14300000 - 0x143052d1 INFO: bl1_mem_layout->total_base = 0x14000000x NOTICE: BL1: Booting BL2 INFO: Entry point address = 0x14300000 INFO: SPSR = 0x3c5 Exception return from AArch64 EL3 to AArch64 EL1 PC 0x14300000 INFO: BL1 inherited memory layout: 0x14000000 [size = 22020096] NOTICE: BL2: v2.5(debug):v2.5-61-g84d7d6a30-dirty NOTICE: BL2: Built : 14:53:02, Nov 21 2021 INFO: BL2: Skip loading image id 23 INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 INFO: Using mmap INFO: Using FIP INFO: Loading image id=3 at address 0x800000000 INFO: Image id=3 loaded: 0x800000000 - 0x8000080a9 INFO: BL2: Skip loading image id 5 Taking exception 13 [Secure Monitor Call] ...from EL1 to EL3 ...with ESR 0x17/0x5e000000 ...with ELR 0x14302a04 ...to EL3 PC 0x5400 PSTATE 0x3cd NOTICE: BL1: Booting BL31 INFO: Entry point address = 0x800000000 INFO: SPSR = 0x3cd Exception return from AArch64 EL3 to AArch64 EL3 PC 0x800000000 INFO: Boot BL33 from 0x800080000 for 0 Bytes NOTICE: BL31: v2.5(debug):v2.5-61-g84d7d6a30-dirty NOTICE: BL31: Built : 14:53:04, Nov 21 2021 INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: Maximum SPI INTID supported: 63 INFO: BL31: Initializing runtime services WARNING: BL31: neoverse_n1: CPU workaround for 1946160 was missing! INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x800080000 INFO: SPSR = 0x0 Exception return from AArch64 EL3 to AArch64 EL0 PC 0x800080000 Taking exception 1 [Undefined Instruction] ...from EL0 to EL1 ...with ESR 0x18/0x6232c061 ...with ELR 0x8000b7164 ...to EL1 PC 0x400 PSTATE 0x3c5 Taking exception 4 [Data Abort]

4 years, 1 month

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Canceled event with note: TF-A Tech Forum @ Thu Nov 18, 2021 4pm - 5pm (GMT) (tf-a@lists.trustedfirmware.org)

by joanna.farley＠arm.com

This event has been canceled with this note: "Cancelling TF-A Tech Forum this week as the team have nothing to present. We expect to have a topic for December 2nd." Title: TF-A Tech Forum We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr… Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location        +1 646 558 8656 US (New York)        +1 669 900 9128 US (San Jose)        877 853 5247 US Toll-free        888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h   When: Thu Nov 18, 2021 4pm – 5pm United Kingdom Time Calendar: tf-a(a)lists.trustedfirmware.org Who: * Bill Fletcher - creator * marek.bykowski(a)gmail.com * okash.khawaja(a)gmail.com * tf-a(a)lists.trustedfirmware.org Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this courtesy email at the account tf-a(a)lists.trustedfirmware.org because you are an attendee of this event. To stop receiving future updates for this event, decline this event. Alternatively you can sign up for a Google account at https://calendar.google.com/calendar/ and control your notification settings for your entire calendar. Forwarding this invitation could allow any recipient to send a response to the organizer and be added to the guest list, or invite others regardless of their own invitation status, or to modify your RSVP. Learn more at https://support.google.com/calendar/answer/37135#forwarding

4 years, 1 month

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Re: [TF-A] Missing CPU workaround warning message

by Varun Wadekar

Hi Pali, My understanding of the errata reporting mechanism is that some erratas are always checked during CPU boot. If the corresponding MACRO (ERRATA_A53_*) is disabled, then the ERRATA_MISSING code is reported. I would be concerned if the CPU is affected by the errata. If the errata needs to be enabled, the fix would be to enable the ERRATA_A53_* from the platform makefile. Hope this helps. -Varun -----Original Message----- From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Pali Rohár via TF-A Sent: Wednesday, July 7, 2021 9:11 PM To: Olivier Deprez <Olivier.Deprez(a)arm.com>; Bipin Ravi <Bipin.Ravi(a)arm.com>; tf-a(a)lists.trustedfirmware.org Cc: Konstantin Porotchkin <kostap(a)marvell.com>; Marek Behún <marek.behun(a)nic.cz> Subject: Re: [TF-A] Missing CPU workaround warning message External email: Use caution opening links or attachments Hello! Could somebody from TF-A helps with these two topics? I would really need to know if "missing errata warnings" debug message is some critical and needs to be fixed (and how?) or it is just a debug message and therefore should not be a warning... On Monday 28 June 2021 17:11:18 Pali Rohár wrote: > On Monday 28 June 2021 14:03:06 Olivier Deprez wrote: > > Hi, > > > > Is the question strictly related to this platform not implementing the mentioned errata (for which a platform change can be emitted)? > > Hello! The first question is if this is an issue that CPU workaround > is missing. And if yes (which seems to be) how big issue it is? And > how to resolve it? > > > Or is it more generally that those "missing errata warnings" are not printed in release mode? > > Assuming the latter, it looks to me it is the integrator mistake to not include the appropriate mitigations at development phase (hence while using debug mode for building TF-A). > > Then when the device is deployed (hence most often built for release mode), if this message is printed it is an indication for a malicious agent that such attack vector through mis-implemented errata is possible. So the consequence is possibly even worst than just "missing" to include the errata. > > > > Other TF-Aers (Bipin?) may have other opinions? > > And this is a second question. If missing CPU workaround is an issue, > should not be it printed also in release build? > > Also I see that in release builds are omitted not only messages about > missing CPU workarounds, but basically _all_ warning messages. But > notice messages are _not_ omitted. Which seems strange as in most > cases notice message has lower priority than warning message. > > > > > Regards, > > Olivier. > > > > ________________________________________ > > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of > > Pali Rohár via TF-A <tf-a(a)lists.trustedfirmware.org> > > Sent: 28 June 2021 15:36 > > To: tf-a(a)lists.trustedfirmware.org > > Cc: Konstantin Porotchkin; Marek Behún > > Subject: [TF-A] Missing CPU workaround warning message > > > > Hello! If TF-A for Marvell Armada 3720 platform is compiled in debug > > mode then at runtime it prints following warning messages: > > > > WARNING: BL1: cortex_a53: CPU workaround for 855873 was missing! > > WARNING: BL1: cortex_a53: CPU workaround for 1530924 was missing! > > > > These lines are not printed in non-debug mode. It is an issue? > > -- > > TF-A mailing list > > TF-A(a)lists.trustedfirmware.org > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli > > sts.trustedfirmware.org%2Fmailman%2Flistinfo%2Ftf-a&data=04%7C01 > > %7Cvwadekar%40nvidia.com%7Cb3605175f552468740e708d941836783%7C43083d > > 15727340c1b7db39efd9ccc17a%7C0%7C0%7C637612854914595696%7CUnknown%7C > > TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX > > VCI6Mn0%3D%7C1000&sdata=%2FW6HuFPYQCD5ECIA%2FZZxhm5ti5HYILNlsWTz > > moJ7L8E%3D&reserved=0 -- TF-A mailing list TF-A(a)lists.trustedfirmware.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.tru…

4 years, 1 month

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Re: [TF-A] PSCI lock contention

by Varun Wadekar

<Adding TF-A mailing list to the discussion> Thanks, Soby. I agree that this needs to be re-evaluated for platforms. I think we should introduce an option to disable them, if required. We plan to try some more experiments and hopefully remove the locks at least for Tegra platforms. Looking forward to the elaborate answer. From: Soby Mathew <Soby.Mathew(a)arm.com> Sent: Tuesday, 2 November 2021 10:18 AM To: Varun Wadekar <vwadekar(a)nvidia.com>; Manish Pandey2 <Manish.Pandey2(a)arm.com>; Dan Handley <Dan.Handley(a)arm.com> Cc: Joanna Farley <Joanna.Farley(a)arm.com>; Matteo Carlini <Matteo.Carlini(a)arm.com> Subject: RE: PSCI lock contention External email: Use caution opening links or attachments Hi Varun, The short answer is that the locks are used to differentiate the last-CPU-to-suspend and similarly first-CPU-to-powerup at a given power domain level. Now, recent CPU features like DynamIQ means that we don't need to do this differentiation upto cluster level which TF-A hasn't optimized for yet AFAICS. I am happy to elaborate further , but could you please send the query to the TF-A mailing list as I would prefer this discussion to happen in the open if possible. Best Regards Soby Mathew From: Varun Wadekar <vwadekar(a)nvidia.com<mailto:vwadekar@nvidia.com>> Sent: 01 November 2021 20:14 To: Soby Mathew <Soby.Mathew(a)arm.com<mailto:Soby.Mathew@arm.com>>; Manish Pandey2 <Manish.Pandey2(a)arm.com<mailto:Manish.Pandey2@arm.com>>; Dan Handley <Dan.Handley(a)arm.com<mailto:Dan.Handley@arm.com>> Cc: Joanna Farley <Joanna.Farley(a)arm.com<mailto:Joanna.Farley@arm.com>>; Matteo Carlini <Matteo.Carlini(a)arm.com<mailto:Matteo.Carlini@arm.com>> Subject: PSCI lock contention Hi, We were trying performance benchmarking for CPU_SUSPEND on Tegra platforms. We take all CPU cores to CPU_SUSPEND and then wake them up with IPI - all at once and in serial order. From the numbers, we see that the CPUs powering up later take more time than the first one. We have narrowed the most time consumed to the PSCI locks - documented at docs/perf/psci-performance-juno.rst. Can you please help me understand why these locks were added? As a quick experiment we tried the same benchmarking *without* the locks and the firmware does not blow up, but I would like to understand the impact from the analysis on Juno (docs/perf/psci-performance-juno.rst) Happy to hop on a call to discuss further. Thanks. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 1 month

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Re: [TF-A] Trusted Firmware-A v2.6 release activities in November

by Joanna Farley

TF-A Community, Just a reminder we are looking to freeze the tree for release activities starting Monday. Thanks Joanna From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Joanna Farley via TF-A <tf-a(a)lists.trustedfirmware.org> Reply to: Joanna Farley <Joanna.Farley(a)arm.com> Date: Monday, 1 November 2021 at 12:41 To: Joanna Farley via TF-A <tf-a(a)lists.trustedfirmware.org> Subject: [TF-A] Trusted Firmware-A v2.6 release activities in November TF-A Community, This is to notify that we are planning to target the Trusted Firmware-A 2.6 release during the fourth week of Nov 2021 as part of the regular 6 month cadence. The aim is to consolidate all TF-A work since the 2.5 release. As part of this, a release candidate tag will be created and release activities will commence from 15th November 2021 across all TF-A repositories. Essentially we will not merge any major enhancements from this date until the release is made. Please ensure any patches desired to make the 2.6 release are submitted in good time to be complete by 12th November 2021. Any major enhancement patches still open after that date will not be merged until after the release. This will involve the various repositories making up the broader TF-A project including the TF-A mainline, TF-A Tests, Hafnium, TF-A CI Scripts and TF-A CI Jobs. We will endeavour minimise the disruption on patch merging and complete release activities ASAP after we start. Thanks Joanna

4 years, 1 month

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Canceled event with note: TF-A Tech Forum @ Thu Nov 4, 2021 4pm - 5pm (GMT) (tf-a@lists.trustedfirmware.org)

by joanna.farley＠arm.com

This event has been canceled with this note: "No TF-A Tech Forum scheduled this week so cancelling." Title: TF-A Tech Forum We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr… Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location        +1 646 558 8656 US (New York)        +1 669 900 9128 US (San Jose)        877 853 5247 US Toll-free        888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h   When: Thu Nov 4, 2021 4pm – 5pm United Kingdom Time Calendar: tf-a(a)lists.trustedfirmware.org Who: * Bill Fletcher - creator * marek.bykowski(a)gmail.com * okash.khawaja(a)gmail.com * tf-a(a)lists.trustedfirmware.org Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this courtesy email at the account tf-a(a)lists.trustedfirmware.org because you are an attendee of this event. To stop receiving future updates for this event, decline this event. Alternatively you can sign up for a Google account at https://calendar.google.com/calendar/ and control your notification settings for your entire calendar. Forwarding this invitation could allow any recipient to send a response to the organizer and be added to the guest list, or invite others regardless of their own invitation status, or to modify your RSVP. Learn more at https://support.google.com/calendar/answer/37135#forwarding

4 years, 1 month

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FW: Two issues in Qemu port docs

by Joanna Farley

Forwarded on to TF-A Mail list. Seems postings from people with gmail.com email domains get automatically rejected, sorry Ramon not sure if that can be addressed. Joanna On 03/11/2021, 14:20, "Ramon Fried" <rfried.dev(a)gmail.com> wrote: Hi. I'm trying to run the example in TF-A documentation. I found two problems. First, the files: "tee-header_v2.bin, tee-pager_v2.bin, tee-pageable_v2.bin" are not provided as binary downloads, and instructions on how to get them are missing. turn's out you need to build optee, but this step is skipped if you choose to download the QEMU_EFI.fd from Linaro. Second, after following the instructions step by step resulted in the following error: qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 -kernel Image -no-acpi -append 'console=ttyAMA0,38400 keep_bootcon' -initrd rootfs.cpio.gz -smp 2 -m 1024 -bios flash.bin -d unimp NOTICE: Booting Trusted Firmware NOTICE: BL1: v2.5(release):v2.5-60-g7737fdf0e NOTICE: BL1: Built : 13:12:39, Nov 3 2021 NOTICE: BL1: Booting BL2 NOTICE: BL2: v2.5(release):v2.5-60-g7737fdf0e NOTICE: BL2: Built : 13:12:42, Nov 3 2021 NOTICE: BL1: Booting BL31 NOTICE: BL31: v2.5(release):v2.5-60-g7737fdf0e NOTICE: BL31: Built : 13:12:45, Nov 3 2021 read access to unsupported AArch64 system register op0:3 op1:0 crn:12 crm:12 op2:4 This occurs on Qemu 5.0 and also 6.0 Thanks, Ramon.

4 years, 1 month

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Trusted Firmware-A v2.6 release activities in November

by Joanna Farley

TF-A Community, This is to notify that we are planning to target the Trusted Firmware-A 2.6 release during the fourth week of Nov 2021 as part of the regular 6 month cadence. The aim is to consolidate all TF-A work since the 2.5 release. As part of this, a release candidate tag will be created and release activities will commence from 15th November 2021 across all TF-A repositories. Essentially we will not merge any major enhancements from this date until the release is made. Please ensure any patches desired to make the 2.6 release are submitted in good time to be complete by 12th November 2021. Any major enhancement patches still open after that date will not be merged until after the release. This will involve the various repositories making up the broader TF-A project including the TF-A mainline, TF-A Tests, Hafnium, TF-A CI Scripts and TF-A CI Jobs. We will endeavour minimise the disruption on patch merging and complete release activities ASAP after we start. Thanks Joanna

4 years, 1 month

1
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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 3 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 3 of 3 defect(s) ** CID 373791: Control flow issues (DEADCODE) /drivers/usb/usb_device.c: 646 in usb_core_receive() ________________________________________________________________________________________________________ *** CID 373791: Control flow issues (DEADCODE) /drivers/usb/usb_device.c: 646 in usb_core_receive() 640 ep->is_in = false; 641 ep->num = num; 642 643 if (num == 0U) { 644 pdev->driver->ep0_start_xfer(hpcd->instance, ep); 645 } else { >>> CID 373791: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "(*pdev->driver->ep_start_xf...". 646 pdev->driver->ep_start_xfer(hpcd->instance, ep); 647 } 648 649 return USBD_OK; 650 } 651 ** CID 373790: Null pointer dereferences (FORWARD_NULL) /drivers/usb/usb_device.c: 182 in usb_core_set_config() ________________________________________________________________________________________________________ *** CID 373790: Null pointer dereferences (FORWARD_NULL) /drivers/usb/usb_device.c: 182 in usb_core_set_config() 176 } else if (cfgidx != pdev->dev_config) { 177 if (pdev->class != NULL) { 178 usb_core_ctl_error(pdev); 179 return; 180 } 181 /* Clear old configuration */ >>> CID 373790: Null pointer dereferences (FORWARD_NULL) >>> Dereferencing null pointer "pdev->class". 182 pdev->class->de_init(pdev, pdev->dev_config); 183 /* Set new configuration */ 184 pdev->dev_config = cfgidx; 185 /* Set configuration and start the USB class */ 186 if (pdev->class->init(pdev, cfgidx) != 0U) { 187 usb_core_ctl_error(pdev); ** CID 373789: Control flow issues (DEADCODE) /drivers/usb/usb_device.c: 684 in usb_core_transmit() ________________________________________________________________________________________________________ *** CID 373789: Control flow issues (DEADCODE) /drivers/usb/usb_device.c: 684 in usb_core_transmit() 678 ep->is_in = true; 679 ep->num = num; 680 681 if (num == 0U) { 682 pdev->driver->ep0_start_xfer(hpcd->instance, ep); 683 } else { >>> CID 373789: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "(*pdev->driver->ep_start_xf...". 684 pdev->driver->ep_start_xfer(hpcd->instance, ep); 685 } 686 687 return USBD_OK; 688 } 689 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

4 years, 1 month

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ARM Trusted memory Resolution

by IS20 Boaz Baron

Hi all, What is the resolution for secure memory space with the Trust zone? Is it dependent on the MMU resolution? Means, for example, If my MMU can set a range of 16 KB so can I set that range as a trusted zone as well? P.S. I have ARM A35 (I am not sure but I think my MMU supports a resolution of 32KB) You are welcome to comment if I have any mistakes Thanks a lot, Boaz. ________________________________ The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

4 years, 2 months

1
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