TL;DR: move Mandatory features to be runtime checked (value 2)
Month ago there was changeset from Govindraj Raja merged [1]. The plan
was to enable all mandatory features based on architecture version set
by plaform (using ARM_ARCH_{MAJOR,MINOR} variables).
1. https://review.trustedfirmware.org/q/topic:%22gr/build_refactor%22
The idea is nice. But only for final products. If you are working on
silicon bring up or on virtualization platform (QEMU or other) then you
got hit badly...
I am working on SBSA Reference Platform in QEMU. It can have one of
several cpu models. From old v8.0 cores up to v9.0 ones. And then there
is also 'max' core which cannot be mapped to any architecture level
because it contains all Arm cpu features QEMU can emulate. We need to
support all of them in one TF-A binary. Whenever something fails we
have some cpu cores in non-bootable state.
We had to enable FGT to get 'max' boot Linux. Now we have to move DIT to
be runtime checked to boot anything below Neoverse-V1 at all. And HCX to
get 'max' boot Linux again.
At current state of TF-A we cannot handle it. Toplevel Makefile includes
platform.mk which sets ARM_ARCH_{MAJOR,MINOR} and then
make_helpers/arch_features.mk enables mandatory options by setting them
to value "1" which means "present, no need to check".
Due to this we have those changes in Gerrit:
DIT: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/24870
TRF: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/23648
And instead of sending another one to switch FGT, RNG and HCX I decided
to write this email.
I have spent half of day today bisecting TF-A, booting several tools and
operating systems to check how we are and where the problem is. Still
have to get Neoverse-N2 booting properly but other than then I got to
the point where all cpu cores boot into Linux.
We need to change make_helpers/arch_features.mk to stop enabling mandatory
features as "present, no need to check" (value '1') but to use runtime
check (value '2') instead. This way any platform which contains CPU not
yet fully developed can boot TF-A. Or platform where one firmware can boot
different cpu models.
I am sorry that I bring it so late in release cycle but was unable to use
computer for a development for some time.
We have executed below command on terminal to get stack size using ARMCLANG compiler. but we are getting "undefined symbol".
armclang --target=arm-arm-none-eabi -march=armv8-a -c -g file.c -o file.o
armlink file.o --info=stack
armlink file.o --callgraph -o FileImage.axf
Could anyone answer me that how to get stack size using ARMCLANG compiler for TFA code.
This event has been canceled with a note:
"Hi, Cancelling this week as no topic. Thanks & Regards, Olivier."
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Hello,
Trusted Firmware-A LTS version 2.8.11 is now available. This release contains the workarounds for CPU errata, platform errata, and fixes for Versal/Versal-NET security vulnerabilities.
The complete list of changes can be found here<https://ci-builds.trustedfirmware.org/static-files/NdY070C96xYcXq0KeqQzbFaI…>.
Thanks.
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
3 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 3 of 3 defect(s)
** CID 405370: Memory - illegal accesses (OVERRUN)
/lib/psci/psci_stat.c: 210 in psci_get_stat()
________________________________________________________________________________________________________
*** CID 405370: Memory - illegal accesses (OVERRUN)
/lib/psci/psci_stat.c: 210 in psci_get_stat()
204 /* Get the index into the stats array */
205 local_state = state_info.pwr_domain_state[pwrlvl];
206 stat_idx = get_stat_idx(local_state, pwrlvl);
207
208 if (pwrlvl > PSCI_CPU_PWR_LVL) {
209 /* Get the power domain index */
>>> CID 405370: Memory - illegal accesses (OVERRUN)
>>> Overrunning array "psci_cpu_pd_nodes" of 16 16-byte elements at element index 4294967295 (byte offset 68719476735) using index "target_idx" (which evaluates to 4294967295).
210 parent_idx = SPECULATION_SAFE_VALUE(psci_cpu_pd_nodes[target_idx].parent_node);
211 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl < pwrlvl; lvl++)
212 parent_idx = SPECULATION_SAFE_VALUE(psci_non_cpu_pd_nodes[parent_idx].parent_node);
213
214 /* Get the non cpu power domain stats */
215 *psci_stat = psci_non_cpu_stat[parent_idx][stat_idx];
** CID 405369: Memory - illegal accesses (OVERRUN)
/lib/psci/psci_stat.c: 218 in psci_get_stat()
________________________________________________________________________________________________________
*** CID 405369: Memory - illegal accesses (OVERRUN)
/lib/psci/psci_stat.c: 218 in psci_get_stat()
212 parent_idx = SPECULATION_SAFE_VALUE(psci_non_cpu_pd_nodes[parent_idx].parent_node);
213
214 /* Get the non cpu power domain stats */
215 *psci_stat = psci_non_cpu_stat[parent_idx][stat_idx];
216 } else {
217 /* Get the cpu power domain stats */
>>> CID 405369: Memory - illegal accesses (OVERRUN)
>>> Overrunning array "psci_cpu_stat" of 16 32-byte elements at element index 4294967295 (byte offset 137438953471) using index "target_idx" (which evaluates to 4294967295).
218 *psci_stat = psci_cpu_stat[target_idx][stat_idx];
219 }
220
221 return PSCI_E_SUCCESS;
222 }
223
** CID 405368: (NEGATIVE_RETURNS)
/lib/psci/psci_stat.c: 210 in psci_get_stat()
/lib/psci/psci_stat.c: 218 in psci_get_stat()
________________________________________________________________________________________________________
*** CID 405368: (NEGATIVE_RETURNS)
/lib/psci/psci_stat.c: 210 in psci_get_stat()
204 /* Get the index into the stats array */
205 local_state = state_info.pwr_domain_state[pwrlvl];
206 stat_idx = get_stat_idx(local_state, pwrlvl);
207
208 if (pwrlvl > PSCI_CPU_PWR_LVL) {
209 /* Get the power domain index */
>>> CID 405368: (NEGATIVE_RETURNS)
>>> Using variable "target_idx" as an index to array "psci_cpu_pd_nodes".
210 parent_idx = SPECULATION_SAFE_VALUE(psci_cpu_pd_nodes[target_idx].parent_node);
211 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl < pwrlvl; lvl++)
212 parent_idx = SPECULATION_SAFE_VALUE(psci_non_cpu_pd_nodes[parent_idx].parent_node);
213
214 /* Get the non cpu power domain stats */
215 *psci_stat = psci_non_cpu_stat[parent_idx][stat_idx];
/lib/psci/psci_stat.c: 218 in psci_get_stat()
212 parent_idx = SPECULATION_SAFE_VALUE(psci_non_cpu_pd_nodes[parent_idx].parent_node);
213
214 /* Get the non cpu power domain stats */
215 *psci_stat = psci_non_cpu_stat[parent_idx][stat_idx];
216 } else {
217 /* Get the cpu power domain stats */
>>> CID 405368: (NEGATIVE_RETURNS)
>>> Using variable "target_idx" as an index to array "psci_cpu_stat".
218 *psci_stat = psci_cpu_stat[target_idx][stat_idx];
219 }
220
221 return PSCI_E_SUCCESS;
222 }
223
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
This event has been canceled with a note:
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Regards, Olivier."
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Hi there
We recently got our first batch of i.MX 8M Plus QuadLite based SoMs. While NXP downstream works just fine on
them they just hang booting with latest upstream U-Boot (and TF-A). Replacing TF-A with the downstream NXP one
made upstream U-Boot work as well. Further debugging TF-A showed imx_gpc_pm_domain_enable() to be the culprit.
Looking more specifically I discovered the following so far downstream-only commit [1]. So it looks like in
downstream NXP is limiting the to-be-enabled power management domains to HSIOMIX, USB1_PHY and USB2_PHY.
Anybody knows why exactly this is done and why this got never upstreamed?
Thank you very much for any insights into this matter.
[1] https://github.com/nxp-imx/imx-atf/commit/47759cfca10b2286a218062915d4a2808…
Cheers
Marcel