Hello,
QEMU 8.1 added support for FEAT_RME. It is experimental, enabled with
'-cpu max,x-rme=on', and requires fixes that will be available in QEMU
8.2. I'm working on adding support to TF-A and TF-RMM.
I just submitted some TF-A patches for review (topic qemu-rme) that enable
the feature for the virt platform, and intend to send the necessary
changes for TF-RMM within a week or so. Without RMM, the Test Realm
Payload is included into the FIP for light testing.
After the TF-A and TF-RMM changes, I'd like to add support for the SBSA
platform as well, which should be a relatively small change once the
common QEMU support is merged.
Thanks,
Jean
---
Building TF-A for QEMU with RME support:
make -j CROSS_COMPILE=aarch64-linux-gnu- PLAT=qemu DEBUG=1
RMM=path/to/rmm/build/Debug/rmm.img ENABLE_RME=1
BL33=path/to/QEMU_EFI.fd QEMU_USE_GIC_DRIVER=QEMU_GICV3
all fip
dd if=tf-a/build/qemu/debug/bl1.bin of=flash.bin bs=4096 conv=notrunc
dd if=tf-a//build/qemu/debug/fip.bin of=flash.bin seek=64 bs=4096 conv=notrunc
Running QEMU, for example:
qemu-system-aarch64 -cpu max,x-rme=on,sme=off -m 3G -smp 8
-M virt,gic-version=3,virtualization=on,secure=on,acpi=off
-bios flash.bin
-kernel linux/arch/arm64/boot/Image
-initrd path/to/initrd
-append console=ttyAMA0
-nographic
...
[ 0.825891] kvm [1]: Using prototype RMM support (version 66.0)
SMC_RMM_FEATURES 0 > RMI_SUCCESS 33403e30
Hi all,
I find that the latest Arm A-profile manual (DDI0487_J_a) mention
several registers/instructions related to memory encryption (e.g.,
MECID-related registers). So can I ask two questions about it?
1. Is the FVP (I use the Base RevC AEM) support Memory Encryption
Context (MEC) and Memory Protection Engine (MPE)? They are critical to
memory encryption. If no, do we have some solutions to simulate them
and verify memory encryption?
2. Does current TF-A support managing MPE, or other hardware related
to memory encryption?
Besides that, one problem for curiosity (only related to FVP).
3. I find some PCI-E device can use hardware encryption (example,
NVIDIA H100 GPU). Can we attach this device to FVP's PCI-E port?
Assume it has already connected to my Host PC via PCI-E.
Sincerely,
WANG Chenxu
Hi All,
Note you may have received another instance of this note but when I
attempted to send to all TF ML's simultaneously it seemed to fail, so
sending to each one at a time. Sorry about that. :/
We've created a Discord Server for real time chats/sharing. This solution
comes at no cost to the project, is set up with channels for each project,
includes a #general channel, and supports direct 1-1 chats between members,
all with the goal of improving collaboration between trustedfirmware.org
developers.
We encourage all to join! :) Instructions for joining can be found on
the TF.org
FAQ page <https://www.trustedfirmware.org/faq/>.
See you all there and please don't hesitate to reach out if you have any
questions!
Don Harbin
TrustedFirmware Community Manager
don.harbin(a)linaro.org
It is observed that several unused functions are present in Trusted Firmware-A code, is it possible to mask those unused functions or leave them as it is to fix MISRA-C Violations? If these functions are not appearing in symbol table, then no need to take actions on violations reported in these functions? Please suggest.
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Hi All,
SCR_EL3.EA define whether to route External Abort and SError Interrupt to EL3 or EL2/1. ATF have a compile time flag to HANDLE_EA_EL3_FIRST_NS to program SCR_EL3.EA.
Below text from ATF documentation.
- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError
Interrupts, resulting from errors in NS world, will be always trapped in
EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions
will be trapped in the current exception level (or in EL1 if the current
exception level is EL0).
Have question related to forwarding of these errors when External Abort and SError Interrupt are routed to EL3.
In this case will ATF forward Asynchronous SError Interrupt to Linux via RAS?
Thanks
-Bharat