Hello,
Recently I wondered who was the Code-Owner of the files in this patch:
fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32
(https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27162)
By the way it still doesn't have the Code-Owner review vote ;-)
But that triggered a more generic question about files and directories
in docs/about/maintainers.rst: are all the paths listed here reflect all
the files in TF-A repository?
The answer is unfortunately no.
I've then ended up writing some shell commands to try to list
unmaintained files:
for p in $(grep ^':|F|' docs/about/maintainers.rst | cut -d" " -f2 |
grep ^[a-zA-Z] | grep -v "drivers/nuvoton" | sed "s;\\\;;g"); do find $p
-type f >> /tmp/find_tf-a_maintained_files.txt; done; sort -u -o
/tmp/find_tf-a_maintained_files.txt{,}; git ls-files | sort -u >
/tmp/tf-a_files.txt; diff /tmp/find_tf-a_maintained_files.txt
/tmp/tf-a_files.txt > /tmp/tf-a_unmaintained_files.txt
Some are easy to correct, e.g. some docs/plat/<platform> files should be
added to the list of files for a given <platform>. Or some
include/drivers paths missing. I may push some patches for this if I
can. The drivers/nuvoton path is listed but it doesn't exist.
Some platforms or drivers are completely missing, and that would be good
their maintainers add a chapter for them.
But some generic & core files are also not listed. The goal of this mail
is to open the discussion about that.
That could be tricky as maintainer may change.
But all of that would ease the contributors way of working.
I've also seen that gerrit automatically adds Code-Owner for the review.
So it seems there is another list for that, and we could somehow try to
align those 2 lists.
Best regards,
Yann
We do nightly testing of our yocto layers against the latest kernel,
uboot, trusted-firmware-a, and optee. On April 12th we started getting
a build failure with trusted-firmware-a. I have tracked the issue down
to this commit:
https://github.com/ARM-software/arm-trusted-firmware/commit/71c42e98bbe900a…
Specifically, the line in make_helpers/utilities.mk:
escape-shell = '$(subst ','\'',$(1))'
On the surface it feels like the ' is overused and might cause issues.
I tried making the line:
escape-shell = $(subst ','\'',$(1))
And the builds went back to working properly. Does that seem like a
change that should be made, or was there a reason for the extra '' wrapper?
I have submitted a GitHub issue about this as well:
https://github.com/TrustedFirmware-A/trusted-firmware-a/issues/7
--
Ryan Eatmon reatmon(a)ti.com
-----------------------------------------
Texas Instruments, Inc. - LCPD - MGTS
Hi,
I'm upgrading the ATF I use from 2.4 to 2.8, and ran into a header
conflict. The change
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13806
introduced an inclusion of
include/drivers/arm/gicv3.h
in lib/el3_runtime/aarch64/context_mgmt.c, but in my build environment that
.c file also includes
include/drivers/arm/gicv2.h
so now I get macro redefinition of "INT_ID_MASK" errors when compiling. Is
it an error, that in my build environment the gicv2.h gets included ?
I've solved it locally by doing:
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c
b/lib/el3_runtime/aarch64/context_mgmt.c
index 866ac4154..395635a86 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -18,7 +18,9 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <context.h>
+#if CTX_INCLUDE_EL2_REGS
#include <drivers/arm/gicv3.h>
+#endif
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/el3_runtime/pubsub_events.h>
#include <lib/extensions/amu.h>
but I am not sure whether this is the correct fix or not, or if I am doing
something else wrong here. Any suggestions on what would be the correct fix
?
Regards
Jacob
Hi, In the TF-A Tech Forum on Apr 18th at 4.00pm BST, Javier Almansa
Sobrino will present the topic of TF-RMM Stage-1 Memory management, by his
own words: "This week's TF-A Tech Forum will present the TF-RMM Stage 1
Memory Management, where we will discuss the design of the TF-RMM memory
space as well as some implementation details and future work." Regards,
Olivier.
TF-A Tech Forum
Thursday Apr 18, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
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Guests
tf-a(a)lists.trustedfirmware.org
marek.bykowski(a)gmail.com
okash.khawaja(a)gmail.com
Hi ,
As I understand , there are separate page tables in MMU for EL2 and EL3 .
If a memory region is mapped as secure memory (MT_SECURE , MT_MEMORY, MT_RW) in bl31 code which runs in EL3 ,
and the same memory region is mapped again with same attributes (MT_SECURE , MT_MEMORY, MT_RW ) in EL2 , will EL2 be able to read and write to EL3 secure memory region ?
Regards
Amit
Hi,
I tried to follow the contribution guide but was unable to push the patch
to gerrit for review. "git review" just hangs with nothing happening.
The patch I want to push for review is:
From 198af98d05cfb4704aa2387eaa0a1e606a7968de Mon Sep 17 00:00:00 2001
From: Jacob Kroon <jacob.kroon(a)gmail.com>
Date: Fri, 12 Apr 2024 13:11:36 +0200
Subject: [PATCH] fix(gic): Fix SGIR_NSATT bitshift
See
https://documentation-service.arm.com/static/5f8ff196f86e16515cdbf969?token=
Fixes: dcb31ff79096fc88b45df8068e5de83b93f833ed
Signed-off-by: Jacob Kroon <jacob.kroon(a)gmail.com>
---
include/drivers/arm/gicv2.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index bebd9ceff..c7c441d78 100644
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -51,7 +51,7 @@
#define SGIR_TGTLSTFLT_MASK U(0x3)
#define SGIR_TGTLST_SHIFT 16
#define SGIR_TGTLST_MASK U(0xff)
-#define SGIR_NSATT (U(0x1) << 16)
+#define SGIR_NSATT (U(0x1) << 15)
#define SGIR_INTID_MASK ULL(0xf)
#define SGIR_TGT_SPECIFIC U(0)
--
2.39.2
Are there any suggestions on what I should do next ?
Regards
Jacob
