Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/287/

Failed Jobs: MUSCA_B1_ARMCLANG_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426828/ AN521_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426270/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426294/ AN521_GCC_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426295/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426297/ MUSCA_B1_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426301/ corstone315_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/426304/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426315/ MUSCA_B1_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426317/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426329/ MUSCA_B1_ARMCLANG_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426339/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426342/ AN521_GCC_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426421/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426428/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426457/ MUSCA_B1_GCC_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426476/ MUSCA_B1_GCC_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426501/ MUSCA_B1_GCC_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426568/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426574/ MUSCA_B1_ARMCLANG_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426591/ MUSCA_B1_GCC_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426681/ AN521_GCC_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426700/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426763/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426793/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426822/ corstone320_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/426829/ MUSCA_B1_ARMCLANG_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426830/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426834/ MUSCA_B1_GCC_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426836/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426864/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426980/ MUSCA_B1_ARMCLANG_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426397/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426564/ MUSCA_B1_ARMCLANG_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426621/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426724/ MUSCA_B1_ARMCLANG_3_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426877/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426900/ AN521_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426272/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426277/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426288/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426306/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426319/ MUSCA_B1_GCC_3_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426344/ MUSCA_B1_ARMCLANG_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426366/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426373/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426541/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426543/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426610/ AN521_ARMCLANG_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426698/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426812/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426892/ AN521_ARMCLANG_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426913/ AN521_GCC_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426486/ AN521_GCC_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426398/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426402/ AN521_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426419/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426434/ AN521_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426445/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426448/ MUSCA_B1_GCC_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426458/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426462/ MUSCA_B1_ARMCLANG_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426464/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426484/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426495/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426499/ MUSCA_B1_GCC_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426502/ MUSCA_B1_GCC_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426503/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426506/ MUSCA_B1_GCC_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426512/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426513/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426517/ MUSCA_B1_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426518/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426524/ MUSCA_B1_ARMCLANG_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426535/ MUSCA_B1_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426536/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426546/ MUSCA_B1_GCC_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426547/ MUSCA_B1_GCC_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426548/ MUSCA_B1_ARMCLANG_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426551/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426555/ AN521_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426558/ AN521_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426561/ MUSCA_B1_GCC_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426586/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426646/ MUSCA_B1_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426652/ MUSCA_B1_GCC_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426657/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426695/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426708/ MUSCA_B1_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426719/ corstone315_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/426735/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426740/ corstone315_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/426746/ MUSCA_B1_GCC_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426747/ MUSCA_B1_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426753/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426761/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426779/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426808/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426811/ corstone320_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/426842/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426844/ AN521_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426849/ corstone320_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/426852/ MUSCA_B1_GCC_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426861/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426868/ MUSCA_B1_ARMCLANG_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426872/ corstone320_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/426873/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426876/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426878/ MUSCA_B1_GCC_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426879/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426894/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426895/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426897/ MUSCA_B1_GCC_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426898/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426902/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426947/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426953/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426958/ MUSCA_B1_ARMCLANG_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426971/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426990/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426697/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426711/ AN521_GCC_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426768/ MUSCA_B1_GCC_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426940/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426612/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426643/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426649/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426658/ MUSCA_B1_GCC_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426662/ MUSCA_B1_GCC_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426670/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426687/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/426694/ MUSCA_B1_ARMCLANG_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426916/ AN521_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426588/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/426596/ MUSCA_B1_GCC_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426607/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/426625/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/426663/ MUSCA_B1_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/426668/ corstone315_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/426689/ psoc64_ARMCLANG_2_RegS_RegNS_Release https://ci.trustedfirmware.org/job/tf-m-build-config/426797/ psoc64_ARMCLANG_1_RegS_RegNS_Release https://ci.trustedfirmware.org/job/tf-m-build-config/426860/

For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/287/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/289/

Failed Jobs: MUSCA_B1_ARMCLANG_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428343/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428426/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428725/ MUSCA_B1_GCC_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428844/ corstone315_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/428335/ corstone315_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/428259/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428322/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428346/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428347/ AN521_GCC_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428349/ MUSCA_B1_GCC_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428362/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428371/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428379/ MUSCA_B1_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428420/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428839/ MUSCA_B1_ARMCLANG_3_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428841/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428248/ MUSCA_B1_GCC_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428268/ MUSCA_B1_ARMCLANG_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428278/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428284/ AN521_ARMCLANG_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428286/ MUSCA_B1_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428297/ AN521_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428314/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428318/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428341/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428357/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428404/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428431/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428494/ MUSCA_B1_GCC_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428795/ MUSCA_B1_ARMCLANG_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428816/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428843/ MUSCA_B1_GCC_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428903/ MUSCA_B1_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428785/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428246/ MUSCA_B1_ARMCLANG_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428305/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428325/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428273/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428295/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428300/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428307/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428311/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428332/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428354/ MUSCA_B1_GCC_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428359/ MUSCA_B1_ARMCLANG_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428369/ MUSCA_B1_ARMCLANG_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428403/ MUSCA_B1_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428405/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428442/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428450/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428463/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428464/ MUSCA_B1_GCC_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428466/ MUSCA_B1_GCC_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428478/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428522/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428539/ corstone320_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/428552/ MUSCA_B1_GCC_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428562/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428574/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428576/ AN521_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428578/ corstone320_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/428585/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428610/ AN521_ARMCLANG_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428616/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428626/ MUSCA_B1_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428628/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428630/ MUSCA_B1_GCC_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428631/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428632/ MUSCA_B1_ARMCLANG_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428635/ MUSCA_B1_GCC_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428639/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428732/ AN521_GCC_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428742/ MUSCA_B1_ARMCLANG_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428744/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428749/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428777/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428811/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428819/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428833/ AN521_GCC_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428834/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428840/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428842/ MUSCA_B1_GCC_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428857/ MUSCA_B1_GCC_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428860/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428862/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428880/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428912/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428916/ corstone320_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/428918/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428924/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428930/ AN521_GCC_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428821/ AN521_GCC_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428361/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428392/ MUSCA_B1_ARMCLANG_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428402/ MUSCA_B1_GCC_3_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428437/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428470/ AN521_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428524/ MUSCA_B1_ARMCLANG_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428600/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428763/ MUSCA_B1_ARMCLANG_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428803/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428848/ MUSCA_B1_GCC_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428856/ corstone315_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/428910/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428469/ MUSCA_B1_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428533/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428787/ MUSCA_B1_GCC_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428796/ MUSCA_B1_GCC_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428867/ MUSCA_B1_ARMCLANG_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428607/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428658/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428779/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428484/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428504/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/428598/ MUSCA_B1_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428678/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428711/ MUSCA_B1_GCC_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428721/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428773/ MUSCA_B1_GCC_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428774/ MUSCA_B1_GCC_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428932/ corstone315_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/428476/ MUSCA_B1_GCC_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428519/ AN521_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428582/ MUSCA_B1_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428653/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428656/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/428680/ AN521_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428708/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428931/ MUSCA_B1_GCC_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428765/ psoc64_ARMCLANG_1_RegS_RegNS_Release https://ci.trustedfirmware.org/job/tf-m-build-config/428358/ AN521_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428523/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428532/ psoc64_ARMCLANG_2_RegS_RegNS_Release https://ci.trustedfirmware.org/job/tf-m-build-config/428558/ AN521_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428587/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/428595/ AN521_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428605/ MUSCA_B1_ARMCLANG_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428637/ corstone320_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/428675/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/428698/ AN521_GCC_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/428706/

For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/289/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/291/

Failed Jobs: MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430160/ MUSCA_B1_GCC_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430162/ corstone315_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/430165/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430184/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430204/ MUSCA_B1_GCC_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430210/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430426/ AN521_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430506/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430566/ AN521_GCC_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430622/ corstone315_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/430639/ AN521_GCC_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430645/ MUSCA_B1_GCC_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430727/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430749/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430197/ AN521_ARMCLANG_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430217/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430257/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430279/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430287/ MUSCA_B1_GCC_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430491/ MUSCA_B1_ARMCLANG_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430692/ AN521_GCC_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430765/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430768/ AN521_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430804/ AN521_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430820/ psoc64_ARMCLANG_1_RegS_RegNS_Release https://ci.trustedfirmware.org/job/tf-m-build-config/430779/ MUSCA_B1_GCC_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430167/ AN521_GCC_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430198/ MUSCA_B1_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430200/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430218/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430235/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430273/ MUSCA_B1_GCC_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430297/ MUSCA_B1_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430319/ AN521_ARMCLANG_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430366/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430368/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430380/ MUSCA_B1_ARMCLANG_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430381/ MUSCA_B1_GCC_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430553/ MUSCA_B1_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430573/ corstone320_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/430577/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430597/ MUSCA_B1_GCC_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430599/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430619/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430699/ MUSCA_B1_ARMCLANG_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430704/ MUSCA_B1_GCC_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430707/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430725/ MUSCA_B1_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430735/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430743/ corstone320_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/430754/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430763/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430767/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430777/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430799/ MUSCA_B1_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430805/ MUSCA_B1_ARMCLANG_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430841/ psoc64_ARMCLANG_2_RegS_RegNS_Release https://ci.trustedfirmware.org/job/tf-m-build-config/430846/ MUSCA_B1_GCC_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430849/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430711/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430314/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430449/ MUSCA_B1_GCC_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430454/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430698/ AN521_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430739/ MUSCA_B1_GCC_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430829/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430880/ MUSCA_B1_GCC_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430430/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430250/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430265/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430267/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430269/ MUSCA_B1_ARMCLANG_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430276/ MUSCA_B1_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430282/ MUSCA_B1_GCC_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430285/ MUSCA_B1_ARMCLANG_3_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430312/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430316/ MUSCA_B1_GCC_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430320/ MUSCA_B1_ARMCLANG_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430339/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430385/ MUSCA_B1_ARMCLANG_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430397/ MUSCA_B1_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430399/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430403/ MUSCA_B1_ARMCLANG_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430404/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430427/ AN521_GCC_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430434/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430436/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430439/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430460/ AN521_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430521/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430531/ MUSCA_B1_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430532/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430542/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430545/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430549/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430560/ MUSCA_B1_ARMCLANG_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430574/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430581/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430589/ MUSCA_B1_GCC_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430590/ MUSCA_B1_GCC_3_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430595/ MUSCA_B1_ARMCLANG_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430674/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430689/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430716/ corstone320_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/430718/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430719/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430733/ MUSCA_B1_GCC_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430736/ corstone315_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/430755/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430761/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430774/ MUSCA_B1_GCC_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430784/ MUSCA_B1_GCC_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430789/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430791/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430798/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430821/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430859/ MUSCA_B1_ARMCLANG_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430861/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430869/ MUSCA_B1_GCC_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430875/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430375/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430447/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430466/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430467/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430475/ corstone315_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/430484/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430486/ corstone320_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/430489/ AN521_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430493/ AN521_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430503/ MUSCA_B1_ARMCLANG_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430609/ AN521_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430612/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/430613/ MUSCA_B1_GCC_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430631/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430638/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/430643/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430646/ MUSCA_B1_ARMCLANG_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430652/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/430654/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/430666/ AN521_GCC_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/430737/

For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/291/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/293/

Failed Jobs: MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432407/ MUSCA_B1_GCC_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432451/ MUSCA_B1_GCC_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432333/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432345/ MUSCA_B1_GCC_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432366/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432391/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432396/ MUSCA_B1_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432455/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432457/ MUSCA_B1_ARMCLANG_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432463/ MUSCA_B1_GCC_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432469/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432537/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432677/ MUSCA_B1_ARMCLANG_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432716/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432718/ corstone320_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/432732/ MUSCA_B1_ARMCLANG_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432744/ AN521_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432804/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432842/ MUSCA_B1_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432334/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432338/ MUSCA_B1_GCC_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432340/ corstone320_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/432347/ AN521_GCC_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432348/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432353/ MUSCA_B1_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432355/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432404/ AN521_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432422/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432425/ MUSCA_B1_ARMCLANG_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432428/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432429/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432438/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432439/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432447/ MUSCA_B1_ARMCLANG_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432449/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432459/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432475/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432489/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432490/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432491/ AN521_GCC_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432497/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432499/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432501/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432507/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432509/ corstone320_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/432516/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432520/ MUSCA_B1_GCC_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432538/ MUSCA_B1_ARMCLANG_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432542/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432553/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432565/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432567/ MUSCA_B1_GCC_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432572/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432578/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432581/ MUSCA_B1_ARMCLANG_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432582/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432591/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432599/ AN521_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432605/ MUSCA_B1_GCC_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432606/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432608/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432609/ MUSCA_B1_GCC_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432610/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432617/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432620/ AN521_GCC_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432622/ MUSCA_B1_GCC_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432631/ MUSCA_B1_ARMCLANG_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432633/ MUSCA_B1_GCC_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432644/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432651/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432659/ MUSCA_B1_GCC_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432678/ MUSCA_B1_GCC_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432680/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432690/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432691/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432704/ MUSCA_B1_GCC_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432705/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432727/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432742/ MUSCA_B1_GCC_3_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432761/ MUSCA_B1_GCC_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432764/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432770/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432771/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432772/ MUSCA_B1_GCC_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432773/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432778/ MUSCA_B1_ARMCLANG_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432789/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432794/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432800/ AN521_ARMCLANG_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432815/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432821/ MUSCA_B1_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432830/ AN521_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432833/ AN521_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432844/ MUSCA_B1_ARMCLANG_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432847/ MUSCA_B1_GCC_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432848/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432852/ AN521_ARMCLANG_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432862/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432865/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432874/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432879/ corstone315_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/432888/ AN521_GCC_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432889/ corstone315_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/432893/ MUSCA_B1_GCC_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432905/ MUSCA_B1_ARMCLANG_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432910/ AN521_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432914/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/432915/ MUSCA_B1_GCC_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432929/ MUSCA_B1_ARMCLANG_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432932/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432935/ MUSCA_B1_GCC_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432941/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432945/ MUSCA_B1_ARMCLANG_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432946/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432964/ corstone315_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/432971/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432973/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/432979/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/432980/ MUSCA_B1_ARMCLANG_3_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432982/ AN521_GCC_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432989/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432991/ MUSCA_B1_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432992/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/432997/ MUSCA_B1_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/433001/ MUSCA_B1_GCC_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/433003/ AN521_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/433004/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/433008/ AN521_GCC_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/433009/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/433014/ corstone315_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/433019/ MUSCA_B1_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/433027/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/433029/ corstone320_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/433041/ MUSCA_B1_GCC_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/433043/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/433044/ MUSCA_B1_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/433045/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/433056/ AN521_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/432880/

For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/293/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/295/

Failed Jobs: corstone320_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/435499/ corstone320_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/435150/ AN521_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/435234/ AN521_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/435660/ MUSCA_B1_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/435697/ AN521_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/435792/ corstone315_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/435123/ corstone315_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/435205/ MUSCA_B1_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/435299/ corstone320_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/435632/ MUSCA_B1_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/435636/ corstone320_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/435585/ AN521_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/435443/ corstone315_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/435621/ corstone315_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/435451/ MUSCA_B1_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/435369/

For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/295/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/297/

Failed Jobs: AN521_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/437751/ MUSCA_B1_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/437937/ AN521_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/438257/ corstone320_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/438258/ corstone320_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/438281/ MUSCA_B1_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/438446/ MUSCA_B1_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/438453/ corstone315_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/437862/ corstone315_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/437915/ AN521_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/437852/ corstone320_GCC_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/438362/ MUSCA_B1_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/438221/ corstone320_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/438173/ corstone315_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/437907/ corstone315_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/437935/ AN521_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/437927/

For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/297/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/299/

Failed Jobs: MUSCA_B1_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/440676/ AN521_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/440770/ MUSCA_B1_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/440823/ MUSCA_B1_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/440849/ AN521_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/441221/ MUSCA_B1_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/441051/ AN521_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/440918/ AN521_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/440972/

For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/299/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/301/

Failed Jobs: MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891913 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891914 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891915 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891916 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891917 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891918 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891919 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891920 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891921 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891922 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891923 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891924 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891925 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891926 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891927 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891928 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891929 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891930 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2891931 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891932 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891933 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891934 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2891935 MUSCA_B1_ATFE_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891936 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891937 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891938 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891939 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891940 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2891941 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891942 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891943 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891944 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891945 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891946 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891947 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891948 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891949 MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891950 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891951 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891952 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891953 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2891954 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891955 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891956 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891957 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891958 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891959 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891960 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891961 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891962 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891963 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891964 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891965 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891966 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891967 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891968 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891969 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891970 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891971 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891972 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891973 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891974 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891975 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2891976 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891977 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891978 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891979 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891980 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891981 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891982 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891983 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891984 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891985 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891986 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2891987 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2891988

For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/301/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/303/

Failed Jobs: RSE_TC4_GCC_1_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3AKcHqlvxsCg62lZ... RSE_TC4_GCC_1_Release_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3AKcHzO9RW1xSaR6... MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2892898 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892899 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2892900 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892901 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2892902 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892903 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892904 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2892905 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2892906 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2892907 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892908 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892909 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2892910 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892911 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892912 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892913 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2892914 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892915 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892916 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892917 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892918 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892919 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2892920 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892921 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2892922 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892923 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2892924 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892925 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2892926 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2892927 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892928 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2892929 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2892930 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892931 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2892932 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2892933 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2892934 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2892935 MUSCA_B1_ATFE_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2892936 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2892937 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2892938 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2892939 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2892940 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892941 MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2892942 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2892943 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2892944 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892945 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892946 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2892947 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2892948 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892949 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2892950 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892951 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2892952 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2892953 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892954 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2892955 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892956 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892957 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2892958 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2892959 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892960 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892961 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2892962 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2892963 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2892964 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2892965 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2892966 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2892967 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2892968 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2892969 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2892970 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2892971 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2892972 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2892973

For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/303/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/300/

Failed Jobs: RSE_TC4_GCC_3_RegS_RegNS_Release_BL2_CM_DM_BL2_ECDSA_SIGNING https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3AC8S9xyyJSUb1nW... MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891108 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891109 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891110 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891111 RSE_TC4_GCC_2_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3AC8SKv0N4dtrOgJ... MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891112 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891113 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891114 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891115 MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891116 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891117 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891118 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891119 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2891120 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891121 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891122 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891123 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891124 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891125 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891126 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891127 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891128 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891129 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891130 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891131 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891132 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2891133 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891134 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891135 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891136 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891137 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891138 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891139 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891140 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891141 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2891142 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891143 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891144 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891145 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891146 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891147 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891148 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891149 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891150 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891151 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891152 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891153 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891154 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891155 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891156 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891157 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891158 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891159 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2891160 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891161 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891162 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2891163 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891164 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2891165 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891166 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891167 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891168 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891169 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2891170 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2891171 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891172 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891173 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891174 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891175 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2891176 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891177 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891178 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2891179 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891180 MUSCA_B1_ATFE_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2891181 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2891182 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2891183

For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/300/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/298/

Failed Jobs: RSE_TC4_GCC_1_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3A6UGp2xHrKLqGND... RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3A6UGvRQnLXeKjSR... MUSCA_B1_GCC_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889770 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889771 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889772 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2889773 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889774 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889775 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2889776 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2889777 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889778 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889779 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2889780 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2889781 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889782 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889783 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2889784 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889785 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889786 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2889787 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2889788 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2889789 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889790 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2889791 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889792 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889793 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2889794 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2889795 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889796 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889797 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889798 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2889799 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889800 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2889801 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889802 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889803 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889804 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889805 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889806 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889807 MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889808 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889809 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889810 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2889811 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889812 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889813 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889814 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2889815 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2889816 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889817 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2889818 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889819 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889820 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2889821 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889822 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2889823 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889824 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889825 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889826 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889827 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2889828 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889829 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2889830 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889831 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889832 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2889833 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2889834 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2889835 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889836 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889837 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889838 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889839 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2889840 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2889841 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2889842 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2889843 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889844 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2889845

For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/298/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/295/

Failed Jobs: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2887858 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887859 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887860 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2887861 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2887862 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887863 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2887864 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2887865 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2887866 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2887867 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887868 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2887869 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887870 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2887871 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2887872 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887873 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2887874 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887875 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887876 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887877 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2887878 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887879 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887880 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887881 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2887882 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2887883 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2887884 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887885 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2887886 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887887 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2887888 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887889 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887890 MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887891 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2887892 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2887893 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887894 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887895 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887896 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887897 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2887898 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2887899 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887900 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2887901 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2887902 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887903 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2887904 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2887905 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2887906 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887907 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887908 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887909 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887910 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2887911 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887912 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2887913 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887914 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2887915 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2887916 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887917 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887918 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2887919 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887920 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887921 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887922 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887923 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887924 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2887925 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2887926 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887927 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887928 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2887929 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2887930 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2887931 MUSCA_B1_ATFE_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2887932 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2887933 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2887934 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2887935 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://tf.validation.linaro.org/scheduler/job/2887936

For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/295/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/293/

Failed Jobs: RSE_TC4_GCC_1_RegS_RegNS_Release_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/39rw2jkxWCpqEphU... MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2886265 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2886266 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2886267 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2886268 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2886269 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2886270 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2886271 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2886272 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2886273 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2886274 MUSCA_B1_ATFE_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2886275 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2886276 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2886277 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2886278 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2886279 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2886280 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2886281 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2886282 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2886283 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2886284 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2886285 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2886286

For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/293/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/291/

Failed Jobs: MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2885119 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2885120 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2885121 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2885122 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2885123 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2885124 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2885125 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2885126 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2885127 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2885128 MUSCA_B1_ATFE_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2885129 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2885130 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2885131 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2885132 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2885133 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2885134 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2885135 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2885136 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2885137 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2885138 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2885139 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2885140

For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/291/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/289/

Failed Jobs: MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2884104 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2884105 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2884106 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2884107 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2884108 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2884109 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2884110 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2884111 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2884112 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2884113 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2884114 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2884115 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2884116 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2884117 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2884118 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2884119 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2884123 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2884120 MUSCA_B1_ATFE_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2884121 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2884122 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2884125 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2884124

For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/289/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/287/

Failed Jobs: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2883098 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2883099 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2883100 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2883101 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2883102 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2883103 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2883104 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2883105 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2883106 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2883107 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2883108 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2883109 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2883110 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2883111 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2883112 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2883113 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2883114 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2883115 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2883116 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2883117 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2883118 MUSCA_B1_ATFE_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2883119

For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/287/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.