Hi ,
There is a contradiction present in TF-A documentation whether secure interrupts can be handled in EL3 for arm gic v2 case .
1.
Referring https://trustedfirmware-a.readthedocs.io/en/latest/design/interrupt-framewo…
It says secure interrupts can't be handled in EL3 .
Refer statement : "In Arm GICv2, all secure interrupts are assumed to be handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they cannot be handled in EL3."
2.
Referring https://trustedfirmware-a.readthedocs.io/en/latest/components/platform-inte…
It says secure interrupts can be handled in EL3 , When GICV2_G0_FOR_EL3 is 1 .
Refer below statements :
For interrupt type INTR_TYPE_EL3:
When GICV2_G0_FOR_EL3 is 0, it returns false, indicating no support for EL3 interrupts.
When GICV2_G0_FOR_EL3 is 1, it returns true, indicating support for EL3 interrupts.
can this be clarified ?
Regards
Amit
This event has been canceled with a note:
"Hi, Cancelling as no topic proposed this week. Thanks & Regards, Olivier. "
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Hi All,
The next release of the Firmware-A bundle of projects tagged v2.10 has an expected code freeze date of Nov, 7th 2023.
Refer to the Release Cadence section from TF-A documentation (https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/docs/about…).
Closing out the release takes around 6-10 working days after the code freeze.
Preparations tasks for v2.10 release should start in coming month.
We want to ensure that planned feature patches for the release are submitted in good time for the review process to conclude. As a kind recommendation and a matter of sharing CI resources, please launch CI jobs with care e.g.:
-For simple platform, docs changes, or one liners, use Allow-CI+1 label (no need for a full Allow-CI+2 run).
-For large patch stacks use Allow-CI+2 at top of the patch stack (and if required few individual Allow+CI+1 in the middle of the patch stack).
-Carefully analyze results and fix the change if required, before launching new jobs on the same change.
-If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not added as a gerrit comment on the patch right away please be patient as under heavy load CI jobs can be queued and in extreme conditions it can be over an hour before the Build start notice is issued. Issuing another Allow-CI+1 or Allow-CI+2 label will just result in an additional job being queued.
Thanks & Regards,
Olivier.
Hi,
Referring https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/getti…
it says : ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault injection from lower Els.
Referring https://github.com/ARM-software/arm-trusted-firmware/blob/master/lib/el3_ru…
FAULT_INJECTION_SUPPORT enables FIEN bit.
#if FAULT_INJECTION_SUPPORT
/* Enable fault injection from lower ELs */
scr_el3 |= SCR_FIEN_BIT;
#endif
Question :
1.
Do we have any relevant documentation from arm which specifies FIEN bit can be enabled from armv8.4 ?
2.
In cortex a-53 technical reference manual, SCR_EL3 does not have FIEN bit , bit 21 is marked reserved .
In cortex a-78 technical reference manual , manual does not have details for SCR_EL3 .
I want to know whether on Armv8.2-a based cores like cortex a-78 , is the FIEN bit field marked reserved in SCR_EL3 register or is available functionality wise as in armv8.4 ?
Please help with above query.
Regards
Amit
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
14 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)
** CID 425813: Memory - corruptions (OVERRUN)
/drivers/arm/css/dsu/dsu.c: 133 in cluster_on_dsu_pmu_context_restore()
________________________________________________________________________________________________________
*** CID 425813: Memory - corruptions (OVERRUN)
/drivers/arm/css/dsu/dsu.c: 133 in cluster_on_dsu_pmu_context_restore()
127 void cluster_on_dsu_pmu_context_restore(void)
128 {
129 unsigned int cluster_pos;
130
131 cluster_pos = (unsigned int) plat_cluster_id_by_mpidr(read_mpidr_el1());
132
>>> CID 425813: Memory - corruptions (OVERRUN)
>>> "&cluster_pmu_context[cluster_pos]" evaluates to an address that is at byte offset 138720 of an array of 544 bytes.
133 restore_dsu_pmu_state(&cluster_pmu_context[cluster_pos]);
** CID 425812: Memory - corruptions (OVERRUN)
/drivers/arm/css/dsu/dsu.c: 81 in cluster_off_dsu_pmu_context_save()
________________________________________________________________________________________________________
*** CID 425812: Memory - corruptions (OVERRUN)
/drivers/arm/css/dsu/dsu.c: 81 in cluster_off_dsu_pmu_context_save()
75 void cluster_off_dsu_pmu_context_save(void)
76 {
77 unsigned int cluster_pos;
78
79 cluster_pos = (unsigned int) plat_cluster_id_by_mpidr(read_mpidr_el1());
80
>>> CID 425812: Memory - corruptions (OVERRUN)
>>> "&cluster_pmu_context[cluster_pos]" evaluates to an address that is at byte offset 138720 of an array of 544 bytes.
81 save_dsu_pmu_state(&cluster_pmu_context[cluster_pos]);
82 }
83
84 /*****************************************************************************
85 * This function, restore_dsu_pmu_state, restores the state of the
86 * Performance Monitoring Unit (PMU) from a previously saved state.
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
8 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 425810: High impact quality (WRITE_CONST_FIELD)
/plat/nxp/s32/s32g274ardb2/plat_console.c: 17 in console_s32g2_register()
________________________________________________________________________________________________________
*** CID 425810: High impact quality (WRITE_CONST_FIELD)
/plat/nxp/s32/s32g274ardb2/plat_console.c: 17 in console_s32g2_register()
11
12 void console_s32g2_register(void)
13 {
14 static console_t s32g2_console;
15 int ret;
16
>>> CID 425810: High impact quality (WRITE_CONST_FIELD)
>>> A write to an aggregate overwrites a const-qualified field within the aggregate.
17 (void)memset(&s32g2_console, 0, sizeof(s32g2_console));
18
19 ret = console_linflex_register(UART_BASE, UART_CLOCK_HZ,
20 UART_BAUDRATE, &s32g2_console);
21 if (ret == 0) {
22 panic();
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…