This event has been canceled with a note:
"No TF-A Tech forum on Dec 25th."
TF-A Tech Forum
Thursday Dec 25, 2025 ⋅ 5pm – 6pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
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Hi, On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will
present a design update on TF-RMM Live Firmware Activation: This
presentation describes the revised TF-RMM Low-VA MMU and
global-runtime-data design required to support Live Firmware Activation
(LFA). Compared to the earlier approach (outlined in the TFA Tech Forum
session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings
and per-platform handcrafted Low-VA contexts, the new design is driven by
several changes in RMM specification: RMM must now support runtime
mapping/unmapping of PAs for RMM objects like struct granule , reuse those
dynamic mappings across LFA transitions. These PAs can come either from NS
world at runtime or EL3 reservation from RMM carveout. In order to migrate
Stage 1 dynamic mappings across LFA instances, RMM needs to reduce
dependence on platform-specific MMU setup, and provide a structured
framework for allocating, versioning and migrating global runtime data. The
Stage 1 Low-VA is therefore split into static and dynamic regions managed
by the common xlat layer. The detailed design is captured in the TF-RMM
wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial
design presented in the TFA Tech Forum session on 12-Jun-2025 [1] : [1]
Previous LFA discussion:
https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations [2]
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act…
Regards, Olivier.
TF-A Tech Forum
Thursday Dec 11, 2025 ⋅ 5pm – 6pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A
Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu,
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Hi,
On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will present a design update on TF-RMM Live Firmware Activation:
This presentation describes the revised TF-RMM Low-VA MMU and global-runtime-data design required to support Live Firmware Activation (LFA). Compared to the earlier approach (outlined in the TFA Tech Forum session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings and per-platform handcrafted Low-VA contexts, the new design is driven by several changes in RMM specification: RMM must now support runtime mapping/unmapping of PAs for RMM objects like struct granule , reuse those dynamic mappings across LFA transitions. These PAs can come either from NS world at runtime or EL3 reservation from RMM carveout.
In order to migrate Stage 1 dynamic mappings across LFA instances, RMM needs to reduce dependence on platform-specific MMU setup, and provide a structured framework for allocating, versioning and migrating global runtime data. The Stage 1 Low-VA is therefore split into static and dynamic regions managed by the common xlat layer. The detailed design is captured in the TF-RMM wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial design presented in the TFA Tech Forum session on 12-Jun-2025 [1] :
[1] Previous LFA discussion: https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations
[2] https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act…
Regards,
Olivier.
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TF-A Tech Forum
Thursday 2025-11-13 ⋅ 4pm – 5pm
United Kingdom Time
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A
Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu,
78 occurrence(s)Please download and import the following iCalendar (.ics)
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TF-A Tech Forum
Every 2 weeks from 4pm to 5pm on Thursday
United Kingdom Time
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Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A
Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu,
78 occurrence(s)Please download and import the following iCalendar (.ics)
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Hi
I'm looking for a suggestion for a reliable place to store a small boot
index for PSA Firmware Update. SNVS LPGPRs looked promising, but NXP’s
guidance is thin and we don’t keep the battery-backed LP domain alive, so
those values won’t survive many power cycles. Are there better options on
LS1028A? Would using the user RAM byte in our external I2C RTC make sense?
Or perhaps should I store it on eMMC? (we don't use raw NOR/NAND flash).
That RTC I mentioned is already accessed in both U-Boot and Linux, so I’m
wary of conflicts but can try it if you think it’s viable.
Any suggestions would be much appreciated.
Best regards
Patryk
Hi,
I have a sort of generic Arm architecture question that's not directly
related to TF-A (other than that TF-A controls some of the registers
involved in this decision), but I'm hoping that one of the experts
here can still help me out or at least refer me to someone who can.
I'm trying to figure out how exception routing for SError aborts works
in EL2. Specifically, I have a bootloader (BL33) running in NS-EL2 and
I want the "simple" setup that it manages all its own exceptions, the
same way that an OS kernel normally manages all exceptions at EL1. I
assumed that I could achieve that simply by installing exception
handlers, unmasking all exceptions in PSTATE, and leaving all the
special trap feature bits in the MSRs at 0 (disabled).
This seems to work for synchronous exceptions and external aborts, but
not for SErrors. Looking at the architecture reference manual
(revision L.b), table D1-14 in section D1.3.6.3 (page D1-6114), I can
see that my case is represented by the first line (all special trap
bits 0), which shows that SErrors caused by EL0 and EL1 would be
routed to EL1 as expected (though even when PSTATE.A is 1 which seems
odd?), but SErrors caused by EL2 will get ignored and remain pending
(with no regard to PSTATE.A). Instead, the "default" behavior I expect
(aborts get routed to the EL that caused them if PSTATE.A is 0) seems
to require me to enable SCTLR_EL2.NMEA. But if you're looking at the
description of SCTLR_EL2.NMEA, it says that it controls whether
PSTATE.A masks SError exceptions at EL2 (and that if it is 0, SError
exceptions are not taken at EL2 if PSTATE.A == 1). Doesn't that imply
that SError exceptions *are* taken at EL2 if PSTATE.A == 0? What does
a control that seems to be about trapping masked aborts from a lower
EL have to do with unmasked aborts from my current EL?
Basically, I think what I'm asking is: is that table really correct as
printed (some behavior we've observed seems to indicate it is), and if
so, why? Why do SError exceptions seem to behave differently by
default in EL1 and EL2 (in regards to unmasked exceptions taken from
the same exception level)? Why does the PSTATE.A bit only seem to
apply to EL0 and EL1, not EL2 and EL3, even for exceptions taken from
the same level, when this peculiarity seems to not be mentioned
anywhere else in the manual? Why do SError exceptions get treated so
differently from external aborts in EL2/EL3, when in EL1 they seem to
mostly count as the same? Is the current description of the NMEA bit
in the SCTLR_EL2 register documentation really accurate, if it also
seems to make fundamental changes to cases not really mentioned in
that description? Is there any way for EL2 to only handle its own
SError exceptions without interfering with EL1's exception handling
when FEAT_DoubleFault2 is not implemented (other than flipping
HCR_EL2.AMO on every EL2 entry/exit)? And am I the only one who finds
this all incredibly inconsistent and confusing?
I feel like I'm missing some critical insight in how you were meant to
think about this to make it make sense, would appreciate any help in
that regard!
Thanks,
Julius