mmc_enumerate() is the only caller of mmc_send_op_cond().
mmc_enumerate() calls mmc_reset_to_idle() just before calling
mmc_send_op_cond(). No need to do that again in mmc_send_op_cond().
Signed-off-by: Baruch Siach <baruch(a)tkos.co.il>
Change-Id: Ib8c8ed1a559e3fecb315245f91bb3dc1f547d820
---
Sending the patch to the list once again. review.trustedfirmware.org
does not work for me.
https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…
---
drivers/mmc/mmc.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 2b727d4e7696..57f47482013a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -452,11 +452,6 @@ static int mmc_send_op_cond(void)
int ret, n;
unsigned int resp_data[4];
- ret = mmc_reset_to_idle();
- if (ret != 0) {
- return ret;
- }
-
for (n = 0; n < SEND_OP_COND_MAX_RETRIES; n++) {
ret = mmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7,
--
2.39.2
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Hi,
In ARM TBBR, there is a requirement
“R0100_TBBR_AFM_FLASHING” (The AP firmware must switch to the Non-Trusted world for executing the SoC firmware loader),
But there is no requirement for secure boot as long as I finish chain if ROT verification.
So, can I implement FWU in BL2 which is verified and load from BL1 (ROM)?
For example,
BL1(ROM) -> Load and verify BL2U with new image from SD to secure RAM -> execute BL2U in Secure RAM then write new image to NAND flash
Best regards,
Jun
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Agenda UpdateTitle:PSCI OS-initiated mode in TF-APresented by:Maulik Shah,
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AllJoanna===============================We run an open technical forum call
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Hi,
I have one question about SIP Service Calls range and it's range checking.
Based on DEN0028E SIP Service Calls ranges are
0x82000000-0x8200FFFF SMC32: SiP Service Calls
0xC2000000-0xC200FFFF SMC64: SiP Service Calls
That's the ranges which we are using for implementing SOC specific SMC handlers
and I found that in past it was also added code which is out of this range.
Specifically in Xilinx ZynqMP you can see code like this
if (is_em_fid(smc_fid)) {
return em_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
flags);
}
where EM range is 0x820e0001- 0x820e0003 is out of our range which is assigned
to us. But there is no failure at all that we are out of ranged in spec.
Shouldn't this be enforced by core itself?
That's why I just wanted to know your opinion about it. We will definitely
implement better masking to find out that 0x00fe0000 are all zeros.
But that bit 16 is based on DEN0028E related to smcccv1.3 which I think we are
not supporting now that's why should be 0 too.
But definitely some information about this bit should be useful.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
External email: Use caution opening links or attachments
We are pleased to announce the release of the Trusted Firmware-A LTS version 2.8.0 [1]. To help with the verification and stability of the release, we also created side branches for Trusted Firmware-A Tests [2] and TF-A OpenCI Scripts/Jobs [3].
These went live on 13th February 2023. The trusted-firmware-a repository is now open again.
On behalf of the TF-A LTS project maintainers, I would like to thank the Trustedfirmware.org TF-A Project community for the support and guidance.
Notable features of the TF-A LTS Version 2.8.0 Release are as follows:
TF-A Project Repository
* Resolved issues
* Workarounds for the following CPU errata
* Cortex-A510 erratum 2684597
* Cortex-A710 erratum 2282622
* Cortex-A710 erratum 2768515
* Cortex-A78 erratum 2772019
* Cortex-A78 erratum 2779479
* Cortex-A78C erratum 2772121
* Cortex-X2 erratum 2282622
* Cortex-X2 erratum 2768515
* Cortex-X3 erratum 2615812
* Neoverse N2 erratum 2743089
* Neoverse V1 erratum 2743093
* Neoverse V1 errata 2779461
* Mitigations for the security advisory #10
* Critical bug fixes for the following platforms
* Arm/CSS
* Intel
* Layerscape
* LS1046a
* LX2
* NXP
* ST
Patch Statistics
* 35 Patches merged since v2.8 Nov 2022 release
Please refer to the TF-A LTS [1] changelog for the complete summary of changes.
[1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/docs/chang…
[2] tf-a-tests.git - Trusted Firmware-A Tests<https://git.trustedfirmware.org/TF-A%2Ftf-a-tests.git/log/?h=refs%2Fheads%2…>
[3] tf-a-ci-scripts.git - Trusted Firmware A (TF-A) CI scripts<https://git.trustedfirmware.org/ci%2Ftf-a-ci-scripts.git/log/?h=refs%2Fhead…>
[4] tf-a-job-configs.git - Trusted Firmware A (TF-A) Jenkins job configs<https://git.trustedfirmware.org/ci%2Ftf-a-job-configs.git/log/?h=refs%2Fhea…>
Hi all,
As you may know, the TF-A project historically used to make heavy use of
weak functions. The code base has numerous examples of them. However,
based on previous discussions, I think we have general consensus in the
TF-A community that the disadvantages of weak functions outweigh their
benefits and for this reason we should discourage introducing new ones.
In practice, I think this policy is already enforced most of the time in
code reviews but I've now posted a patch that makes it explicit in the
project's coding guidelines and provide the rationale behind it.
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19398
Note that TF-A maintainers would still be responsible for enforcing this
policy, as the CI system won't flag that for them, mainly because I
think there might be legitimate cases for weak functions in rare
instances so we'd get some false positives from such checks.
We (at Arm) have got plans to gradually convert existing weak functions
to strongly-defined implementations across the code base but this will
take time.
Like I said, I don't expect this change to be too controversial but
please raise any concerns you may have in this email thread or on Gerrit.
Best regards,
Sandrine