Hello all,
We are sending this note to notify you of one of the breaking changes related to the enablement of FEAT_SVE in TF-A. This mainly impacts platforms which are configurable (FVP, QEMU, Total Compute).
FEAT_SVE has now been moved under the Feature detection mechanism wherein a CPU feature macro can have 3 possible states
* 0: FEAT_STATE_DISABLED
* 1: FEAT_STATE_ALWAYS ( Always enabled, no runtime check)
* 2: FEAT_STATE_CHECK (Dynamically check based on ID registers, done each time when feature registers are being accessed)
For platforms which have a single configuration, it's better to choose either disabled or enabled (as it is a bit faster as there is no dynamic check).
For platforms which can have different HW configurations, it makes sense to put them under FEAT_STATE_CHECK(=2), so that they will boot with any configuration of HW.
Keeping this in mind, all configurable platforms (FVP, QEMU, TC) have been modified to adopt dynamic detection(FEAT_STATE_CHECK) for FEAT_SVE. [1]
SVE Patch Reference:
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20306
Best regards,
Jayanth
Hello Kever,
on a rk3399, booting current U-Boot SPL with mainline TF-A leads to
missing DMA (and no sound) on Linux.
However, when using rockchip its so called mini-loader
(rk3399_miniloader_v1.26.bin) and their BL31 (rk3399_bl31_v1.35.elf) to
boot, DMA works perfectly fine.
Tested on a custom rk3399 board and on ROCK Pi4.
Attached to this mail are two boot logs with some debug prints:
- good_amba_log.txt (DMA works)
- no_amba_log.txt (no DMA device)
The main difference I can spot between the two logs is that on Linux
(drivers/amba/bus.c) AMBA_CID (0xb105f00d) cannot be found. Instead,
only some CORESIGHT_CIDs (presumably for debugging) and four 0x00000000
CIDs are detected.
As a result, the "PL330 DMAC-241330" driver does not load. My theory is
that DMA needs to be allowed somewhere in the undocumented syscon-
registers, similar to what U-Boot is already doing for eMMC in
arch_cpu_init() (arch/arm/mach-rockchip/rk3399/rk3399.c).
Any ideas?
Or maybe I'm just missing some configuration?
Since multiple software projects are involved (TF-A, OP-TEE, U-Boot,
Linux), I Cc'ed a bit.
Thanks
-- Christoph
This event has been canceled with a note:
"No topics this week so cancelling."
TF-A Tech Forum
Thursday Apr 6, 2023 ⋅ 4pm – 5pm
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Hi Folks,
I’ve just updated the Techforum session information (Slides and Recording) from the RAS Handing session last week on https://www.trustedfirmware.org/meetings/tf-a-technical-forum/ which will be deployed soon once the patch is approved.
The next TF-A Tech forum is due on Thursday 6th April at 4pm BST.
At this time I don’t have any topics for that session. If anybody in the community has anything they would like to present please do reach out to me.
Thanks
Joanna
Hi,
according to the current erratum document for the ARM Cortex-A78AE [0], the workaround for erratum 1941500 says:
"This erratum can be avoided by setting CPUECTLR_EL1[8] to 1."
However, the current code on branch "master" (git hash 5906d97a832b6f6 ) at
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/cpus/a…
executes a "bic" instruction with an immediate, which is a synthetic instruction to clear the bit, instead of setting it. Moreover, the comment above says "Set bit 8 in ECTLR_EL1", which is inconsistent to the code.
The equivalent workaround for the Cortex-A78 non-AE (erratum 1941498) uses the correct "orr" (bitwise-or) instruction to set the bit:
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/cpus/a…
Please confirm if this is an error.
Thank you.
Best Regards,
Matthias
[0] "Arm Cortex-A78AE (MP105) Software Developer Errata Notice", Document version: v14.0, Document ID: SDEN-1707912,
https://developer.arm.com/documentation/SDEN1707912/latest
Hi all,
I try to enable the smmu of Juno R2 development board but face two
great challenges. I am working on them and I still need some hints.
Here are my problems:
1. By reading the SMMUv1 manuals I find that several registers are
related to secure state (e.g., SMMU_sCR0). But in my TF-A and the
latest version I can only find the SMMUv3 configurations, not
SMMUv1/2. Thus, how to config these registers? Any reference?
2. For the non-secure GPU SMMU regs, I try to map and read them based
on the Juno R2 manual. I know the GPU SMMU is a MMU-400, and its mmio
is in 0x2b40_0000 - 0x2b40_ffff. Then in EL1 I first do
ioremap(0x2b400000,0x10000) and then ioread32(). However I get the
SError as "Bad mode in Error handler detected on CPU1, code
0xbf000002". I also try to do it in EL2 (with a hvc call and reading
in the handler), but cannot get any valid number and still get SError
when exiting EL2. But when I access the other smmus (e.g., a PCIe
SMMU, in 0x2b50_0000), it works fine. Thus, is there something to
prevent the Non-secure World from accessing the GPU SMMU MMIO?
My source codes are downloaded from the arm-reference-platforms, in
which Linux is v4.14.59 and TF-A is v2.1.
Can someone help me?
Sincerely,
WANG Chenxu
This event has been updated with a note:
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Changed: description
TF-A Tech Forum
Thursday Mar 23, 2023 ⋅ 4pm – 5pm
United Kingdom Time
Discussion Topic: RAS Refactoring Presented by: Manish Pandey and Soby
MathewTopics to be discussed 1. Introduction to philosophies of handling
RAS errors(FFH/KFH) 2. Discussing exceptions caused by synchronization
barriers at execption boundries 3. Refactoring and enhancements in
TF-A(along with various build macros) 4. Tests introduced 5. Future
work----------------We run an open technical forum call for anyone to
participate and it is not restricted to Trusted Firmware project members.
It will operate under the guidance of the TF TSC. Feel free to forward this
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I have already created patch in tf-a for review, added plat Nuvoton
npcm845x, gerrit topic No. 20088.
How should I upload a scripts patch to support new added platform?
In documentation I didn't found how exactly should I send a scripts patch.
Thank you in advance.
Margarita Glushkin