Hi All,
The next release of the Firmware-A bundle of projects tagged v2.13 has an expected code freeze date of May, 2nd 2025.
In order to accommodate the Linaro connect event occurring during the week of May 12th we may extend the release completion date up until the week of May 26th.
v2.13 release preparation tasks start from now.
We want to ensure that planned feature patches for the release are submitted in good time for the review process to conclude.
As a kind recommendation and a matter of sharing CI resources, please launch CI jobs with care e.g.:
-For simple platform, docs changes, or one liners, use Allow-CI+1 label (no need for a full Allow-CI+2 run).
-For large patch stacks use Allow-CI+2 at top of the patch stack (and if required few individual Allow+CI+1 labels in the middle of the patch stack).
-Carefully analyze results and fix the change if required, before launching new jobs on the same change.
-If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not added as a gerrit comment on the patch right away please be patient as under heavy load CI jobs can be queued and in extreme conditions it can be over an hour before the Build start notice is issued. Issuing another Allow-CI+1 or Allow-CI+2 label will just result in an additional job being queued.
Regards,
Olivier.
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Hi,
For some reason the invite disappeared from the shared trustedfirmware.org calendar but this message is to state there is no TF-A tech forum planned tomorrow May 1st due to lack of topics.
Thanks & Regards,
Olivier.
Hi All,
We currently have TF-A/OP-TEE support for a platform (ADSP-SC598,
arm cortex A55) in our forked repositories and would like to upstream
our past efforts to align better with newer developments within the projects.
As per the contributor's guide for TF-A, it mentions that it might be a good
idea to start a discussion regarding the same prior to submission of a patch
series.
Currently, the plan is for the initial patch series to support BL31 followed by
another patch series adding support for PSCI. The overarching idea being that
BOOTROM passes control to u-boot SPL, which configures required peripherals
and loads us into TF-A, then proceeding to load OP-TEE, followed by full
uboot/linux.
Please let me know your thoughts/concerns and if I should be proceeding
with the patch series submission.
Regards,
Utsav Agarwal
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)
** CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW)
/services/std_svc/sdei/sdei_event.c: 79 in get_event_entry_target_pe()
________________________________________________________________________________________________________
*** CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW)
/services/std_svc/sdei/sdei_event.c: 79 in get_event_entry_target_pe()
73 */
74 idx = mapsub;
75
76 /* Base of private mappings for this CPU */
77 base_idx = (unsigned int) plat_core_pos_by_mpidr(target_pe);
78 base_idx *= nm;
>>> CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW)
>>> "base_idx", which might have underflowed, is passed to "sdei_private_event_table[base_idx]".
79 cpu_priv_base = &sdei_private_event_table[base_idx];
80 /*
81 * Return the address of the entry at the same index in the
82 * per-CPU event entry.
83 */
84 return &cpu_priv_base[idx];
** CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS)
/services/std_svc/sdei/sdei_intr_mgmt.c: 64 in sdei_is_target_pe_masked()
________________________________________________________________________________________________________
*** CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS)
/services/std_svc/sdei/sdei_intr_mgmt.c: 64 in sdei_is_target_pe_masked()
58
59 /* SDEI states for all cores in the system */
60 static sdei_cpu_state_t cpu_state[PLATFORM_CORE_COUNT];
61
62 bool sdei_is_target_pe_masked(uint64_t target_pe)
63 {
>>> CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS)
>>> Using variable "plat_core_pos_by_mpidr(target_pe)" as an index to array "cpu_state".
64 const sdei_cpu_state_t *state = sdei_get_target_pe_state(target_pe);
65
66 return state->pe_masked;
67 }
68
69 int64_t sdei_pe_mask(void)
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…
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