Hi Bohdan,
Yes, when called from NSPE the __disable_irq() has the effect of boosting execution priority to 0 if AIRCR.PRIS is clear, or 0x80 (i.e. just lower priority than SPE IRQs) if AIRCR.PRIS is set.
We set AIRCR.PRIS in TF-M (in tfm_arch_set_secure_exception_priorities()) precisely because we don't want the NSPE to be able to mask SPE interrupts. I would advise sticking with this strategy and ensuring that SPE IRQ handlers do not touch any NSPE state to preserve the semantics of the critical sections in NSPE, without masking IRQs. But if you really do want to mask SPE interrupts from NSPE, then you need to clear the PRIS flag in the SPE.
Kind regards, Jamie
From: Bohdan.Hunko--- via TF-M tf-m@lists.trustedfirmware.org Sent: Friday, December 15, 2023 3:00 PM To: tf-m@lists.trustedfirmware.org Cc: Hennadiy.Kytsun@infineon.com; Roman.Mazurak@infineon.com; Oleksii.Khyzhniak-EE@infineon.com; Nazar.Chornenkyy@infineon.com Subject: [TF-M] How to disable all interrupts on ARM V8?
Hi all,
From what I have seen, looks like __disable_irq() only disables non-secure interrupts when called from NSPE on ARM v8 arch.
Am I correct? If so then how can I disable all interrupts (including secure interrupts) from NSPE? - We need this for critical section and other critical code.
Regards, Bohdan Hunko
Cypress Semiconductor Ukraine Engineer CSUKR CSS ICW SW FW Mobile: +38099 50 19 714 Bohdan.Hunko@infineon.commailto:Bohdan.Hunko@infineon.com