Hello,
I am pleased to announce the new v1.6.0 released of TF-M project.
New major features are:
* MCUboot updated to v1.9.0.
* Mbed TLS updated to v3.1.0 (Support all required PSA Crypto APIs).
* Enabled Secure Function (SFN) Model Partition compliance in IPC backend.
* Interrupt support (both SLIH/FLIH) for the SFN backend.
* MM-IOVEC Support for the SFN backend.
* The following Secure Partitions are converted to SFN model:
* Protected Storage
* Internal Trusted Storage
* Initial Attestation
* FF-M v1.1 SFN Model supported in Profile Small.
* HAL Separation of Library Model and IPC/SFN backend.
* FP support for Armv8.1-M Mainline for IPC backend.
* Simplified build output message and configurable output.
* Halting instead of rebooting on panic in debug build type.
* Automated testing of MCUboot BL2.
* A new driver interface for the CC-312 runtime library as specified in the PSA Unified Driver spec [1]_.
* Added reference bootloader stage 1 (BL1) bootloader for certain platforms.
* A new CC312 ROM library for the BL1.
* Updated documentation structure.
The changes tagged by TF-Mv1.6.0 and located in the release/v1.6.x<https://review.trustedfirmware.org/q/project:TF-M%252Ftrusted-firmware-m+br…> branch at the moment.
In short, they will be integrated with the main branch and be available from there.
Thanks everyone for contribution, review and support this milestone.
Anton
Hi,
The next Technical Forum is planned on Thursday, April 28, 7:00-8:00 UTC (East time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi everyone,
We have discussed the design proposal of supporting secure Flash in tf-m
framework via this mailing list before,now the implementation code of this
external trusted secure storage partition has been uploaded to tf-m-extras
repo for review:
https://review.trustedfirmware.org/c/TF-M/tf-m-extras/+/14953
And the binary component of this patch has also been uploaded to
tf-binaries repo:
https://review.trustedfirmware.org/c/tf-binaries/+/14954
For easy understanding please refer to this document first:
https://review.trustedfirmware.org/c/TF-M/tf-m-extras/+/14953/1/partitions/…
Looking forward to your comments and suggestions.
Best Regards,
Poppy Wu
吴偏偏
Macronix Microelectronics (Suzhou) Co.,Ltd
旺宏微电子(苏州)有限公司
http://www.mxic.com.cn
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Hello,
The branch release/1.6.x<https://git.trustedfirmware.org/TF-M%2Ftrusted-firmware-m.git/log/?h=refs%2…> has been created, indicating the project feature's freeze and beginning the release process. Expecting to place RC1 tag asap, after successful run of the basic tests.
Let me remind that the code is not frozen, and development can be continued on the main branch.
Thanks,
Anton
Hi All,
TF-M Open CI is back to normal now.
Please feel free to use it.
Thanks,
Xinyu
From: Xinyu Zhang via TF-M <tf-m(a)lists.trustedfirmware.org>
Sent: Monday, April 18, 2022 12:06 PM
To: TF-M mailing list <tf-m(a)lists.trustedfirmware.org>
Subject: [TF-M] TF-M Open CI Down
Hi All,
Sorry to inform you that TF-M Open CI is down for the time being because of Jenkins upgrade.
I'll let you know once it is back to normal.
Apologize for any inconvenience!
Thanks,
Xinyu
Hi All,
Sorry to inform you that TF-M Open CI is down for the time being because of Jenkins upgrade.
I'll let you know once it is back to normal.
Apologize for any inconvenience!
Thanks,
Xinyu
Hi,
The forum is cancelled because of the empty agenda and the assumption that many of us in the west time zone will have a long weekend this week.
Thanks,
Anton
From: Anton Komlev via TF-M <tf-m(a)lists.trustedfirmware.org>
Sent: Wednesday, April 6, 2022 12:43 PM
To: tf-m(a)lists.trustedfirmware.org
Cc: nd <nd(a)arm.com>
Subject: [TF-M] Technical Forum call - April 14
Hi,
The next Technical Forum is planned on Thursday, April 14, 15:00-16:00 UTC (West time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hello!
My name is Oleg.
I'm working on TF-M Isolation Level 3 testing and I need to develop test cases list for it.
Could you be so kind to provide me the test cases list? May be you know where I can find it by myself?
Also I have test cases list for Isolation Leve 2. Am I right that it can be reused for Isolation Level 3 with some changes?
I will be very appreciate for any help.
Thank you so much,
Oleg Dokanov
Hi,
The next Technical Forum is planned on Thursday, April 14, 15:00-16:00 UTC (West time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi all,
Please be advised that the Mbed TLS GitHub migration is complete. The new home for Mbed TLS is:
https://github.com/Mbed-TLS
We recommend updating your project, checkouts, etc to point at the new repository, but it's not urgent as everything will continue to work for some time via automatic redirection.
Also please note that our project boards, which we use for planning upcoming work via epics, and tracking current activity, have moved. They are now available here:
Epics board: https://github.com/orgs/Mbed-TLS/projects/1
Current activity: https://github.com/orgs/Mbed-TLS/projects/2
Thanks
Dave Rodgman
On 22/03/2022, 14:52, "Dave Rodgman via Mbed-tls-announce" <mbed-tls-announce(a)lists.trustedfirmware.org> wrote:
Hi all,
Please note that in the next couple of weeks, we will migrate Mbed TLS to a new GitHub organisation. Your existing scripts, links etc for accessing Mbed TLS on GitHub should not be affected.
This will change the url from https://github.com/ARMmbed/mbedtls to https://github.com/Mbed-TLS/mbedtls . GitHub will redirect any accesses to the old URL for the foreseeable future, but we would recommend updating your links once the migration is complete.
All of the Mbed TLS repositories will migrate to this new organisation, i.e.:
mbedtls
mbedtls-docs
mbedtls-test
Thanks
Dave Rodgman
--
Mbed-tls-announce mailing list -- mbed-tls-announce(a)lists.trustedfirmware.org
To unsubscribe send an email to mbed-tls-announce-leave(a)lists.trustedfirmware.org
Hi,
The next Technical Forum is planned on Thursday, March 31, 7:00-8:00 UTC (East time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hello,
Quite some time ago there was a proposal to move TF-M into GitHub. The main motivation is: more convenient review process, the Wiki for knowledge sharing and issue tracking facility.
This idea had been discussed multiple times in TSC. The following options were considered:
1. Hybrid: Add TF-M on GitHub with 2 ways synchronization between GitHub and existing Git/Gerrit
2. GitHub only: Move to GitHub completely and drop Gerrit.
3. Mirror: Create a read-only mirror on GitHub. TF-M review process stays in Gerrit but Wiki and issue tracking are on GitHub.
4. Nothing: Stay on Gerrit as good enough solution.
The options are ordered by complexity and cost each has pros and cons. The Mirror option (3) seeing as the best compromise and practically affordable in a short time.
Please share your opinion and comments on the topic with any dependencies or specific requirements to be considered.
Thanks,
Anton
Hi All,
Please find the link to the TrustedFirmware Community Code of Conduct here:
https://developer.trustedfirmware.org/w/collaboration/community_guidelines/…
Trusted Firmware has a very diverse and global developer community. It is
important that we adhere to the code of conduct in all our interactions.
For some of you all this may be new and for others just a gentle reminder.
In either case, if you have any questions, please feel free to reach out to
me directly.
And thanks to you all for your contributions to the TrustedFirmware
community!
Best regards,
Don Harbin
TrustedFirmware Community Manager
don.harbin(a)linaro.org
Hi.
I've been working on making an example on how an application can use the secure interrupts in a secure partition in TF-M.
During this I've encountered an issue where the secure partition will not be scheduled to process the secure interrupt signal in certain conditions.
I've compared it to the current SLIH and FLIH test cases to my observed behaviour and I could see that they did not have this problem.
I've created a test-case that triggers the problem [0].
In the mailing list I can see that this was actually discussed recently [1]
The summary is that secure partitions will not be scheduled to process a secure interrupt signal when the interrupt is interrupting the NSPE.
I could not find that this was documented anyway, but maybe I have overlooked.
In any case I find this behaviour very unexpected and I would like to know if this is indeed a design decision and the behaviour has to be this way?
If I wanted to do some processing in the secure partition context it would now mean that I have to get the NSPE to trigger this through a secure partition call.
This seems like a limitation to me .
I'd like to know what would be the issue with scheduling the partition once it now has the signal asserted.
I've done a quick test with scheduling the partition at this point with [2] and this now works as I expect it to.
I'd be happy to follow up with submitting a change to schedule the partition as done in [2] if that is an acceptable solution.
[0] https://github.com/joerchan/tf-m-tests/commit/d9f0a3a7653b594d0fa797d9e0bca…
[1] https://lists.trustedfirmware.org/archives/list/tf-m@lists.trustedfirmware.…
[2] https://github.com/joerchan/sdk-trusted-firmware-m/commit/e5512c6e8b2bad95c…
Hi,
Just a reminder that the MCUboot version has been upgraded to v1.9.0<https://github.com/mcu-tools/mcuboot/releases/tag/v1.9.0> in TF-M. If you are using the local MCUboot repo, then you need to update it to that version to avoid build error.
Regards,
Sherry Zhang
Hi,
The next Technical Forum is planned on Thursday, March 17, 15:00-16:00 UTC (West time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hello,
TF-M release v1.6.0 will be shifted from April 15 to April 28. The main reason is Easter holiday and expected lack of availability from community and platform owners around that date. Feature freeze will be moved to April 6th when the release branch will be created.
Please update your plans accordingly.
Please let me know if this change make difficulty for you and better date is possible.
Thanks,
Anton
Hi all,
I want to simplify the flag TFM_PLATFORM in build system. TF-M now already supports two different ways to choose specific platform, for example AN521:
- Absolute path: '<tf-m path>/platform/ext/target/arm/mps2/an521'
- Relative path: 'arm/mps2/an21'
Recently I have uploaded a [tf-m patch]<https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/14260> to support platform name:
- Platform name: 'an521'
I think it will be more convenient for developers to use:
- Users don't need to remember and type the absolute or relative path, only target platform name is enough.
- If the structure of certain platform is changed, the default build command of TFM_PLATFORM is same.
I'd be very grateful if you can give any suggestion or enhancement for me. Thanks.
Best Regards
Jianliang Shen
Dear All,
I view the tf-m source code for the first time, and many of the code
details can not be make clear. So ..,
where may I find the design documents of spm, for example:
trusted-firmware-m-TF-Mv1.5.0\secure_fw\spm\cmsis_func and cmsis_psa
software modules.
Best Regards
Wang Zhilei | Software
Beken Corporation
----------------------------------------------------------------------------
---------------------------------------------------------
Hi,
The next Technical Forum is planned on Thursday, March 3, 7:00-8:00 UTC (Asian time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi colleagues!
Could we get a list of MISRA/CERT-C violations that were found by tf-m Coverity CI, as example from https://ci.trustedfirmware.org/job/tf-m-coverity/lastSuccessfulBuild/
Also (if it possible), could you provide Coverity configs to help align this tool setup on our side to CI and to check all changes before any pool requests?
Best regards,
Kostiantyn Tkachov
Cypress Semiconductor Ukraine
Firmware Security
Hello,
I am writing to you asking help because we are having problems when I try to compile the Trusted Firmware M from source code.
I downloaded the code from the official repository: https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git
I moved to the last TAG: TF-Mv1.5.0
I am following this tutorial for PSOC64 platform https://tf-m-user-guide.trustedfirmware.org/platform/ext/target/cypress/pso…
When I execute the first cmake command indicating the platform and the toolchain everything works well: cmake -DTFM_PLATFORM=cypress/psoc64 -DTFM_TOOLCHAIN_FILE=../toolchain_GNUARM.cmake ..
The problems appears when I build the code using the second cmake command: cmake --build cmake_build -- -j
I got this output
[cid:image003.jpg@01D82A77.95B43640]
/home/admin/Escritorio/trusted-firmware-m/lib/ext/t_cose/crypto_adapters/t_cose_psa_crypto.c: In function 't_cose_crypto_pub_key_verify':
/home/admin/Escritorio/trusted-firmware-m/lib/ext/t_cose/crypto_adapters/t_cose_psa_crypto.c:145:5: error: conversion to non-scalar type requested
145 | verification_key_psa = (psa_key_handle_t)verification_key.k.key_handle;
| ^~~~~~~~~~~~~~~~~~~~
/home/admin/Escritorio/trusted-firmware-m/lib/ext/t_cose/crypto_adapters/t_cose_psa_crypto.c: In function 't_cose_crypto_pub_key_sign':
/home/admin/Escritorio/trusted-firmware-m/lib/ext/t_cose/crypto_adapters/t_cose_psa_crypto.c:194:5: error: conversion to non-scalar type requested
194 | signing_key_psa = (psa_key_handle_t)signing_key.k.key_handle;
| ^~~~~~~~~~~~~~~
/home/admin/Escritorio/trusted-firmware-m/lib/ext/t_cose/crypto_adapters/t_cose_psa_crypto.c: In function 't_cose_crypto_sig_size':
/home/admin/Escritorio/trusted-firmware-m/lib/ext/t_cose/crypto_adapters/t_cose_psa_crypto.c:245:5: error: conversion to non-scalar type requested
245 | signing_key_psa = (psa_key_handle_t)signing_key.k.key_handle;
| ^~~~~~~~~~~~~~~
secure_fw/partitions/internal_trusted_storage/CMakeFiles/tfm_psa_rot_partition_its.dir/build.make:425: recipe for target 'secure_fw/partitions/internal_trusted_storage/CMakeFiles/tfm_psa_rot_partition_its.dir/__/__/__/lib/ext/t_cose/crypto_adapters/t_cose_psa_crypto.o' failed
make[2]: *** [secure_fw/partitions/internal_trusted_storage/CMakeFiles/tfm_psa_rot_partition_its.dir/__/__/__/lib/ext/t_cose/crypto_adapters/t_cose_psa_crypto.o] Error 1
make[2]: *** Waiting for unfinished jobs....
CMakeFiles/Makefile2:1347: recipe for target 'secure_fw/partitions/internal_trusted_storage/CMakeFiles/tfm_psa_rot_partition_its.dir/all' failed
make[1]: *** [secure_fw/partitions/internal_trusted_storage/CMakeFiles/tfm_psa_rot_partition_its.dir/all] Error 2
Makefile:135: recipe for target 'all' failed
make: *** [all] Error 2
There are the version of the software that are using:
arm-none-eabi-gcc (GNU Arm Embedded Toolchain 10.3-2021.10) 10.3.1 20210824 (release)
cmake version 3.23.0-rc2
It seems strange to me that there are compilation errors in the source code, that's why I am writing this mail, in case there is a bug in the code.
Best regards.
Antonio Javier Cabrera Gutierrez
Infineon Technologies AG
PhD Candidate
R&D Engineer
IFAG BEX RDE RDF ISS
Office: +49 89 234 36403
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Hi all,
We are currently testing the tfm-m implementation on a STMicroelectronic chip: stm32u5 board.
This stm32u5 has a special register: SYSCFG_CSLOCKR (see https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbase…). This register allows to lock the PRIS bit of the AIRCR register from further modification.
The issue here is that, in the ST implementation, thanks to this SYSCFG_CSLOCKR, the PRIS bit of the AIRCR is locked at boot (Reset_Handler in file startup_stm32u5xx_s.c). Resulting in the function tfm_arch_set_secure_exception_priorities() not being able to set the PRIS bit of the AIRCR. This situation lead to big issues at runtime as interrupt priority of NSPE are able to pre-empt interrupt of SPE.
Disabling the locking of PRIS bit solve our problem but currently we don't see a clean way to integrate chip specific security features (something like callback/tfm_hal_ ) after the function tfm_arch_set_secure_exception_priorities() has been called.
What would be the best way to fix the current issue which could also arise on other platform ?
Regards,
Romain
Hi all,
As part of the documentation improvements, a new design proposal guideline [1] is proposed to replace and simplify the current process.
The basic idea is to encourage developers to share their design via mailing list and tech forum, without a well-formatted design document.
If developers prefer a document for a new feature, please provide an integration guide/user manual instead.
Please check the details in the patch below.
[1] https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/14104
The rendered html version: https://ci-builds.trustedfirmware.org/static-files/KTOoRMhB4VsgNQFkdMgWZcZG…
Best regards,
Hu Ziji
Hello,
I am trying to write an Application RoT for a research project I am a part of. I have run into an issue that I have been unable to solve independently.
My problem is the unexpected behavior of psa_wait() when using signal masks.
I have two signals, TFM_TIMER1_IRQ_SIGNAL and TFM_SECURE_FUNCTION_SIGNAL. The TIMER1_IRQ signal is triggered by an FLIH interrupt handler that returns TFM_FLIH_SIGNAL. The interrupt is triggered every 1 second by TIMER1. The TFM_SECURE_FUNCTION_SIGNAL is triggered by a periodic function call from the NSPE (a Zephyr thread) and is called every 10 seconds.
Observed result:
If PSA_WAIT_ANY is used as a signal mask, the TIMER0_IRQ_SIGNAL will only be received when TFM_SECURE_FUNCTION_SIGNAL is received, ergo, every 10 s. Thus any stage 2 handling of an interrupt would be missed.
If TFM_TIMER1_IRQ_SIGNAL is used as a signal mask, the signal will be received every 1 s as expected. The TFM_SECURE_FUNCTION_SIGNAL will never be received, as can be expected in the NSPEtoo.
I have tried a "hybrid approach" where I call psa_wait(TFM_TIMER1_IRQ_SIGNAL, PSA_BLOCK) /* handle signals .... */ and then psa_wait(TFM_SECURE_FUNCTION_SIGNAL, PSA_POLL). The stage 2 IRS is called, and the secure function is also called. But not with the regularity that I would like.
Am I missing something obvious? I have read the Secure Interrupt Integration Guide and carefully studied the SLIH and FLIH test services for the TF-M regression tests. Have I forgotten to reset a signal somewhere? Does the interrupt not preempt the NSPE?
I would be immensely grateful for any or all responses. If you need more information, please let me know.
Best wishes,
Martin Gunnarsson
PhD Student
RISE Research Institutes of Sweden & Lund University
Complete code of my Application RoT:
#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>
#include "tfm_api.h"
#include "tfm_secure_api.h"
#include "psa/service.h"
#include "tfm_sp_log.h"
#include "psa_manifest/pid.h"
#include "psa_manifest/tfm_secure_partition.h"
#include <hal/nrf_gpio.h>
#include <hal/nrf_timer.h>
#include <helpers/nrfx_reset_reason.h>
#include <nrf_board.h>
#include <region_defs.h>
#define TIMER_RELOAD_VALUE (1*1024*1024)
static volatile uint32_t interrupt_ctr = 0;
static volatile uint32_t function_ctr = 0;
static void timer_init(NRF_TIMER_Type * TIMER)
{
nrf_timer_mode_set(TIMER, NRF_TIMER_MODE_TIMER);
nrf_timer_bit_width_set(TIMER, NRF_TIMER_BIT_WIDTH_32);
nrf_timer_frequency_set(TIMER, NRF_TIMER_FREQ_1MHz);
nrf_timer_cc_set(TIMER, NRF_TIMER_CC_CHANNEL0, TIMER_RELOAD_VALUE);
/* Clear the timer once event is generated. */
nrf_timer_shorts_enable(TIMER, NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK);
}
static void timer_stop(NRF_TIMER_Type * TIMER)
{
nrf_timer_task_trigger(TIMER, NRF_TIMER_TASK_STOP);
nrf_timer_int_disable(TIMER, NRF_TIMER_INT_COMPARE0_MASK);
nrf_timer_event_clear(TIMER, NRF_TIMER_EVENT_COMPARE0);
}
static void timer_start(NRF_TIMER_Type * TIMER)
{
timer_stop(TIMER);
nrf_timer_task_trigger(TIMER, NRF_TIMER_TASK_CLEAR);
nrf_timer_int_enable(TIMER, NRF_TIMER_INT_COMPARE0_MASK);
nrf_timer_task_trigger(TIMER, NRF_TIMER_TASK_START);
}
static void timer_event_clear(NRF_TIMER_Type *TIMER)
{
nrf_timer_event_clear(TIMER, NRF_TIMER_EVENT_COMPARE0);
}
void tfm_secure_controller_secure_timer_start(void)
{
timer_init(NRF_TIMER1);
timer_start(NRF_TIMER1);
}
void tfm_secure_controller_secure_timer_clear_intr(void)
{
timer_event_clear(NRF_TIMER1);
}
psa_flih_result_t tfm_timer1_irq_flih(void)
{
tfm_secure_controller_secure_timer_clear_intr();
interrupt_ctr++;
return PSA_FLIH_SIGNAL;
}
static psa_status_t tfm_sp_secure_function_ipc(psa_msg_t *msg)
{
function_ctr++;
LOG_INFFMT("Secure function called %u times, interrupt ctr: %u\n", function_ctr, interrupt_ctr );
return PSA_SUCCESS;
}
void tfm_sp_secure_function(psa_msg_t *msg) {
psa_status_t status;
status = tfm_sp_secure_function_ipc(msg);
psa_reply(msg->handle, status);
}
void tfm_sp_entry(void)
{
LOG_INFFMT("Secure Partition: Init\n");
tfm_secure_controller_secure_timer_start();
psa_irq_enable(TFM_TIMER1_IRQ_SIGNAL);
psa_signal_t signals = 0;
uint32_t ctr = 0;
while (1) {
signals = psa_wait(TFM_TIMER1_IRQ_SIGNAL, PSA_BLOCK);
if ( (signals & TFM_TIMER1_IRQ_SIGNAL) == TFM_TIMER1_IRQ_SIGNAL) {
ctr++;
LOG_INFFMT("FLIH stage 2 %u\n", interrupt_ctr);
psa_reset_signal(TFM_TIMER1_IRQ_SIGNAL);
}
if ( ctr % 10 == 0 ) {
signals = psa_wait(PSA_WAIT_ANY, PSA_POLL);
if ( (signals & TFM_SECURE_FUNCTION_SIGNAL) == TFM_SECURE_FUNCTION_SIGNAL) {
psa_msg_t msg;
psa_get(signals, &msg);
tfm_sp_secure_function(&msg);
}
}
}
}
Hi,
in the effort to ease debugging by supporting a choice between halting and rebooting
we are introducing a new HAL API:
void tfm_hal_system_halt(void)
which by default (weak) does:
__disable_irq();
while(1) { __WFE(); }
CPUs cannot halt. But they can sleep until they are awoken in a loop, which is pretty close.
tfm_hal_system_halt() is, when configured so, used by tfm_core_panic() which is why we disable irqs
to stop all threads of execution, not just the thread that is executing.
Currently it is proposed that tfm_core_panic() halts when TFM_HALT_ON_CORE_PANIC is ON
and otherwise reboots.
TFM_HALT_ON_CORE_PANIC is default ON if and only if Debug mode is enabled.
Any feedback to these changes are welcome, and if any platform needs to halt in a different manner
then a contribution would be welcome as well.
https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/13839
Hi, all
I'd like to share two new refinements in TF-M test repo to you.
l The struct variable test_result_t has been removed from the definition of struct variable test_t. It is unnecessary to set an initial value of test result for each case. With this change, the binary size will be reduced. Please see [test patch]<https://review.trustedfirmware.org/c/TF-M/tf-m-tests/+/13822/4> for more details.
l The flag TEST_SKIPPED has been added into enum variable test_status_t, works with TEST_PASSED and TEST_FAILED. TEST_SKIPPED indicates that the test case is skipped in runtime when the test environment is unavailable. Please ee [test patch]<https://review.trustedfirmware.org/c/TF-M/tf-m-tests/+/13826/5> for more details.
Hope these two changes can help your work in the future. Please let me know if anything can be improved. Thanks!
Best Regards
Jianliang Shen
Hi,
the performance improvement presentation[0] reports a FF PSA API overhead
of 20 000 CPU cycles for the psa_call. Which is 300 us for a 64MHz CPU.
This is quite a lot of instructions and I am concerned about whether
real world embedded application's will have time to call these secure services.
I'm interested in isolation level 2.
I understand that it is not possible to have isolation level 2 with library mode. But what about SFN
mode, could that eventually support isolation level 2?
If not, what is the current status of optimizing the service call overhead for IPC.
Is it considered to be as optimized as it can be or is there still hope for optimizing further?
[0] https://www.trustedfirmware.org/docs/tf-m_forum_20211209-TF-M_Performance-I…
Hi,
The next Technical Forum is planned on Thursday, February 17, 15:00-16:00 UTC (US time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi,
We got a tiny update merged in level 3 ld/sct files to support partition runtime:
https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/13925
Platforms with level 3 support please have a test and report issue here if spotted. We have internally tested MPS2 and MUSCA_B1.
Thanks.
/Ken
Hi,
it seems we could try to be more consistent with fault handling.
The current default behaviour is:
Error code returned from an SPE function? Reboot.
MemFault/HardFault/SecureFault in the SPE? Halt.
Null-pointer dereference from the NSPE? (results in a secure fault for cortex-m) Halt.
Should we perhaps consistently halt or consistently reboot for these three cases
and allow this to be configurable?
It is not clear to me why an error returned from a function results in a reboot, whereas a Hardfault does not.
They both indicate a fault in the SPE.
At the very least the behaviour should be configurable, which this PR is a step towards:
https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/13839
Commit 27f9a49508547320c50056a52a372674c27771eb seems to have missed changing ns_agent_mailbox, breaking dual core. I'd send a patch, but I's not immediately obvious what it should look like...
Seems like a good change, but inadequately reviewed?
Chris Brand
Cypress Semiconductor (Canada), Inc.
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Hi,
Let's cancel the forum tomorrow due to the empty agenda and the holiday time in Asia.
Best regards,
Anton
From: Anton Komlev via TF-M <tf-m(a)lists.trustedfirmware.org>
Sent: Thursday, January 27, 2022 4:36 PM
To: tf-m(a)lists.trustedfirmware.org
Cc: nd <nd(a)arm.com>
Subject: [TF-M] Technical Forum call - Feb 3
Hi,
The next Technical Forum is planned on Thursday, Feb 3, 7:00-8:00 UTC (Asia time zone).
Please reply on this email with your proposals for agenda topics.
This slot is in Chinese New Year celebration period so we can expect fewer participants from Asia.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi everyone,
I have a few questions related to TF-M code:
1. Default implementation of tfm_hal_system_reset(void) from platform/ext/common/tfm_platform.c<https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/e…> just calls NVIC_SystemReset(), but some ARM platform, take musca_b1 for example, reimplement it (platform/ext/target/arm/musca_b1/sse_200/tfm_hal_platform.c<https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/e…> ).
Custom implementations tend to also disable and clean IRQ and call mpc_revert_non_secure_to_secure_cfg();
Is there any benefits of doing that??? If so then what those benefits are?
1. tfm_core_panic() (secure_fw/spm/ffm/utilities.c<https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/secure_fw/…>) when TFM_FIH_PROFILE_ON is defined calls fih_delay() and tfm_hal_system_reset() twice. Is this done to ensure that tfm_hal_system_reset() will be called (even if first one was skipped there is second one)? And if so, can a comment be added there to highlight that intention?
Regards,
Bohdan Hunko
Cypress Semiconductor Ukraine
Engineer
CSUKR CSS ICW SW FW
Mobile: +38099 50 19 714
Bohdan.Hunko(a)infineon.com<mailto:Bohdan.Hunko@infineon.com>
Hi,
The next Technical Forum is planned on Thursday, Feb 3, 7:00-8:00 UTC (Asia time zone).
Please reply on this email with your proposals for agenda topics.
This slot is in Chinese New Year celebration period so we can expect fewer participants from Asia.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi All,
Please do use the tf-m-tests version specified in TF-M CMake configs (TFM_TEST_REPO_VERSION in trusted-firmware-m/lib/ext/tf-m-tests/repo_config_default.cmake), otherwise there might be some unexpected build errors.
Please let us know if there is any problem.
Thanks,
Xinyu
Hi All,
TF-M Open CI is back to normal. Please feel free to use.
Thanks,
Xinyu
From: Xinyu Zhang
Sent: Monday, January 17, 2022 4:05 PM
To: TF-M mailing list <tf-m(a)lists.trustedfirmware.org>
Cc: nd <nd(a)arm.com>
Subject: TF-M Open CI Not Stable Right Now
Hi All,
Sorry to inform you that TF-M Open CI is not stable right now. Jobs are likely to come into unexpected failure.
I'll keep following up with the latest information.
Sorry for any inconvenience!
Thanks,
Xinyu
Hi,
The next Technical Forum is planned on Thursday, January 20, 15:00-16:00 UTC (US time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
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Hi All,
Sorry to inform you that TF-M Open CI is not stable right now. Jobs are likely to come into unexpected failure.
I'll keep following up with the latest information.
Sorry for any inconvenience!
Thanks,
Xinyu
Hi,
ER_INITIAL_PSP section was used as the Trustzone NS Agent partition stack in IPC model.
Since Trustzone NS Agent partition has changed to use private variables as its stack, ER_INITIAL_PSP related definitions and references can be removed.
Change: https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/13186
This change involves all the platforms for IPC model, it removes:
* Definition of ER_INITIAL_PSP section in the linker script
* Reference of ER_INITIAL_PSP for isolation configuration in platform HALs
This can simplify the linker script a bit.
This patch is going to be put there for a while as there are holidays, but please do review it when you see this mail. Plan to merge it before end of Jan, as soon as all concerns get addressed (if there are).
Regards,
Mingyang
Hi all,
I'd like to introduce a code size analyse tool to you. The tool is developed to help optimize TF-M code size by gathering the data from map file and output friendly.
These python scripts can
- Get a database to implement data tables from ARMCLANG or GNUARM map file.
- Supply an UI for developers to scan sorted information of sections, libraries, object files, functions and data.
- Help analyse the biggest or smallest targets in certain image. It can also help search functions or data to locate their address and detail information.
- Diff two databases to see the code size increment or decrement between two different build results.
The patch is: [tf-m-tools]<https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/12665>, it also contains the document for users.
Hope this tool can help you measure code size in the daily work. Please let me know if anything can be improved. I'd like to merge this tool this Friday if no critical comment.
Best Regards
Jianliang Shen
Here is what I could find on Zephyr:
https://docs.zephyrproject.org/1.14.1/reference/power_management/index.html
Any thoughts from anybody on this topic.
thanks
Suresh Marisetty
Infineon Semiconductor Corporation
From: Anton Komlev <Anton.Komlev(a)arm.com>
Sent: Thursday, January 13, 2022 2:19 AM
To: Joseph Yiu <Joseph.Yiu(a)arm.com>; Marisetty Suresh (CYSC CSS ICW SW SSE) <Suresh.Marisetty(a)infineon.com>
Subject: RE: Power management and TFM
Caution: This e-mail originated outside Infineon Technologies. Do not click on links or open attachments unless you validate it is safe<https://intranet-content.infineon.com/explore/aboutinfineon/rules/informati…>.
Hi Suresh,
As you noted, the power management topic is not covered by TF-M, leaving it for a platform or project level handling. Would you like to discuss the topic on TF-M Tech Forum and check what community thinks about it?
Best regards,
Anton
From: Joseph Yiu <Joseph.Yiu(a)arm.com<mailto:Joseph.Yiu@arm.com>>
Sent: Wednesday, January 12, 2022 8:52 PM
To: Suresh.Marisetty(a)infineon.com<mailto:Suresh.Marisetty@infineon.com>; Anton Komlev <Anton.Komlev(a)arm.com<mailto:Anton.Komlev@arm.com>>
Subject: RE: Power management and TFM
Hi Suresh,
> Power management does have an impact on security flows and how it is done.
Agree.
> Not sure if there is a standardized framework and application note on how it can be done on Corte-M with or without Secure Enclave model
Unfortunately there is no standardization of power management interface for Cortex-M systems today.
And given that the low power implementation varies between different vendors significantly, trying to define a power control interface is going to be very challenging.
By the way, I noticed you reply to me only. Is that intentional or would you want to have this conversation on the email list?
Regards,
Joseph
From: Suresh.Marisetty(a)infineon.com<mailto:Suresh.Marisetty@infineon.com> <Suresh.Marisetty(a)infineon.com<mailto:Suresh.Marisetty@infineon.com>>
Sent: 12 January 2022 18:58
To: Joseph Yiu <Joseph.Yiu(a)arm.com<mailto:Joseph.Yiu@arm.com>>
Cc: nd <nd(a)arm.com<mailto:nd@arm.com>>
Subject: RE: Power management and TFM
HI Anton and Joseph,
Power management does have an impact on security flows and how it is done. This is a town down architecture/implementation starting with NSPE and down with expected behavior of SPE (secure boot, TFM context management, etc.), cold boot, warm boot, deep-sleep, hibernate and active modes.
On the Cortex-A, there is PSCI framework couple with ACPI. Not sure if there is a standardized framework and application note on how it can be done on Corte-M with or without Secure Enclave model.
thanks
Suresh Marisetty
Infineon Semiconductor Corporation
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org<mailto:tf-m-bounces@lists.trustedfirmware.org>> On Behalf Of Joseph Yiu via TF-M
Sent: Monday, December 20, 2021 8:04 AM
To: tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Cc: nd <nd(a)arm.com<mailto:nd@arm.com>>
Subject: Re: [TF-M] Power management and TFM
Caution: This e-mail originated outside Infineon Technologies. Do not click on links or open attachments unless you validate it is safe<https://intranet-content.infineon.com/explore/aboutinfineon/rules/informati…>.
Hi Suresh, Anton,
This is an interesting topic :-)
Armv8-M processors has some power management registers that can be restricted to Secure world access only.
System Control Register (SCR)
- Bit 2 SLEEPDEEP - 0 = Normal Sleep, 1 = Deep Sleep (this can also enable WIC feature). Access permission depends on SLEEPDEEPS.
- Bit 3 SLEEPDEEPS - 0 - NS privileged world can r/w to SLEEPDEEP, 1 - SLEEPDEEP is RAZ/WI to NS privileged world
(This is applicable to Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55)
Cortex-M55 also has Implementation defined power model control registers (CPDLPSTATE, DPDLPSTATE)
https://developer.arm.com/documentation/101273/0101/Cortex-M55-Processor-le…
If TrustZone is used (AIRCR.BFHFNMINS is 0), then these registers are Secure privileged access only.
So definitely Secure firmware should provide some APIs for Non-secure software for changing the power control settings. However, I would expect that power control APIs would likely to be at a higher level which also manage other system level power control functions (which, as Anton said, device specific). In such case having APIs for modifying SLEEPDEEP and power model control registers is not helpful (or might even end up with confusions - e.g. if a SW developer trying to use both low level and high level APIs at the same time).
Given that a Secure firmware can setup SLEEPDEEPS easily if it wants to allow/disallow access to SLEEPDEEP control, having an API for this might be overkill.
Access to Cortex-M55's power model control registers is more tricky. Would an 'optional' reference API for updating power model control registers (CPDLPSTATE, DPDLPSTATE) be considered?
Regards,
Joseph
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org<mailto:tf-m-bounces@lists.trustedfirmware.org>> On Behalf Of Anton Komlev via TF-M
Sent: 20 December 2021 12:32
To: tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Cc: nd <nd(a)arm.com<mailto:nd@arm.com>>
Subject: Re: [TF-M] Power management and TFM
Hi Suresh,
The power management is out of scope of TF-M core or any PSA service. Such functionality is HW platform specific and may vary depending on HW or SW adaptation capabilities. If you concern about a specific use case, where TF-M support is expected - let's discuss it here.
Hope that helps,
Anton
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org<mailto:tf-m-bounces@lists.trustedfirmware.org>> On Behalf Of Suresh Marisetty via TF-M
Sent: Friday, December 17, 2021 8:11 PM
To: tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Subject: [TF-M] Power management and TFM
Hi,
Wondering if anybody can throw some light on any ongoing efforts on power management on a system with TFM (deep sleep, etc).
thanks
Suresh Marisetty
Infineon Semiconductor Corporation
CYSC CSS ICW SW SSE
Mobile: +5103863997
Suresh.Marisetty(a)infineon.com<mailto:Suresh.Marisetty@infineon.com>
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Hello TFM owners,
I would like to report an issue for ARMv8-MAIN in TFM.
From GCC9, it may use FPU registers (S16~S31) to backup general purpose registers for better performance.
However, TFM’s library mode is not backup and restore FPU registers (S16~S31) base on EXC_RETURN.FType bit in tfm_core_sfn_request.
(Reference for LR.FType https://developer.arm.com/documentation/100235/0004/the-cortex-m33-processo… )
This may causes FPU registers (S16~S31) to be corrupted in tfm_core_sfn_request, if interrupt happens between two SVC call.
Here is an example to reproduce the issue:
1. Task A uses FPU S16 register to backup GPR R0
2. Task A calls psa_import_key() API
3. After the instruction “SVC %[SVC_REQ]” in tfm_core_sfn_request, the CONTROL.FPCA become “NOT active”
4. Enter FreeRTOS PendSV_Handler and schedule to others task.
* Originally, this should backup S16 due to CONTROL.FPCA is active and EXC_RETURN.FType should be 0.
* But, the EXC_RETURN.FType become 1 due to step3. So the S16 is not backup in stack and changed by others task.
1. Another task uses FPU S16 register (overwrite the value of S16 from Task A)
2. Enter FreeRTOS PendSV_Handler and schedule back to Task A
3. psa_import_key is finished and exit from TFM
4. Task A restore GPR R0 from FPU R16
5. Memory access violation in Task A due to incorrect value of GPR R0.
Stacking FPU s16-s31 in tfm_core_sfn_request can fix this problem. Please check the blue instructions. Thank you.
__attribute__((section("SFN"), naked))
int32_t tfm_core_sfn_request(const struct tfm_sfn_req_s *desc_ptr)
{
__ASM volatile(
"PUSH {r4-r12, lr} \n"
"MRS r4, control \n" /* Check FPCA in control register */
"TST r4, #0x04 \n"
"IT NE \n" /* Stacking S16-S31, if CONTROL.FPCA = 1 */
"VSTMDBNE sp!, {s16-s31} \n"
"PUSH {r4} \n" /* Backup CONTROL register */
"PUSH {r4} \n" /* For 8-bytes alignment to prevent xPSR.BIT9 = 1 */
"SVC %[SVC_REQ] \n" /* To remove upon instruction, xPSR.BIT9 should be masked to 0 in prepare_partition_iovec_ctx(…) */
"MOV r4, #0 \n"
"MOV r5, r4 \n"
"MOV r6, r4 \n"
"MOV r7, r4 \n"
"MOV r8, r4 \n"
"MOV r9, r4 \n"
"MOV r10, r4 \n"
"MOV r11, r4 \n"
"BLX lr \n"
"SVC %[SVC_RET] \n"
"POP {r4} \n" /* Restore CONTROL register */
"POP {r4} \n"
"TST r4, #0x04 \n" /* Check FPCA in control register */
"IT NE \n"
"VLDMIANE sp!, {s16-s31} \n" /* Restore S16-S31, if CONTROL.FPCA = 1 */
"POP {r4-r12, pc} \n"
: : [SVC_REQ] "I" (TFM_SVC_SFN_REQUEST),
[SVC_RET] "I" (TFM_SVC_SFN_RETURN)
);
}
Best regards!
Hi Jamie,
The change has been merged. Sorry for the possible inconveniences caused by end of the year holidays.
Best regards,
Anton
From: Jamie Mccrae via TF-M <tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>>
Sent: Tuesday, January 11, 2022 4:03 PM
To: tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Subject: [TF-M] Pending PR needs merging
Hi,
Would it be possible to get this PR merged https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12686 due to a pending update for Zephyr?
Thanks,
Jamie
THIS MESSAGE, ANY ATTACHMENT(S), AND THE INFORMATION CONTAINED HEREIN MAY BE PROPRIETARY TO LAIRD CONNECTIVITY, LLC. AND/OR ANOTHER PARTY, AND MAY FURTHER BE INTENDED TO BE KEPT CONFIDENTIAL. IF YOU ARE NOT THE INTENDED RECIPIENT, PLEASE DELETE THE EMAIL AND ANY ATTACHMENTS, AND IMMEDIATELY NOTIFY THE SENDER BY RETURN EMAIL. THIS MESSAGE AND ITS CONTENTS ARE THE PROPERTY OF LAIRD CONNECTIVITY, LLC. AND MAY NOT BE REPRODUCED OR USED WITHOUT THE EXPRESS WRITTEN CONSENT OF LAIRD CONNECTIVITY, LLC.
Hi,
Would it be possible to get this PR merged https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12686 due to a pending update for Zephyr?
Thanks,
Jamie
THIS MESSAGE, ANY ATTACHMENT(S), AND THE INFORMATION CONTAINED HEREIN MAY BE PROPRIETARY TO LAIRD CONNECTIVITY, LLC. AND/OR ANOTHER PARTY, AND MAY FURTHER BE INTENDED TO BE KEPT CONFIDENTIAL. IF YOU ARE NOT THE INTENDED RECIPIENT, PLEASE DELETE THE EMAIL AND ANY ATTACHMENTS, AND IMMEDIATELY NOTIFY THE SENDER BY RETURN EMAIL. THIS MESSAGE AND ITS CONTENTS ARE THE PROPERTY OF LAIRD CONNECTIVITY, LLC. AND MAY NOT BE REPRODUCED OR USED WITHOUT THE EXPRESS WRITTEN CONSENT OF LAIRD CONNECTIVITY, LLC.
Hi all,
TF-M CI is back to normal. Please feel free to use it. 😊
BR,
Xinyu
From: Xinyu Zhang
Sent: Monday, January 10, 2022 11:07 AM
To: TF-M mailing list <tf-m(a)lists.trustedfirmware.org>
Cc: nd <nd(a)arm.com>
Subject: TF-M Open CI Fails to Run Tests
Hi all,
Sorry to inform you that TF-M Open CI is down for the time being – tests cannot be run.
I’ll let you know as long as CI is back to normal.
Apologize for any inconvenience!
Thanks,
Xinyu
Hi all,
Sorry to inform you that TF-M Open CI is down for the time being - tests cannot be run.
I'll let you know as long as CI is back to normal.
Apologize for any inconvenience!
Thanks,
Xinyu
Hi,
Thank Chris made a couple of changes to move the mailbox mechanism from a kernel-coupled one into a partition-based one, which simplifies the programming model much.
And mailbox-related platforms (musca-b1 secure enclave and corstone 1000) may get affected after merged, please mentioned platform owners take a try on these patches. Another solution is we can merge them and then fix the problems found.
Will wait for one more week for the last patch (Patches no affecting platforms out of PSoC are merged already).
I think checkout this one should bring all related changes into local:
https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12311
Feel free to comment, thanks.
/Ken
Hi,
The next Technical Forum is planned on Thursday, Jan 6, 7:00-8:00 UTC (Asia time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi everyone,
While taking a look into PSA header files from interface/include/psa/ folder I have found out that they are actually slightly different from PSA headers in build_folder/lib/ext/mbedcrypto-src/include/psa/ folder.
Here is list of files that are different:
* crypto.h
* crypto_compat.h
* crypto_extra.h
* crypto_sizes.h
* crypto_struct.h
* crypto_types.h
* crypto_values.h
My expectation was that PSA interface (header files) should be the same in both folders.
Maybe we should use only one version of those files (remove files from interface/include/psa/ and just use files from build_folder/lib/ext/mbedcrypto-src/include/psa/)?
Regards,
Bohdan Hunko
Cypress Semiconductor Ukraine
Engineer
CSUKR CSS ICW SW FW
Mobile: +38099 50 19 714
Bohdan.Hunko(a)infineon.com<mailto:Bohdan.Hunko@infineon.com>
Back after the holidays I have tested a few builds and I've noticed that
a few builds fail a bunch of tests.
Fails on all tool chains.
Is this a known issue?
psoc64, musca_s1 works.
Musca_B1 (nxp lpcxpresso55s69 also fails:
PS D:\Projects\tf-m6\trusted-firmware-m\armclang> cmake -GNinja -S .. -B
. -DTFM_PLATFORM=arm/musca_b1/sse_200
"-DTFM_TOOLCHAIN_FILE=..\toolchain_ARMCLANG.cmake" -DTEST_NS=ON
-DTEST_S=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo -DBL2=ON
...
Running Test Suite PSA internal trusted storage S interface tests
(TFM_S_ITS_TEST_1XXX)...
> Executing 'TFM_S_ITS_TEST_1001'
Description: 'Set interface'
Set should not fail with valid UID (Failed at
D:/Projects/tf-m6/trusted-firmware-m/armclang/lib/ext/tfm_test_repo-src/test/suites/its/its_tests_common.c:32)
TEST: TFM_S_ITS_TEST_1001 - FAILED!
> Executing 'TFM_S_ITS_TEST_1002'
Description: 'Set interface with create flags'
Set should not fail with no flags (Failed at
D:/Projects/tf-m6/trusted-firmware-m/armclang/lib/ext/tfm_test_repo-src/test/suites/its/its_tests_common.c:91)
TEST: TFM_S_ITS_TEST_1002 - FAILED!
> Executing 'TFM_S_ITS_TEST_1003'
Description: 'Set interface with NULL data pointer'
Set should succeed with NULL data pointer and zero length (Failed at
D:/Projects/tf-m6/trusted-firmware-m/armclang/lib/ext/tfm_test_repo-src/test/suites/its/its_tests_common.c:115)
TEST: TFM_S_ITS_TEST_1003 - FAILED!
> Executing 'TFM_S_ITS_TEST_1004'
Description: 'Set interface with write once UID'
Set should not rewrite a write once UID (Failed at
D:/Projects/tf-m6/trusted-firmware-m/armclang/lib/ext/tfm_test_repo-src/test/suites/its/its_tests_common.c:138)
TEST: TFM_S_ITS_TEST_1004 - FAILED!
> Executing 'TFM_S_ITS_TEST_1005'
Description: 'Get interface with valid data'
Set should not fail (Failed at
D:/Projects/tf-m6/trusted-firmware-m/armclang/lib/ext/tfm_test_repo-src/test/suites/its/its_tests_common.c:186)
TEST: TFM_S_ITS_TEST_1005 - FAILED!
> Executing 'TFM_S_ITS_TEST_1006'
Description: 'Get interface with zero data length'
Set should not fail (Failed at
D:/Projects/tf-m6/trusted-firmware-m/armclang/lib/ext/tfm_test_repo-src/test/suites/its/its_tests_common.c:293)
TEST: TFM_S_ITS_TEST_1006 - FAILED!
...
(lots more failed tests)
...
*** Non-secure test suites summary ***
Test suite 'PSA protected storage NS interface tests
(TFM_NS_PS_TEST_1XXX)' has PASSED
Test suite 'PSA internal trusted storage NS interface tests
(TFM_NS_ITS_TEST_1XXX)' has FAILED
Test suite 'Crypto non-secure interface test (TFM_NS_CRYPTO_TEST_1XXX)'
has FAILED
Test suite 'Platform Service Non-Secure interface
tests(TFM_NS_PLATFORM_TEST_1XXX)' has PASSED
Test suite 'Initial Attestation Service non-secure interface
tests(TFM_NS_ATTEST_TEST_1XXX)' has PASSED
Test suite 'QCBOR regression test(TFM_NS_QCBOR_TEST_1XXX)' has PASSED
Test suite 'T_COSE regression test(TFM_NS_T_COSE_TEST_1XXX)' has PASSED
Test suite 'PSA firmware update NS interface tests
(TFM_NS_FWU_TEST_1xxx)' has PASSED
Test suite 'Core non-secure positive tests (TFM_NS_CORE_TEST_1XXX)' has
PASSED
Test suite 'IPC non-secure interface test (TFM_NS_IPC_TEST_1XXX)' has PASSED
Test suite 'TFM IRQ Test (TFM_IRQ_TEST_1xxx)' has PASSED
*** End of Non-secure test suites ***
--
*Thomas Törnblom*, /Product Engineer/
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com Website: www.iar.com <http://www.iar.com>
Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>
Hello,
This platform is tested for profile medium and low (-DTFM_PROFILE=profile_small or -DTFM_PROFILE=profile_medium). I just checked on master with medium profile and GNUARM.
The default config takes a crypto config with its associated crypto tests that leads to overlap in flash area. (This device has 512Kbytes Flash)
Best Regards
ST Restricted
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Bøe, Sebastian via TF-M
Sent: mercredi 22 décembre 2021 13:40
To: tf-m(a)lists.trustedfirmware.org
Subject: [TF-M] nucleo_l552ze_q platform does not build since TF-M 1.5
Hi,
I am observing that the nucleo_l552ze_q platform is producing hex files that overlap
since the 1.5 release. Tested on master and 1.5.
Is there an STM maintainer that could look into this?
Steps to reproduce:
rm -rf cmake_build && cmake -S . -B cmake_build -DTFM_PLATFORM=stm/nucleo_l552ze_q -DTFM_TOOLCHAIN_FILE=toolchain_GNUARM.cmake -DCMAKE_BUILD_TYPE=MinSizeRel -DTEST_S=ON -DTEST_NS=ON && make -C cmake_build install && /usr/bin/python3.8 /home/sebo/ncs/zephyr/scripts/mergehex.py -o merged.hex $(find cmake_build -name "*.hex")
"/usr/bin/python3.8 /home/sebo/ncs/zephyr/scripts/mergehex.py" must be replaced
with the preferred hex file merging tool.
output:
Traceback (most recent call last):
File "/home/sebo/ncs/zephyr/scripts/mergehex.py", line 28, in merge_hex_files
ih.merge(to_merge, overlap=overlap)
File "/home/sebo/.local/lib/python3.8/site-packages/intelhex/__init__.py", line 875, in merge
raise AddressOverlapError(
intelhex.AddressOverlapError: Data overlapped at address 0xC014400
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
File "/home/sebo/ncs/zephyr/scripts/mergehex.py", line 56, in <module>
main()
File "/home/sebo/ncs/zephyr/scripts/mergehex.py", line 52, in main
merge_hex_files(args.output, args.input_files, args.overlap)
File "/home/sebo/ncs/zephyr/scripts/mergehex.py", line 30, in merge_hex_files
raise AddressOverlapError("{} has merge issues".format(hex_file_path))
intelhex.AddressOverlapError: cmake_build/install/outputs/STM/NUCLEO_L552ZE_Q/tfm_s.hex has merge issues
PS: Depending on the revision tested, it might be necessary to also apply this patch:
modified platform/ext/target/stm/common/stm32l5xx/CMakeLists.txt
@@ -90,7 +90,7 @@ target_sources(platform_s
${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32l5xx_hal_gtzc.c
${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_isolation_mpu_v8m.c
${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_nvic.c
- $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/secure/tfm_platform_system>
+ $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/secure/tfm_platform_system.c>
${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32l5xx_hal_rng.c
${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32l5xx_hal_rng_ex.c
PUBLIC
Hi,
I am observing that the nucleo_l552ze_q platform is producing hex files that overlap
since the 1.5 release. Tested on master and 1.5.
Is there an STM maintainer that could look into this?
Steps to reproduce:
rm -rf cmake_build && cmake -S . -B cmake_build -DTFM_PLATFORM=stm/nucleo_l552ze_q -DTFM_TOOLCHAIN_FILE=toolchain_GNUARM.cmake -DCMAKE_BUILD_TYPE=MinSizeRel -DTEST_S=ON -DTEST_NS=ON && make -C cmake_build install && /usr/bin/python3.8 /home/sebo/ncs/zephyr/scripts/mergehex.py -o merged.hex $(find cmake_build -name "*.hex")
"/usr/bin/python3.8 /home/sebo/ncs/zephyr/scripts/mergehex.py" must be replaced
with the preferred hex file merging tool.
output:
Traceback (most recent call last):
File "/home/sebo/ncs/zephyr/scripts/mergehex.py", line 28, in merge_hex_files
ih.merge(to_merge, overlap=overlap)
File "/home/sebo/.local/lib/python3.8/site-packages/intelhex/__init__.py", line 875, in merge
raise AddressOverlapError(
intelhex.AddressOverlapError: Data overlapped at address 0xC014400
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
File "/home/sebo/ncs/zephyr/scripts/mergehex.py", line 56, in <module>
main()
File "/home/sebo/ncs/zephyr/scripts/mergehex.py", line 52, in main
merge_hex_files(args.output, args.input_files, args.overlap)
File "/home/sebo/ncs/zephyr/scripts/mergehex.py", line 30, in merge_hex_files
raise AddressOverlapError("{} has merge issues".format(hex_file_path))
intelhex.AddressOverlapError: cmake_build/install/outputs/STM/NUCLEO_L552ZE_Q/tfm_s.hex has merge issues
PS: Depending on the revision tested, it might be necessary to also apply this patch:
modified platform/ext/target/stm/common/stm32l5xx/CMakeLists.txt
@@ -90,7 +90,7 @@ target_sources(platform_s
${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32l5xx_hal_gtzc.c
${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_isolation_mpu_v8m.c
${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_nvic.c
- $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/secure/tfm_platform_system>
+ $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/secure/tfm_platform_system.c>
${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32l5xx_hal_rng.c
${CMAKE_CURRENT_SOURCE_DIR}/hal/Src/stm32l5xx_hal_rng_ex.c
PUBLIC
Hi,
Currently, in the compiler link script, the CMSE VENEER section is placed at a fixed address which is at the end of tfm code. See code for armclang<https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/e…> and gnu arm<https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/e…>.
Placing the veneers at the fixed address has the benefit that the when the secure image updates, the veneer symbols remain unchanged. So, the nonsecure image does not have to be updated together.
The problem is that the size of tfm_s.bin is always the same in different TF-M build configurations(debug mode, release mode, profile small, profile large and so on). So, there can be large empty space between the end of tfm code and the veneer section.
As we discussed on today's tech forum meeting, I propose to move the LR_VENEER from the end of tfm code to right after the secure vector table. In this way, the space between the tfm code and the veneers section is eliminated. Also, the supported number of interrupts for each platform is fixed. So, the size of the vector table is fixed for each platform. So, the start address of veneer section is still fixed for each platform. The size of tfm_s.bin is reduced significantly after this change. Take the AN521 platform for example, the size of tfm_s.bin has a 70 percent reduction.
The link script change for armclang<https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12620/6/plat…> and gnu arm<https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12620/6/plat…> in this patch<https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12620/> can help me demonstrating my proposal. I am not hurry asking for review and merge this patch. As it impacts all the platforms, I want to get confirmed that all platforms which are using the common link script are happy with this proposal.
Any comments or especially concerns on this proposal?
Thanks,
Regards,
Sherry Zhang
Hi,
Wondering if anybody can throw some light on any ongoing efforts on power management on a system with TFM (deep sleep, etc).
thanks
Suresh Marisetty
Infineon Semiconductor Corporation
CYSC CSS ICW SW SSE
Mobile: +5103863997
Suresh.Marisetty(a)infineon.com<mailto:Suresh.Marisetty@infineon.com>
I'm working on the IAR part of this and I'm having a problem with the
following test in isolation level 3:
---
Running Test Suite TFM IRQ Test (TFM_IRQ_TEST_1xxx)...
> Executing 'TFM_NS_IRQ_TEST_SLIH_1001'
Description: 'SLIH HANDLING Case 1'
---
If I run the test at full speed, it will run into a MemManage fault
while if I single step through the entire test it will pass.
Is there a race condition somewhere in there?
If I disable the SLIH tests it succeeds.
The exception happens when dereferencing "dev" in this function:
bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev)
{
return dev->data->is_initialized;
}
dev is 0x30002440 at the time.
I've been trying to figure out what part of the memory protection system
it is that is causing the exception.
DACCVIOL is set and MMFAR shows the faulting address.
Ideas?
The build line:
cmake -GNinja -S .. -B . -DTFM_PLATFORM=arm/musca_b1/sse_200
"-DTFM_TOOLCHAIN_FILE=..\toolchain_IARARM.cmake" -DTEST_NS=ON
-DTEST_S=ON -DCMAKE_BUILD_TYPE=Debug -DBL2=ON -DTFM_ISOLATION_LEVEL=3
-DTEST_NS_SLIH_IRQ=ON -DTEST_NS_QCBOR=OFF
Notice that this build runs into a linker bug in the IAR toolchain and I
have a non-released fixed version I'm using, in case anyone is
attempting to replicate the issue.
Cheers,
Thomas
Den 2021-12-17 kl. 11:30, skrev TrustedFirmware Code Review (Code Review):
>
> Attention is currently required from: Kevin Peng, Ken Liu, David Hu,
> Chris Brand, Anton Komlev, Thomas Törnblom.
>
> "Build Successful
>
> http://ci.trustedfirmware.org/job/tf-m-static/3226/display/redirect :
> SUCCESS"
>
> Patch set 16:Verified +1
>
> View Change
> <https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12620>
>
> To view, visit change 12620
> <https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12620>.
> To unsubscribe, or for help writing mail filters, visit settings
> <https://review.trustedfirmware.org/settings>.
>
> Gerrit-Project: TF-M/trusted-firmware-m
> Gerrit-Branch: master
> Gerrit-Change-Id: I0084aef576d90af45513c7eaae58ba6c6dbbddab
> Gerrit-Change-Number: 12620
> Gerrit-PatchSet: 16
> Gerrit-Owner: sherryzhang <sherry.zhang2(a)arm.com>
> Gerrit-Reviewer: Anton Komlev <Anton.Komlev(a)arm.com>
> Gerrit-Reviewer: David Hu <david.hu(a)arm.com>
> Gerrit-Reviewer: Ken Liu <ken.liu(a)arm.com>
> Gerrit-Reviewer: Sebastian Bøe <Sebastian.boe(a)nordicsemi.no>
> Gerrit-Reviewer: Thomas Törnblom <thomas.tornblom(a)iar.com>
> Gerrit-Reviewer: TrustedFirmware Code Review
> Gerrit-Reviewer: sherryzhang <sherry.zhang2(a)arm.com>
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> Gerrit-Attention: Kevin Peng <kevin.peng(a)arm.com>
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> Gerrit-Attention: David Hu <david.hu(a)arm.com>
> Gerrit-Attention: Chris Brand <chris.brand(a)cypress.com>
> Gerrit-Attention: Anton Komlev <Anton.Komlev(a)arm.com>
> Gerrit-Attention: Thomas Törnblom <thomas.tornblom(a)iar.com>
> Gerrit-Comment-Date: Fri, 17 Dec 2021 10:30:20 +0000
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> Gerrit-MessageType: comment
--
*Thomas Törnblom*, /Product Engineer/
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com Website: www.iar.com <http://www.iar.com>
Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>
Hi everyone,
I’m wondering if there is any existing effort on enabling X.509 CSR generation and certificate verification inside TF-M? Our project has some custom secure partitions which need to generate the CSR and verify the issued certificates by themselves. The current TF-M implementation hasn’t added X.509’s support. So, I’m wondering if any open source project already does that which we can leverage?
Regards,
Jun Li
Intel Corporation, CA
Hello,
In the light of the end of the year celebrations expecting not many joiners on Dec 23, specially for US time zone, hence
let's cancel the forum at the next week.
Thanks and wish you the great holidays,
Anton
I recently switched to a new MBP that ships with OS X Monterey, and on both
12.0 and 12.1 (released this week) git clone seems to be broken when you're
using HTTP rather than SSH:
digital envelope routines:CRYPTO_internal:bad key length
In order to clone TF-M, I had to make the following changes.
1. Add these details to $HOME/.ssh/config (microbuilder being my github
username, associated with my TF-M account):
Host trustedfirmware.org
User microbuilder
Hostname review.trustedfirmware.org
Port 29418
IdentityFile ~/.ssh/id_rsa
IdentitiesOnly yes
2. Then try to clone with:
$ git clone trustedfirmware.org:/TF-M/trusted-firmware-m.git
This fails, however, since it tries to clone tf-m-tests.git, so:
3. Edit lib/ext/tf-m-tests/fetch_repo.cmake, changing:
FetchContent_Declare(tfm_test_repo
GIT_REPOSITORY trustedfirmware.org:TF-M/tf-m-tests.git
# GIT_REPOSITORY https://git.trustedfirmware.org/TF-M/tf-m-tests.git
GIT_TAG ${TFM_TEST_REPO_VERSION}
GIT_PROGRESS TRUE
)
This let me at least clone TF-M until the issues with HTTP-based cloning
are fixed.
Hope this is useful to someone else working on OS X natively.
Kevin
Hi,
The next Technical Forum is planned on Thursday, Dec 9, 7:00-8:00 UTC (Asia time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi,
for PSA Certification level 2 a log of significant security events is required. Which I assume
should be done with the Audit log service.
But the Audit log service does not support IPC mode.
Should PSA Certification level 2 be done with IPC mode or with library mode?
Hello,
TF-M project released v1.5.0 in release/v1.5.x<https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/log/?h=release/…> branch and tagged as TF-Mv1.5.0.
In the following days the changes from the release branch will be integrated with the main branch.
Please take a look into the release notes for the new features and changes:
https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/docs/relea…
The HTML version will be available after the main branch update.
New major features are:
* MCUboot updated to v1.8.0.
* Thread mode SPM.
* Add Non-secure Client Extension (NSCE) for non-secure client ID management support.
* Secure Function model support in framework.
* Support Memory-mapped IOVECs.
* Decouple documentation and binary builds.
* Manifest tool skips disabled Secure Partitions.
* Provisioning and OTP are supported.
* PSA Protected Storage, Internal Trusted Storage, Initial Attestation services are converted to Stateless services.
* Support out-of-tree build of Secure Partitions.
* Support out-of-tree build of platform specific test suites.
* Introduce platform binding HAL.
* ITS enhancement for harden ITS module against invalid data in Flash.
* Support to select/deselect single or multiple TF-M regression test cases.
* Decouple regression test flag configuration from TF-M.
* New platforms added.
Thank you, everyone who contributed to this milestone.
Anton Komlev
Hello,
Having no items to discuss - let's cancel the forum today.
Have a happy Thanksgiving day and enjoy your turkey if you celebrate it.
Thanks,
Anton
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Anton Komlev via TF-M
Sent: Monday, November 22, 2021 12:04 PM
To: tf-m(a)lists.trustedfirmware.org
Cc: nd <nd(a)arm.com>
Subject: [TF-M] Technical Forum call - Nov-25
Hi,
The next Technical Forum is planned on Thursday, Nov 25, 15:00-16:00 UTC (US time zone).
This is Thanksgiving day and public holiday in US so we might want to cancel the forum expecting fewer participants unless we have a good topic to discuss.
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi,
The next Technical Forum is planned on Thursday, Nov 25, 15:00-16:00 UTC (US time zone).
This is Thanksgiving day and public holiday in US so we might want to cancel the forum expecting fewer participants unless we have a good topic to discuss.
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi Thomas,
The tf-m-tests fix is under review and has not been merged yet. Therefore that commit ID is not available in tf-m-tests.
I'd suggest to do following to test the fix:
* Cherry pick https://review.trustedfirmware.org/c/TF-M/tf-m-tests/+/12563 to your local tf-m-tests repo
* Cherry pick https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12564 to your local trusted-firmware-m repo
* Add `-DTFM_TEST_REPO_PATH=<local tf-m-tests folder>` in the build command.
After the fix is merged, the commit will be available when fetching the tf-m-tests repo.
Best regards,
Hu Ziji
________________________________
From: Thomas Törnblom <thomas.tornblom(a)iar.com>
Sent: Thursday, November 18, 2021 8:10 PM
To: David Hu <David.Hu(a)arm.com>; David Wang <David.Wang(a)arm.com>; Feder Liang <Feder.Liang(a)arm.com>
Cc: nd <nd(a)arm.com>
Subject: Re: [TF-M] d4dbaa93, "Add FPU support for gnu arm embedded toolchain" causing build errors
I'm getting another error after cherry picking these:
PS D:\Projects\trusted-firmware-m\iar> cmake -GNinja -S .. -B . -DTFM_PLATFORM=arm/musca_s1 "-DTFM_TOOLCHAIN_FILE=..\toolchain_IARARM.cmake" -DTEST_NS=ON -DTEST_S=ON -DCMAKE_BUILD_TYPE=Debug -DBL2=ON -DTEST_NS_QCBOR=OFF
-- Populating tfm_test_repo
-- Configuring done
-- Generating done
-- Build files have been written to: D:/Projects/trusted-firmware-m/iar/lib/ext/tfm_test_repo-subbuild
[1/9] Creating directories for 'tfm_test_repo-populate'
[1/9] Performing download step (git clone) for 'tfm_test_repo-populate'
Cloning into 'tfm_test_repo-src'...
remote: Enumerating objects: 1094, done.
remote: Counting objects: 100% (1094/1094), done.
remote: Compressing objects: 100% (613/613), done.
remote: Total 2057 (delta 913), reused 511 (delta 481), pack-reused 963
Receiving objects: 100% (2057/2057), 2.05 MiB | 8.43 MiB/s, done.
Resolving deltas: 100% (1371/1371), done.
fatal: invalid reference: 14ca288
CMake Error at tfm_test_repo-subbuild/tfm_test_repo-populate-prefix/tmp/tfm_test_repo-populate-gitclone.cmake:40 (message):
Failed to checkout tag: '14ca288'
FAILED: tfm_test_repo-populate-prefix/src/tfm_test_repo-populate-stamp/tfm_test_repo-populate-download
cmd.exe /C "cd /D D:\Projects\trusted-firmware-m\iar\lib\ext && "C:\Program Files\CMake\bin\cmake.exe" -P D:/Projects/trusted-firmware-m/iar/lib/ext/tfm_test_repo-subbuild/tfm_test_repo-populate-prefix/tmp/tfm_test_repo-populate-gitclone.cmake && "C:\Program Files\CMake\bin\cmake.exe" -E touch D:/Projects/trusted-firmware-m/iar/lib/ext/tfm_test_repo-subbuild/tfm_test_repo-populate-prefix/src/tfm_test_repo-populate-stamp/tfm_test_repo-populate-download"
ninja: build stopped: subcommand failed.
CMake Error at C:/Program Files/CMake/share/cmake-3.20/Modules/FetchContent.cmake:1012 (message):
Build step for tfm_test_repo failed: 1
Call Stack (most recent call first):
C:/Program Files/CMake/share/cmake-3.20/Modules/FetchContent.cmake:1141:EVAL:2 (__FetchContent_directPopulate)
C:/Program Files/CMake/share/cmake-3.20/Modules/FetchContent.cmake:1141 (cmake_language)
lib/ext/tf-m-tests/fetch_repo.cmake:27 (FetchContent_Populate)
lib/ext/tf-m-tests/tf-m-tests.cmake:56 (include)
config/set_config.cmake:68 (include)
CMakeLists.txt:42 (include)
Den 2021-11-18 kl. 13:00, skrev David Hu:
Hi Thomas,
Sorry for the failure and the trouble.
The build logic of QCBOR NS test was adjusted to fit FP feature but the logic has defect when QCBOR NS test = OFF.
Please cherry pick the following 2 patches and have a try:
https://review.trustedfirmware.org/c/TF-M/tf-m-tests/+/12563https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12564
The fix will be port back to master branch when release completes.
Best regards,
Hu Ziji
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org><mailto:tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M
Sent: Thursday, November 18, 2021 6:57 PM
To: David Wang <David.Wang(a)arm.com><mailto:David.Wang@arm.com>; Feder Liang <Feder.Liang(a)arm.com><mailto:Feder.Liang@arm.com>
Cc: nd <nd(a)arm.com><mailto:nd@arm.com>; tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Subject: Re: [TF-M] d4dbaa93, "Add FPU support for gnu arm embedded toolchain" causing build errors
Oh, and it fails the same on Windows and linux, as well as ARMCLANG and IARARM.
/Thomas
Den 2021-11-18 kl. 11:56, skrev Thomas Törnblom:
commit fd88f7fbde4d23720c3c9be7350e628df51ef964 (HEAD -> master, tag: TF-Mv1.5.0-RC1, origin/master, origin/HEAD, list)
Den 2021-11-18 kl. 11:27, skrev David Wang:
Hi Thomas,
Could you share the SHA of your branch HEAD?
Or you can try to fetch the latest tag and code.
Regards,
David Wang
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org><mailto:tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M
Sent: Thursday, November 18, 2021 6:10 PM
To: Feder Liang <Feder.Liang(a)arm.com><mailto:Feder.Liang@arm.com>
Cc: nd <nd(a)arm.com><mailto:nd@arm.com>; tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Subject: Re: [TF-M] d4dbaa93, "Add FPU support for gnu arm embedded toolchain" causing build errors
Nope,
I was using "master", which was 1.5.0 RC1, both fails.
/Thomas
Den 2021-11-18 kl. 10:56, skrev Feder Liang:
Hi, Thomas
It seems TF-M and Test repo is not synced.
Could you help a try on latest TF-M master branch or tag: TF-Mv1.5.0-RC1?
Best Regards
Feder
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org><mailto:tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M
Sent: Thursday, November 18, 2021 5:42 PM
To: tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Subject: [TF-M] d4dbaa93, "Add FPU support for gnu arm embedded toolchain" causing build errors
Looks like this patch is causing build errors, at least for Musca S1.
cmake line:
cmake -GNinja -S .. -B . -DTFM_PLATFORM=arm/musca_s1 "-DTFM_TOOLCHAIN_FILE=..\toolchain_ARMCLANG.cmake" -DTEST_NS=ON -DTEST_S=ON -DCMAKE_BUILD_TYPE=Debug -DBL2=ON -DTEST_NS_QCBOR=OFF
[1233/1238] Linking C executable bin\tfm_ns.axf
FAILED: bin/tfm_ns.axf
cmd.exe /C "cd . && D:\apps\Keil_v5\ARM\ARMCLANG\bin\armlink.exe --cpu=cortex-m33 --info=summarysizes,sizes,totals,unused,veneers --strict --symbols --xref --diag_suppress=6312 --diag_suppress=6314 --diag_suppress=6304 --diag_suppress=6329 --fpu=softvfp --map --scatter=D:/Projects/trusted-firmware-m/armclang/platform/target/CMakeFiles/tfm_ns_scatter.dir/./Device/Source/armclang/musca_ns.o platform\libplatform_ns.a app\libtfm_ns_integration_test.a app\libtfm_api_ns.a ns_log\libtfm_ns_log.a test\suites\core\libtfm_test_suite_core_ns.a app\libtfm_ns_integration_test.a test\suites\core\libtfm_test_suite_core_ns.a test\suites\attestation\libtfm_test_suite_attestation_ns.a test\suites\crypto\libtfm_test_suite_crypto_ns.a test\suites\qcbor\libtfm_test_suite_qcbor_ns.a -ltfm_qcbor_test test\suites\ps\libtfm_test_suite_ps_ns.a test\suites\its\libtfm_test_suite_its_ns.a test\suites\t_cose\libtfm_test_suite_t_cose_ns.a test\suites\t_cose\libtfm_t_cose_test.a test\suites\t_cose\libtfm_t_cose_ns.a test\suites\qcbor\libtfm_qcbor_ns.a test\suites\platform\libtfm_test_suite_platform_ns.a test\suites\ipc\libtfm_test_suite_ipc_ns.a lib\ext\tfm_test_repo-src\CMSIS\RTOS2\RTX\Library\ARM\RTX_V8MMN.lib app\libtfm_api_ns.a secure_fw\libtfm_s_veneers.a ns_log\libtfm_ns_log.a platform\libplatform_ns.a app\CMakeFiles\tfm_ns.dir\main_ns.o app\CMakeFiles\tfm_ns.dir\__\__\platform\ext\target\arm\musca_s1\Device\Source\armclang\startup_cmsdk_musca_ns.o app\CMakeFiles\tfm_ns.dir\__\ns_interface\ns_client_ext\tz_shim_layer.o app\CMakeFiles\tfm_ns.dir\__\CMSIS\RTOS2\RTX\Config\RTX_Config.o app\CMakeFiles\tfm_ns.dir\__\CMSIS\RTOS2\RTX\Source\rtx_lib.o app\CMakeFiles\tfm_ns.dir\os_wrapper_cmsis_rtos_v2.o -o bin\tfm_ns.axf --list=bin\tfm_ns.axf.map && cd ."
Fatal error: L3900U: Unrecognized option '-ltfm_qcbor_test'.
Finished: 0 information, 0 warning, 0 error and 1 fatal error messages.
ninja: build stopped: subcommand failed.
--
Thomas Törnblom, Product Engineer
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com<mailto:thomas.tornblom@iar.com> Website: www.iar.com<http://www.iar.com>
Twitter: www.twitter.com/iarsystems<http://www.twitter.com/iarsystems>
--
Thomas Törnblom, Product Engineer
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com<mailto:thomas.tornblom@iar.com> Website: www.iar.com<http://www.iar.com>
Twitter: www.twitter.com/iarsystems<http://www.twitter.com/iarsystems>
--
Thomas Törnblom, Product Engineer
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com<mailto:thomas.tornblom@iar.com> Website: www.iar.com<http://www.iar.com>
Twitter: www.twitter.com/iarsystems<http://www.twitter.com/iarsystems>
--
Thomas Törnblom, Product Engineer
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com<mailto:thomas.tornblom@iar.com> Website: www.iar.com<http://www.iar.com>
Twitter: www.twitter.com/iarsystems<http://www.twitter.com/iarsystems>
--
Thomas Törnblom, Product Engineer
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com<mailto:thomas.tornblom@iar.com> Website: www.iar.com<http://www.iar.com>
Twitter: www.twitter.com/iarsystems<http://www.twitter.com/iarsystems>
The mailing list was lost.
From: David Hu
Sent: Thursday, November 18, 2021 8:00 PM
To: Thomas Törnblom <thomas.tornblom(a)iar.com>; David Wang <David.Wang(a)arm.com>; Feder Liang <Feder.Liang(a)arm.com>
Cc: nd <nd(a)arm.com>
Subject: RE: [TF-M] d4dbaa93, "Add FPU support for gnu arm embedded toolchain" causing build errors
Hi Thomas,
Sorry for the failure and the trouble.
The build logic of QCBOR NS test was adjusted to fit FP feature but the logic has defect when QCBOR NS test = OFF.
Please cherry pick the following 2 patches and have a try:
https://review.trustedfirmware.org/c/TF-M/tf-m-tests/+/12563https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12564
The fix will be port back to master branch when release completes.
Best regards,
Hu Ziji
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org<mailto:tf-m-bounces@lists.trustedfirmware.org>> On Behalf Of Thomas Törnblom via TF-M
Sent: Thursday, November 18, 2021 6:57 PM
To: David Wang <David.Wang(a)arm.com<mailto:David.Wang@arm.com>>; Feder Liang <Feder.Liang(a)arm.com<mailto:Feder.Liang@arm.com>>
Cc: nd <nd(a)arm.com<mailto:nd@arm.com>>; tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Subject: Re: [TF-M] d4dbaa93, "Add FPU support for gnu arm embedded toolchain" causing build errors
Oh, and it fails the same on Windows and linux, as well as ARMCLANG and IARARM.
/Thomas
Den 2021-11-18 kl. 11:56, skrev Thomas Törnblom:
commit fd88f7fbde4d23720c3c9be7350e628df51ef964 (HEAD -> master, tag: TF-Mv1.5.0-RC1, origin/master, origin/HEAD, list)
Den 2021-11-18 kl. 11:27, skrev David Wang:
Hi Thomas,
Could you share the SHA of your branch HEAD?
Or you can try to fetch the latest tag and code.
Regards,
David Wang
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org><mailto:tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M
Sent: Thursday, November 18, 2021 6:10 PM
To: Feder Liang <Feder.Liang(a)arm.com><mailto:Feder.Liang@arm.com>
Cc: nd <nd(a)arm.com><mailto:nd@arm.com>; tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Subject: Re: [TF-M] d4dbaa93, "Add FPU support for gnu arm embedded toolchain" causing build errors
Nope,
I was using "master", which was 1.5.0 RC1, both fails.
/Thomas
Den 2021-11-18 kl. 10:56, skrev Feder Liang:
Hi, Thomas
It seems TF-M and Test repo is not synced.
Could you help a try on latest TF-M master branch or tag: TF-Mv1.5.0-RC1?
Best Regards
Feder
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org><mailto:tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M
Sent: Thursday, November 18, 2021 5:42 PM
To: tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org>
Subject: [TF-M] d4dbaa93, "Add FPU support for gnu arm embedded toolchain" causing build errors
Looks like this patch is causing build errors, at least for Musca S1.
cmake line:
cmake -GNinja -S .. -B . -DTFM_PLATFORM=arm/musca_s1 "-DTFM_TOOLCHAIN_FILE=..\toolchain_ARMCLANG.cmake" -DTEST_NS=ON -DTEST_S=ON -DCMAKE_BUILD_TYPE=Debug -DBL2=ON -DTEST_NS_QCBOR=OFF
[1233/1238] Linking C executable bin\tfm_ns.axf
FAILED: bin/tfm_ns.axf
cmd.exe /C "cd . && D:\apps\Keil_v5\ARM\ARMCLANG\bin\armlink.exe --cpu=cortex-m33 --info=summarysizes,sizes,totals,unused,veneers --strict --symbols --xref --diag_suppress=6312 --diag_suppress=6314 --diag_suppress=6304 --diag_suppress=6329 --fpu=softvfp --map --scatter=D:/Projects/trusted-firmware-m/armclang/platform/target/CMakeFiles/tfm_ns_scatter.dir/./Device/Source/armclang/musca_ns.o platform\libplatform_ns.a app\libtfm_ns_integration_test.a app\libtfm_api_ns.a ns_log\libtfm_ns_log.a test\suites\core\libtfm_test_suite_core_ns.a app\libtfm_ns_integration_test.a test\suites\core\libtfm_test_suite_core_ns.a test\suites\attestation\libtfm_test_suite_attestation_ns.a test\suites\crypto\libtfm_test_suite_crypto_ns.a test\suites\qcbor\libtfm_test_suite_qcbor_ns.a -ltfm_qcbor_test test\suites\ps\libtfm_test_suite_ps_ns.a test\suites\its\libtfm_test_suite_its_ns.a test\suites\t_cose\libtfm_test_suite_t_cose_ns.a test\suites\t_cose\libtfm_t_cose_test.a test\suites\t_cose\libtfm_t_cose_ns.a test\suites\qcbor\libtfm_qcbor_ns.a test\suites\platform\libtfm_test_suite_platform_ns.a test\suites\ipc\libtfm_test_suite_ipc_ns.a lib\ext\tfm_test_repo-src\CMSIS\RTOS2\RTX\Library\ARM\RTX_V8MMN.lib app\libtfm_api_ns.a secure_fw\libtfm_s_veneers.a ns_log\libtfm_ns_log.a platform\libplatform_ns.a app\CMakeFiles\tfm_ns.dir\main_ns.o app\CMakeFiles\tfm_ns.dir\__\__\platform\ext\target\arm\musca_s1\Device\Source\armclang\startup_cmsdk_musca_ns.o app\CMakeFiles\tfm_ns.dir\__\ns_interface\ns_client_ext\tz_shim_layer.o app\CMakeFiles\tfm_ns.dir\__\CMSIS\RTOS2\RTX\Config\RTX_Config.o app\CMakeFiles\tfm_ns.dir\__\CMSIS\RTOS2\RTX\Source\rtx_lib.o app\CMakeFiles\tfm_ns.dir\os_wrapper_cmsis_rtos_v2.o -o bin\tfm_ns.axf --list=bin\tfm_ns.axf.map && cd ."
Fatal error: L3900U: Unrecognized option '-ltfm_qcbor_test'.
Finished: 0 information, 0 warning, 0 error and 1 fatal error messages.
ninja: build stopped: subcommand failed.
--
Thomas Törnblom, Product Engineer
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com<mailto:thomas.tornblom@iar.com> Website: www.iar.com<http://www.iar.com>
Twitter: www.twitter.com/iarsystems<http://www.twitter.com/iarsystems>
--
Thomas Törnblom, Product Engineer
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com<mailto:thomas.tornblom@iar.com> Website: www.iar.com<http://www.iar.com>
Twitter: www.twitter.com/iarsystems<http://www.twitter.com/iarsystems>
--
Thomas Törnblom, Product Engineer
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com<mailto:thomas.tornblom@iar.com> Website: www.iar.com<http://www.iar.com>
Twitter: www.twitter.com/iarsystems<http://www.twitter.com/iarsystems>
--
Thomas Törnblom, Product Engineer
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com<mailto:thomas.tornblom@iar.com> Website: www.iar.com<http://www.iar.com>
Twitter: www.twitter.com/iarsystems<http://www.twitter.com/iarsystems>
Hi,
I'm sorry to inform you that ITS/PS access flash on MUSCA_B1 could not be covered on Open CI for the time being.
Because the flash on MUSCA_B1 board in Open CI is broken, we temporarily use RAM_FS as workaround.
This issue will be fixed ASAP. We'll keep following and inform you with further updates.
Sorry for any inconvenience!
BR,
Xinyu
Hello,
To include all planned changes we need more time to review the patches so the feature freeze is postponed to the beginning of the next week when release branch will be created. This gives all a few more days for reviews and last moment changes.
The intention is to keep the final date unchanged.
Best regards,
Anton
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Anton Komlev via TF-M
Sent: Thursday, November 11, 2021 8:33 AM
To: tf-m(a)lists.trustedfirmware.org
Cc: nd <nd(a)arm.com>
Subject: [TF-M] TF-M release v1.5.0 will start on Nov 15
Hello,
Following the updated release strategy, presented on the tech forum today I plan to create the release branch on Nov 13, and freeze project features at that moment. Please review and merge all patches intended for v1.5.0 by the end of this week.
Normal development can continue on the main branch without any restriction.
Thanks,
Anton
Build command is:
cmake -S . -B output -G"Unix Makefiles" -DTFM_PLATFORM=cypress/psoc64 -DTFM_TOOLCHAIN_FILE=toolchain_GNUARM.cmake -DTEST_NS_MULTI_CORE=ON -DTFM_ISOLATION_LEVEL=1
The result is a hang at this point:
> Executing 'MULTI_CLIENT_CALL_HEAVY_TEST'
Description: 'Multiple outstanding NS PSA client calls heavyweight test'
Totally 5 threads for test start
Each thread run 0x20 rounds tests
Some experimentation shows that:
It happens with both gcc and armclang (unable to test IAR).
It doesn't always happen, but does seem to hang more often than it succeeds.
It doesn't happen with TFM_ISOLATION_LEVEL=2.
It looks like this test was passing consistently before 5e68b11764673ee32bae0de8ecf3cde45cc55ea1, so I guess this is another scheduling issue. There's not a lot of code that differs with TFM_LVL, so I wonder if there's a race condition that is always present but just doesn't happen to get hit at TFM_LVL=2...?
BTW, being able to build just the one test is extremely useful!
Chris Brand
Cypress Semiconductor (Canada), Inc.
Sr Prin Software Engr
CSCA CSS ICW SW PSW 1
Office: +1 778 234 0515
Chris.Brand(a)infineon.com<mailto:Chris.Brand@infineon.com>
Hi,
are there any known race conditions in IPC/PS that affect TF-M 1.4-ish?
More specifically TF-M revision a199c3047f320a2f82b9a0c27af5b50991184e0f,
which
is 38 commits prior to TF-Mv1.4.0-RC1.
I am observing that adding printfs, or otherwise changing the flash
alignment and therefore runtime of my code will affect whether the PS
reliability test suite passes or not.
More specifically, if it triggers a secure fault after x iterations of
2001, or y iterations of 2002, etc. depending on where I put my printfs or
otherwise affect the alignment of the code.
This is run on the nrf platform as a part of the nrf SDK.
Test Suite PS reliability tests (TFM_PS_TEST_2XXX)...
'repetitive sets and gets in/from an asset'
'repetitive sets, gets and removes'
It does not reproduce under GDB and I am unable to unwind the backtrace
from the secure fault handler. Any tips about recovering a backtrace from a
secure fault handler would also be appreciated.
#0 SecureFault_Handler ()
at
/home/sebo/ncs/modules/tee/tfm/trusted-firmware-m/secure_fw/spm/cmsis_psa/arch/tfm_arch_v8m_main.c:96
#1 0xffffffb4 in ?? ()
I have not been able to reproduce it in the latest upstream TF-M
release/revision, but that could just be because I haven't been able to hit
the race condition.
Sebastian Bøe
Hi,
I worked out a patch<https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/12025> to make the Manifest Tool (tfm_parse_manifest_list.py) aware of the Secure Partition status when building.
Currently, the tool generates everything and then the Build System picks up the files needed.
With the development of FF-M 1.1 feature, we need the tool to be aware of the Secure Partition enabled status to generate SPM configurations.
The patch make use of the feature of CMake command configure_file which substitutes variable values referenced as @VAR@ or ${VAR}.
It requires the "conditional" attributes in manifest lists to be surrounded by "@" for "${}".
Then when you disable some Partition for building, the tool will not generate anything for that Partition such as PID/SID and TF-M Partition load info.
So please out of tree Secure Partition manifest lists do the corresponding change to make the tool aware of that any Partitions are DISABLED.
The tool currently only takes conditional value "OFF" or "FALSE" as Partitions being disabled, all other values are treated as enabled.
This means if you do not make the change in the manifest list, the tool treats all the partitions as enabled always.
Best Regards,
Kevin
Hello,
Following the updated release strategy, presented on the tech forum today I plan to create the release branch on Nov 13, and freeze project features at that moment. Please review and merge all patches intended for v1.5.0 by the end of this week.
Normal development can continue on the main branch without any restriction.
Thanks,
Anton
Hi,
I'm trying to build Musca B1 SE (as part of my work to create a new ns_agent_mailbox partition), and it seems that it has been missed in some HAL API changes:
spm/libtfm_spm.a(backend_ipc.o): In function `ipc_system_run':
.../secure_fw/spm/ffm/backend_ipc.c:132: undefined reference to `tfm_hal_update_boundaries'
spm/libtfm_spm.a(spm_ipc.o): In function `tfm_spm_init':
.../secure_fw/spm/cmsis_psa/spm_ipc.c:643: undefined reference to `tfm_hal_bind_boundaries'
spm/libtfm_spm.a(spm_ipc.o): In function `do_schedule':
.../secure_fw/spm/cmsis_psa/spm_ipc.c:694: undefined reference to `tfm_hal_update_boundaries'
spm/libtfm_spm.a(static_load.o): In function `load_irqs_assuredly':
.../secure_fw/spm/cmsis_psa/static_load.c:195: undefined reference to `tfm_hal_irq_enable'
.../secure_fw/spm/cmsis_psa/static_load.c:198: undefined reference to `tfm_hal_irq_disable'
spm/libtfm_spm.a(psa_api.o): In function `tfm_spm_partition_psa_eoi':
.../secure_fw/spm/ffm/psa_api.c:830: undefined reference to `tfm_hal_irq_clear_pending'
.../secure_fw/spm/ffm/psa_api.c:831: undefined reference to `tfm_hal_irq_enable'
spm/libtfm_spm.a(psa_api.o): In function `tfm_spm_partition_irq_enable':
.../secure_fw/spm/ffm/psa_api.c:858: undefined reference to `tfm_hal_irq_enable'
spm/libtfm_spm.a(psa_api.o): In function `tfm_spm_partition_irq_disable':
.../secure_fw/spm/ffm/psa_api.c:876: undefined reference to `tfm_hal_irq_disable'
spm/libtfm_spm.a(tfm_core_svcalls_ipc.o): In function `tfm_flih_prepare_depriv_flih':
.../secure_fw/spm/cmsis_psa/tfm_core_svcalls_ipc.c:137: undefined reference to `tfm_hal_update_boundaries'
spm/libtfm_spm.a(tfm_core_svcalls_ipc.o): In function `tfm_flih_return_to_isr':
.../secure_fw/spm/cmsis_psa/tfm_core_svcalls_ipc.c:170: undefined reference to `tfm_hal_update_boundaries'
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Hi,
The next Technical Forum is planned on Thursday, Nov 11, 7:00-8:00 UTC (Asia time zone).
Please reply on this email with your proposals for agenda topics.
Recording and slides of previous meetings are here:
https://www.trustedfirmware.org/meetings/tf-m-technical-forum/
Best regards,
Anton
Hi guys,
I am trying to put tf-m running in the PSoC64 board. However, I have a
board that is slightly different from the one used by default in the tf-m.
(I have *CYB06447BZI-D54* and the default tf-m is prepared to
*CYS0644xxZI-S2D44).
*For what I saw, the main difference among them is in memory, *CYB06447BZI-D54
*has 1MB of flash and 256kB of RAM and *CYS0644xxZI-S2D44 *has 2MB of
Flash and 1MB of RAM.
So now I'm trying to make a small port from tf-m to *CYB06447BZI-D54. *
I changed the flash size in the flash_layout.h file to meet the
*CYB06447BZI-D54 *flash size, however, I am having some difficulties in
changing the RAM size. I am trying to change the RAM partitions size in
region_defs.h and the smpu definitions of that partitions in smpu_config.h,
but without much success.
My question are:
- Is possible to do the porting? Or does *CYB06447BZI-D54* not have
enough memory to run tf-m?
- If possible, what is I missing? Are more changes needed than I'm
making?
Best regards,
Cristiano Rodrigues
Hi,
I need to derive a new key from the HUK using HKDF, but are we able to
request key derivation with the HUK from the NS side, or would we need to
create a custom ARoT partittion for that?
The requirements are identical to what PS does here with HKDF -- no salt
and a fixed 'info' value, resulting in a key that is device-bound and can
be regenerated at startup with no storage requirements:
https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/desig…
(that API usage looks to be out of date, BTW, since "psa_open_key" now
takes two params).
I tried to do something similar from the NS side, modifying this code
https://github.com/zephyrproject-rtos/zephyr/blob/main/samples/tfm_integrat…
..., but get an error when trying to open the HUK with
"TFM_CRYPTO_KEY_ID_HUK".
That isn't surprising, but is there any alternative to generate keys from
the HUK without a custom ARoT service? The fact that no storage is required
when deriving from the HUK is significant.
Best regards,
Kevin
Hi all,
Does anyone know if using software random generator seeded with TRNG to provide random delays for Fault Injection Hardening library is correct from PSA Level 3 certification point of view?
The basic idea is to :
1. Use TRNG to provide seed for software random generator on fih_delay_init.
2. Use software random generator to implement fih_delay_random.
3. Periodically reseed software random generator with data from TRNG (optional).
Thanks,
Roman.
The current version breaks console output for the secure partition on
psoc64 with IAR or ARMCLANG. Appears to work with GNUARM.
It appears that this commit is the culprit:
fce78aef Platform: Duplicate the tfm_hal_platform_init
The console starts out good, then during tests only garbage is seen.
Linker script issues?
/Thomas
--
*Thomas Törnblom*, /Product Engineer/
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com Website: www.iar.com <http://www.iar.com>
Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>
While attempting to build for the musca_s1, with mcuboot, on Windows,
the build failed very late and brought up a Code Writer window on my screen.
I nailed it down to no "PYTHON_EXECUTABLE" being defined while
processing bl2/ext/mcuboot/CMakeLists.txt, which caused the build line
to just attempt to run wrapper.py, with no interpreter, and windows
brought up the appropriate tools to write python code.
Adding "-DPYTHON_EXECUTABLE=python" to the cmake line fixed that, but it
seems that this shouldn't be needed. The build tools should handle this, or?
There is a line:
#! /usr/bin/env python3
in wrapper.py, and I assume linux will handle this appropriately, but it
doesn't seem windows does.
Cheers,
Thomas
--
*Thomas Törnblom*, /Product Engineer/
IAR Systems AB
Box 23051, Strandbodgatan 1
SE-750 23 Uppsala, SWEDEN
Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01
E-mail: thomas.tornblom(a)iar.com Website: www.iar.com <http://www.iar.com>
Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>
Hi everyone,
I was trying to understand usage of TOTAL_ROM_SIZE and FLASH_TOTAL_SIZE from musca_b1/sse_200/partitions/flash_layout.h file.
I haven't found any usage of these definitions.
Does anyone know what is the reason to have them defined?
Regards,
Bohdan Hunko
Cypress Semiconductor Ukraine
Engineer
CSUKR CSS ICW SW FW
Mobile: +38099 50 19 714
Bohdan.Hunko(a)infineon.com<mailto:Bohdan.Hunko@infineon.com>
Hi Thomas and all,
I noticed there are some
#if !defined(__ICCARM__)
".syntax unified \n"
#endif
In source code, looks like ".syntax unified" is not support in IAR, is that true? If it could not be supported in a short term, we can define some wrapper such as:
#ifdef __ICCARM__
#define CLAIM_SYNTAX_UNIFIED "\n"
#else
#define CLAIM_SYNTAX_UNIFIED ".syntax unified \n"
#endif
Another question is about the:
#if defined(__ICCARM__)
#pragma required = do_schedule
#endif
If we claim do_schedule in the constraints, is the above "#pragma required" still needed?
__asm (".... :: "i"(do_schedule));
We can create a patch to test this - using a constraint looks more proper.
Thanks.
/Ken
Hi Sebastian,
The section in the Platform Security Model is describing the behavior of a system reset – the recommendation is that any preceding runtime state (in volatile memory, or in CPU or peripheral registers) does not influence the execution of the reboot. This is except for an optional suspend or hibernate state, which explicitly maintains runtime state while powering off most or all of the system and will resume via a CPU reset.
System security requirements might require explicit clearing of volatile memory on reset to prevent cold-boot style attacks that could allow an attacker to read any residual RAM contents – although software-based attacks of this kind are partly mitigated by trusted boot, which prevents an attacker from running arbitrary code at reset (unlike devices that boot from untrusted flash memory).
The specific bullet list in the PSA Firmware Framework for M (in §3.5.1 on Panics) is describing the challenges for an implementation that does NOT do the recommended action of resetting the system when a Secure Partition panics, which justifies the recommendation to reset the system. If the SPM does reset the system, then the challenges in that bullet list are avoided. The issues listed are:
> * An individual Secure Partition cannot be reset and restarted in isolation.
> * A Secure Partition may have state maintained on behalf of clients that will be destroyed when restarting the service. There is no mechanism to re-synchronize the clients.
> * It is not possible to determine at the point of panic how much corruption has occurred within the Secure Partition and elsewhere in the SPE.
If the SPM only restarted the Secure Partition that panicked, then any previous runtime state within that Secure Partition is lost, including any ongoing connections with clients of services within that partition, or any resources that those services were managing for their clients. FF-M does not provide a specified mechanism for such clients to be informed that the connections are broken, and there is no way to provide a general strategy that allows a client to recover from a service failure. This is what is meant by “There is no mechanism to re-synchronize the clients.”.
I have just realized that in FF-M 1.1, there may be scenarios in which restarting a Secure Partition could be justified and technically feasible. If a Secure Partition with only Stateless services maintains no client state or resources, and also maintains no connections to other RoT Services (so there are no RoT Services maintaining state for this Secure Partition) – then restarting this Secure Partition might not suffer from the first two complications listed in §3.5.1. The third issue is harder to control: the risks from the data corruption that lead up to the panic depends partly on the SPE isolation policies, and on what this Secure Partition was responsible for. Reset remains the recommended response to a Secure Partition panic in v1.1.0.
Regards,
Andrew Thoelke
Arm Ltd.
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Ken Liu via TF-M
Sent: 26 October 2021 10:51
To: tf-m(a)lists.trustedfirmware.org
Cc: nd <nd(a)arm.com>
Subject: Re: [TF-M] System reset
Hi Sebastian,
The specification writer looks not here these two days, let me try to explain it based on my understanding.
I think two specs both recommend clearing general runtime data while resetting. If the booting runtime clearing code can clear the RAM data for a specific platform, the memory clearing in the 'tfm_spm_hal_system_reset ' can be skipped. Basically, simple hardware reset triggering is just fine.
The special-purpose memory to be retained during resetting is not a generic runtime memory, hence they need to be treated specially, such as putting them in a special bank or region and skipping clearing them during booting. This special region can be treated as a private asset of one service, which could NOT be shared between components for direct access. The owner service provides the functionality around this asset.
Please put more comments or corrections, thanks.
/Ken
From: TF-M <mailto:tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Sebastian Bøe via TF-M
Sent: Monday, October 25, 2021 3:16 PM
To: mailto:tf-m@lists.trustedfirmware.org
Subject: [TF-M] System reset
Hi,
I would like some clarification about system reset.
There are these two statements about it in the PSM and PSA-FF:
"No run-time state from before the reset should be retained or used, except where necessary if suspend or hibernate are supported, see section 4.6." -- PSM page 22.
"A Secure Partition may have state maintained on behalf of clients that will be destroyed when restarting the service." -- PSA-FF page 47.
Is it the responsibility of tfm_spm_hal_system_reset to destroy this state or is it OK to destroy it after reset as a part of the C runtime startup procedure?
I assume for instance that PRoT .bss is cleared as a part of the C runtime startup procedure, but should it also have been destroyed as a part of tfm_spm_hal_system_reset ?
PSM - Platform Security Model.
https://developer.arm.com/documentation/den0128/0100/
PSA-FF PSA Firmware Framework
https://armkeil.blob.core.windows.net/developer/Files/pdf/PlatformSecurityA…
Sebastian Bøe
Nordic Semiconductor
Hi all,
I'm been working to unify the HAL APIs for IPC Model.
The IPC Model currently uses two different sets of HAL APIs:
* tfm_spm_hal_* - This is mainly used by the Library Model and IPC Model re-uses some of them
* tfm_hal_* - This is introduced for IPC Model and some are shared to Library Model
This might be confusing for platform vendors.
So I'm trying to make it clear for IPC Model by:
* Duplicating the shared APIs and rename the IPC copy to tfm_hal_*
* Combining several platform init APIs to a single tfm_platform_init for IPC Model
* tfm_spm_hal_enable_fault_handlers
* tfm_spm_hal_system_reset_cfg
* tfm_spm_hal_init_debug
* tfm_spm_hal_nvic_interrupt_target_state_cfg
* tfm_spm_hal_nvic_interrupt_enable
With these changes, IPC Model will use tfm_hal_* APIs only.
Please platform owners review these patches<https://review.trustedfirmware.org/q/topic:%22decouple_legacy_hal_for_ipc%2…> to see if any mistakes (the patches mainly move codes around) or any platforms missed in the patches.
Plan to have them merged before the end of October. Thanks.
Best Regards,
Kevin
Hi,
I would like some clarification about system reset.
There are these two statements about it in the PSM and PSA-FF:
"No run-time state from before the reset should be retained or
used, except where necessary if suspend or hibernate are supported,
see section 4.6." -- PSM page 22.
"A Secure Partition may have state maintained on behalf of clients
that will be destroyed when restarting the service." -- PSA-FF page
47.
Is it the responsibility of tfm_spm_hal_system_reset to destroy this state
or is it OK to destroy it after reset as a part of the C runtime startup
procedure?
I assume for instance that PRoT .bss is cleared as a part of the C runtime
startup
procedure, but should it also have been destroyed
as a part of tfm_spm_hal_system_reset ?
PSM - Platform Security Model.
https://developer.arm.com/documentation/den0128/0100/
PSA-FF PSA Firmware Framework
https://armkeil.blob.core.windows.net/developer/Files/pdf/PlatformSecurityA…
Sebastian Bøe
Nordic Semiconductor