Hi all,
I try to enable the smmu of Juno R2 development board but face two great challenges. I am working on them and I still need some hints. Here are my problems:
1. By reading the SMMUv1 manuals I find that several registers are related to secure state (e.g., SMMU_sCR0). But in my TF-A and the latest version I can only find the SMMUv3 configurations, not SMMUv1/2. Thus, how to config these registers? Any reference?
2. For the non-secure GPU SMMU regs, I try to map and read them based on the Juno R2 manual. I know the GPU SMMU is a MMU-400, and its mmio is in 0x2b40_0000 - 0x2b40_ffff. Then in EL1 I first do ioremap(0x2b400000,0x10000) and then ioread32(). However I get the SError as "Bad mode in Error handler detected on CPU1, code 0xbf000002". I also try to do it in EL2 (with a hvc call and reading in the handler), but cannot get any valid number and still get SError when exiting EL2. But when I access the other smmus (e.g., a PCIe SMMU, in 0x2b50_0000), it works fine. Thus, is there something to prevent the Non-secure World from accessing the GPU SMMU MMIO?
My source codes are downloaded from the arm-reference-platforms, in which Linux is v4.14.59 and TF-A is v2.1.
Can someone help me?
Sincerely, WANG Chenxu
Hi all,
Sorry, but I forget to say two findings.
1. I am using the Android kernel provided by the arm-reference-platforms. It has a Mali GPU driver but seems to disable the GPU SMMU.
2. I also find that I can access the GPU SMMU MMIO region from EL3 *ONLY* when executing the GPU tasks. For example, I trap the submission of GPU task, routing into EL3 and try to access the GPU MMIO. Only at this timepoint I can read or write the GPU SMMU MMIO region. But when GPU task is finished or in system initialization (e.g., running at BL31), I cannot access the GPU SMMU MMIO from EL3 (the system will hang in EL3). I mention that I can write to GPU SMMU MMIO from EL3 and successfully read the changes. However, when I do such things again in the next GPU task, the changed register value is restored.
Sincerely, WANG Chenxu
Chenxu Wang irakatz51@gmail.com 于2023年3月22日周三 04:46写道：
Hi all,
I try to enable the smmu of Juno R2 development board but face two great challenges. I am working on them and I still need some hints. Here are my problems:
- By reading the SMMUv1 manuals I find that several registers are
related to secure state (e.g., SMMU_sCR0). But in my TF-A and the latest version I can only find the SMMUv3 configurations, not SMMUv1/2. Thus, how to config these registers? Any reference?
- For the non-secure GPU SMMU regs, I try to map and read them based
on the Juno R2 manual. I know the GPU SMMU is a MMU-400, and its mmio is in 0x2b40_0000 - 0x2b40_ffff. Then in EL1 I first do ioremap(0x2b400000,0x10000) and then ioread32(). However I get the SError as "Bad mode in Error handler detected on CPU1, code 0xbf000002". I also try to do it in EL2 (with a hvc call and reading in the handler), but cannot get any valid number and still get SError when exiting EL2. But when I access the other smmus (e.g., a PCIe SMMU, in 0x2b50_0000), it works fine. Thus, is there something to prevent the Non-secure World from accessing the GPU SMMU MMIO?
My source codes are downloaded from the arm-reference-platforms, in which Linux is v4.14.59 and TF-A is v2.1.
Can someone help me?
Sincerely, WANG Chenxu
tf-a@lists.trustedfirmware.org
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Chenxu Wang