Hey all:
We are trying to port ARM Trust-Firmware-A to our design, however, we are facing serious SRAM size problem.
Our target SRAM is 64KB, but the compiled BL2 already taken 60K:
After some evaluation, we found that the MMU table take most of the space. Our questions are:
1. Can we disable the MMU so we can fit the BL2 into 64KB space? (However, in ARM's porting guide, enable MMU and icache/dcache is mandatory. Refer to chapter 7.3 in https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/porting-g... https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/porting-guide.html#introduction.）
2. In current design, BL31 is run in SRAM. If we enable DDR in BL2 and load BL31 image to DDR, is there any potential issue?
Thanks in advances,
Hey all:
We are trying to port ARM Trust-Firmware-A to our design, however, we are facing serious SRAM size problem.
Our target SRAM is 64KB, but the compiled BL2 already taken 60K, After some evaluation, we found that the MMU table take most of the space. Our questions are:
1. Can we disable the MMU so we can fit the BL2 into 64KB space? (However, in ARM's porting guide, enable MMU and icache/dcache is mandatory. Refer to chapter 7.3 in https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/porting-g... https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/porting-guide.html#introduction.）
2. In current design, BL31 is run in SRAM. If we enable DDR in BL2 and load BL31 image to DDR, is there any potential issue?
Thanks in advances,
Shaolin.
tf-a@lists.trustedfirmware.org
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shaolin.xie