Hi Soby,

On Fri, 13 Dec 2019 15:08:07 +0000 Soby Mathew Soby.Mathew@arm.com wrote:

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Hi Jisheng, This is due to the power management requirement of GICv3. In section 7.1 of GICv3 specification : https://static.docs.arm.com/ihi0069/c/IHI0069C_gic_architecture_specificatio...

It says the that " Before powering down the CPU interface and the PE when the Redistributor is powered up, software must put the interface between the CPU interface and the Redistributor into the quiescent state or the system will become UNPREDICTABLE". In order to put the Redistributor in a quiescent state, all the group enables in CPU interface must be disabled , otherwise "setting GICR_WAKER.ProcessorSleep to 1 when the physical group enables in the CPU interface are set to 1 results in UNPREDICTABLE behavior."

Got it. Thank you very much for the detailed explanation, it's helpful.

Thanks a lot

Hope that clarifies.

Best Regards Soby Mathew

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-----Original Message----- From: TF-A tf-a-bounces@lists.trustedfirmware.org On Behalf Of Jisheng Zhang via TF-A Sent: 05 December 2019 10:31 To: tf-a@lists.trustedfirmware.org Subject: [TF-A] About disable gic cpuif in psci suspend or off

Hi,

In ATF-A, I usually see below code in psci suspend or off code path:

    /* Prevent interrupts from spuriously waking up this cpu */
    plat_arm_gic_cpuif_disable();

But per my understanding, before calling psci_suspend(), the NW, e.g linux kernel has disabled all interrupts from cpu level, so here preventing interrupt is to prevent the interrupts from secure world?

Another question is: for Cortex A55, this is not necessary. Because CA55 TRM says when the core_pwrdn_en bit is set, executing WFI automatically masks all interrupts and wake-up events in the core. Am I right?

Thanks in advance