Are there any time estimates when the fix should be in?
On Sat, 10 Aug 2019 at 22:46, Marek via TF-A email@example.com wrote:
Thank you Dan for checking this out. Looking forward into the fix.
On Thu, 8 Aug 2019 at 17:52, Dan Handley via TF-A firstname.lastname@example.org wrote:
Thanks for pointing this out. Typically we expect any timing sensitive secure operations to be implemented at Secure-EL1 or lower, which the current code does protect. However, you are correct that all secure world code including EL3 should not expose timing information. A fix is in progress to address this.
-----Original Message----- From: TF-A email@example.com On Behalf Of Marek Bykowski via TF-A Sent: 03 August 2019 07:37 To: firstname.lastname@example.org; David Cunado David.Cunado@arm.com Subject: [TF-A] Advisory TFV 5 to CVE-2017-15031 only saves/stores the PMCR_EL0 across world switching
Hi David/ATF Support,
An excerpt from the commit message to CVE-2017-15031 is "Additionally, PMCR_EL0 is added to the list of registers that are saved and restored during a world switch."
My question is why it is only being saved/restored across the world switch and not during a "normal" SMC call? When I do modify the PMCR_EL0 in EL2 or NonSecure-EL1 and run the smc call the PMCCNTR counter counts during the smc call and does expose secure world timing information to NonSecure in that matter.
Thanks, Marek -- TF-A mailing list TF-A@lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-a
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-- Slán, Marek -- TF-A mailing list TF-A@lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-a