Another option to BL31 in system memory (DDR) is, which we are exploring, is loading an image (in our case BL33/Uboot) to system caches (inner L1/L2 & outer LLC/L3 which ever) and initialize the DDR from within it. This is not trivial though but working successfully with us for Cortex-A15, A53 and A57 with CCN (Cache Coherent Network 504 and 512) featuring the Last Level Cache on three of our SoCs.
Marek
On Fri, 10 Jan 2020 at 11:12, Soby Mathew via TF-A < tf-a@lists.trustedfirmware.org> wrote:
On 10/01/2020 09:05, shaolin.xie via TF-A wrote:
Hey all:
We are trying to port ARM Trust-Firmware-A to our design, however, we
are facing serious SRAM size problem.
Our target SRAM is 64KB, but the compiled BL2 already taken 60K:
After some evaluation, we found that the MMU table take most of the
space. Our questions are: Hi Shaolin, There are some options to reduce the memory used for page-tables like using non-identity virtual to physical mappings. But given your SRAM size, I suspect you may not save enough to fit BL31.
- Can we disable the MMU so we can fit the BL2 into 64KB space? (However, in ARM's porting guide, enable MMU and icache/dcache is
mandatory. Refer to chapter 7.3 in https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/porting-g... < https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/porting-g...
.）
This is a possibility although not recommended for performance reasons and you lose the protection of MMU during BL2 execution. This is not a configuration we support an I suspect some changes to BL2 code may be required for this.
- In current design, BL31 is run in SRAM. If we enable DDR in BL2 and
load BL31 image to DDR, is there any potential issue?
Thanks in advances,
It is possible to create a secure carve-out in DDR and execute BL31 from there. It is less `secure` than running from SRAM but it is acceptable for some market segments depending on the threat model.
You target SRAM of 64 KB is on the lower side and fitting both BL2 and BL31 in that space could be a challenge.
Could you let us know your BL2 and BL31 size and could you break down the size in terms of PROGBITS and NOPROG BITS? The BL31 NOPROG BITS are usually overlayed on top of BL2 memory and this will let us know whether fitting both in SRAM is even possible. If both cannot fit together in SRAM, there are other options you can explore like loading BL31 directly from BootROM or using BL2 as an XIP BootROM image.
Best Regards Soby Mathew
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Marek