-----Original Message----- From: TF-A tf-a-bounces@lists.trustedfirmware.org On Behalf Of Thor Thayer via TF-A Sent: 20 June 2019 09:05 To: tf-a@lists.trustedfirmware.org Subject: [TF-A] Can 1 Core in EL3 elevate other 3 cores to EL3?
Hi,
I have a quad-core ARM64 Cortex-A53 where 1 core is executing in EL3 while the other 3 cores are in EL1. The 3 cores in EL1 are spinning in a WFI loop. The EL3 CPU transitioned to EL3 as a result of the PSCI RESET2 call from Linux.
Is there a way for the EL3 core to switch the other cores into EL3 easily?
Hi Thor, One way to do this to configure an IPI (SGI in GICv3 terminology) to be an EL3 interrupt (Group 0). Trigger this IPI from the first core to all the other 3 cores. This will cause the 3 cores to transition to EL3 to handle the EL3 interrupt and you will have to configure a suitable interrupt handler.
Implication of this new EL3 IPI is that it can also cause the core to transition to EL3 if triggered when executing in Secure world.
Also be aware that configuration of any EL3 interrupt will affect the routing model and change the behaviour of normal world interrupts when executing in Secure world. The secure world executing a "yielding" SMC request will get pre-empted on occurrence of normal world interrupt and the secure world may not get a chance to do a "controlled exit".
Usually the PSCI_RESET2 can work without all the cores being in EL3. Could you elaborate why the other cores need to be in EL3 for this reset?
As far as I know, the communication between cores takes place through the IPI. Unfortunately, in my case, an SError has occurred that is masking the IPI.
If I understand correctly, the PSCI_RESET2 is being issued after the SError has happened on other cores. The EL3 IPI should cause these cores to transition to EL3 regardless of the interrupt mask state at lower Els.
Thanks,
Thor
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Hi Soby,
On 6/20/19 4:14 AM, Soby Mathew wrote:
-----Original Message----- From: TF-A tf-a-bounces@lists.trustedfirmware.org On Behalf Of Thor Thayer via TF-A Sent: 20 June 2019 09:05 To: tf-a@lists.trustedfirmware.org Subject: [TF-A] Can 1 Core in EL3 elevate other 3 cores to EL3?
Hi,
I have a quad-core ARM64 Cortex-A53 where 1 core is executing in EL3 while the other 3 cores are in EL1. The 3 cores in EL1 are spinning in a WFI loop. The EL3 CPU transitioned to EL3 as a result of the PSCI RESET2 call from Linux.
Is there a way for the EL3 core to switch the other cores into EL3 easily?
Hi Thor, One way to do this to configure an IPI (SGI in GICv3 terminology) to be an EL3 interrupt (Group 0). Trigger this IPI from the first core to all the other 3 cores. This will cause the 3 cores to transition to EL3 to handle the EL3 interrupt and you will have to configure a suitable interrupt handler.
Implication of this new EL3 IPI is that it can also cause the core to transition to EL3 if triggered when executing in Secure world.
Also be aware that configuration of any EL3 interrupt will affect the routing model and change the behaviour of normal world interrupts when executing in Secure world. The secure world executing a "yielding" SMC request will get pre-empted on occurrence of normal world interrupt and the secure world may not get a chance to do a "controlled exit".
Hmm. I may not understand this statement completely, but I think I'm OK here.
Usually the PSCI_RESET2 can work without all the cores being in EL3. Could you elaborate why the other cores need to be in EL3 for this reset?
Thank you for the insight. James Morse suggested something similar but I didn't completely understand. This sounds promising so I'll investigate further.
You are correct that PSCI_RESET2 works fine when called from a normal warm reset request. In my case, I'm calling PSCI_RESET2 from SError interrupt context which masks IRQ.
However, the pending SError and IRQs don't allow the CPUs to stay in WFI (checked with an incrementing register inside the while(1) {wfi} loop). Therefore the Warm Reset doesn't occur.
I tried disabling all IRQs by clearing the GICD_CTLR from the EL3 CPU but the pending SError prevents the CPUs from staying in WFI.
As an experiment, I replaced the while(1) WFI loop with a SMC call to EL3. The SError/IRQ aren't pending there and I was able to get a warm reset to work.
James suggested using the EL3 CPU to hoist the other 3 CPUs to EL3 but I wasn't clear on how to do that. Thanks to your reply, I can see a possible solution.
Thanks for your comment!
Thor
As far as I know, the communication between cores takes place through the IPI. Unfortunately, in my case, an SError has occurred that is masking the IPI.
If I understand correctly, the PSCI_RESET2 is being issued after the SError has happened on other cores. The EL3 IPI should cause these cores to transition to EL3 regardless of the interrupt mask state at lower Els.
Thanks,
Thor
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Soby Mathew -
Thor Thayer