Hi, Pali,
Both A3710 and A3720 have L2 cache, but the A3710 has a single CPU, so this erratum is not applicable to it (has to be MPCore)
regards Konstantin
________________________________ From: Pali Rohár pali@kernel.org Sent: Sunday, September 26, 2021 17:57 To: Joanna Farley Joanna.Farley@arm.com; Kostya Porotchkin kostap@marvell.com; Bipin Ravi Bipin.Ravi@arm.com Cc: Olivier Deprez Olivier.Deprez@arm.com; tf-a@lists.trustedfirmware.org tf-a@lists.trustedfirmware.org; Marek Behún marek.behun@nic.cz Subject: [EXT] Re: [TF-A] A53 errata 855873 on Marvell Armada 3720 (Was: Re: Missing CPU workaround warning message)
External Email
---------------------------------------------------------------------- Hello Joanna! Thank you for response.
Konstantin, could you check if A3720 is affected by that ARM errata 855873?
Bipin or Joanna, in ARM errata 855873 is described "system cache". What kind of cache it is? It is L3 or L2 or some other? Because I do not understand to which cache that errata description refers.
On Sunday 26 September 2021 14:49:19 Joanna Farley wrote:
Hi Pali,
Konstantin needs to respond for platform specific questions as the Marcell Platform owner and I see he is copied directly here while Bipin can follow up if you need any more generic Errata guidance. I think for the latter all questions have been answered?
Joanna
On 26/09/2021, 15:04, "TF-A on behalf of Pali Rohár via TF-A" <tf-a-bounces@lists.trustedfirmware.org on behalf of tf-a@lists.trustedfirmware.org> wrote:
Hello! Gentle reminder, could you help us with this issue? On Monday 06 September 2021 21:32:26 Pali Rohár wrote: > Hello! Could you help with this issue? > > On Friday 27 August 2021 12:52:25 Pali Rohár wrote: > > Hello! > > > > On Friday 09 July 2021 14:53:57 Pali Rohár wrote: > > > Hello! > > > > > > > From: Pali Rohár <pali@kernel.org> > > > > Sent: 09 July 2021 14:28 > > > > To: Varun Wadekar > > > > Cc: Olivier Deprez; Bipin Ravi; Konstantin Porotchkin; Marek Behún; tf-a@lists.trustedfirmware.org > > > > Subject: Re: [TF-A] Missing CPU workaround warning message > > > > > > > > Hello! > > > > > > > > It seems that ARM erratas 855873 and 1530924 affect all revisions of A53 > > > > CPU, which is in Marvell Armada 3720 platform. > > > > > > > > So setting compile time macros > > > > > > > > ERRATA_A53_855873 := 1 > > > > ERRATA_A53_1530924 := 1 > > > > > > > > in plat/marvell/armada/a3k/common/a3700_common.mk should be enough? > > > > > > > > > > > > [OD] In general it's a platform maintainer duty to analyse applicable errata from the software developer notice (SDEN) and judge. Yes it looks reasonable to enable those but make sure it doesn't affect other SW stacks (e.g. kernel) by enabling those in the firmware, for any platform which uses this chipset. You can poll through the ML when doing this change. > > > > > > Konstantin (already in email loop) is platform maintainer. > > > > Could somebody with ARM knowledge helps with A53 errata 855873? > > > > According to this ARM document (A53 Software Developers Errata Notice) > > https://urldefense.proofpoint.com/v2/url?u=https-3A__documentation-2Dservice.arm.com_static_5fa29fddb209f547eebd361d&d=DwIDaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=-N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=YD07WZDuNHuftX1ObE78WkdJ8foc_PZVTFkzNkoqoNc&s=O3wEVfZWnHqatJVqMzCvpK86i_XYitN9-8cc5rjDTbI&e= > > errata 855873 affects A53 if CPU is connected to some interconnect with > > system cache or a snoop filter. > > > > Marvell Armada 3720 uses interconnect CCI-400 which according to ARM > > information does not have a snoop filter. And A53 does not have L3 > > cache, it has only L2 cache. > > > > What is that "system cache" which is described in above ARM document for > > errata 855873? L2 or L3 cache? Or something else? And how to check if > > Marvell Armada 3720 platform has this "system cache"? > > > > Konstantin, do you know something about this A53 errata 855873? And if > > it affects Armada 3720 platform? > > > > > > On Wednesday 07 July 2021 21:59:25 Varun Wadekar wrote: > > > > > Hi Pali, > > > > > > > > > > My understanding of the errata reporting mechanism is that some erratas are always checked during CPU boot. If the corresponding MACRO (ERRATA_A53_*) is disabled, then the ERRATA_MISSING code is reported. > > > > > > > > > > I would be concerned if the CPU is affected by the errata. If the errata needs to be enabled, the fix would be to enable the ERRATA_A53_* from the platform makefile. > > > > > > > > > > > > From: TF-A <tf-a-bounces@lists.trustedfirmware.org> on behalf of > > > > > > > Pali Rohár via TF-A <tf-a@lists.trustedfirmware.org> > > > > > > > Sent: 28 June 2021 15:36 > > > > > > > To: tf-a@lists.trustedfirmware.org > > > > > > > Cc: Konstantin Porotchkin; Marek Behún > > > > > > > Subject: [TF-A] Missing CPU workaround warning message > > > > > > > > > > > > > > Hello! If TF-A for Marvell Armada 3720 platform is compiled in debug > > > > > > > mode then at runtime it prints following warning messages: > > > > > > > > > > > > > > WARNING: BL1: cortex_a53: CPU workaround for 855873 was missing! > > > > > > > WARNING: BL1: cortex_a53: CPU workaround for 1530924 was missing! > > > > > > > > > > > > > > These lines are not printed in non-debug mode. It is an issue? -- TF-A mailing list TF-A@lists.trustedfirmware.org https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.trustedfirmware.org_mailman_listinfo_tf-2Da&d=DwIDaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=-N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=YD07WZDuNHuftX1ObE78WkdJ8foc_PZVTFkzNkoqoNc&s=Z4_G4HxjneT33RPbf7rEiihjdpwMsASkHnz1Z9SxpXg&e=