After updating to ATF v2.5 on the Xilinx ZynqMP platform, I was having issues with the FPGA PL logic not loading successfully from U-Boot, it was failing with this error:
PL FPGA LOAD failed with err: 0x000007d6
which is PM_RET_ERROR_TIMEOUT. The following commit introduced the timeout:
commit 4d9b9b2352f9a67849faf2d4484f5fcdd2788b01 Author: Tejas Patel tejas.patel@xilinx.com Date: Thu Feb 25 02:37:09 2021 -0800
plat: xilinx: Add timeout while waiting for IPI Ack
Return timeout error if, IPI is not acked in specified timeout.
Signed-off-by: Tejas Patel tejas.patel@xilinx.com Change-Id: I27be3d4d4eb5bc57f6a84c839e2586278c0aec19
The timeout value (TIMEOUT_COUNT_US) is set to 0x4000 (16384) usec, which appears to be too short for the FPGA loading operation (at least on the ZCU102 board with XCZU9EG device), causing it to always timeout. Increasing the timeout to 0xF4240 usec (i.e. 1 second) fixes the issue, though some lower value may also be sufficient.