Hi,
The PSCI specification defines two different power state coordination modes
for CPU_SUSPEND that can be used to put a core or a group of cores into a
low-power state. These modes are the platform-coordinated mode (default)
and the OS-initiated mode (optional). OS-initiated mode is currently not
supported by TF-A, while both modes are supported by the Linux Kernel.
Requesting reviews for the patches [1] adding support for OS-initiated mode
in TF-A and the corresponding tests in TF-A-Tests. Any feedback and
comments are much appreciated.
Thanks in advance!
Wing
[1] https://review.trustedfirmware.org/q/topic:psci-osi
Hello,
I'm a noob here, and I need help. I've just built flash-image.bin for
my MACCHIATObin Single Shot as follows, but it fails to boot - as
follows further below:
- git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
- Clone the binaries-marvell and mv-ddr-marvell Git repos alongside the
trusted-firmware-a, and check out revisions as recommeded in TF-A build
instructions for Armada80x0
(https://trustedfirmware-a.readthedocs.io/en/latest/plat/marvell/armada/buil…).
- export
CROSS_COMPILE=/my/path/to/arm-gnu-toolchain/11.3.rel1-x86_64-aarch64-none-elf/bin/aarch64-none-elf-
- Build u-boot.bin:
- git clone https://source.denx.de/u-boot/u-boot.git alongside the
binaries-marvell and mv-ddr-marvell repos.
- cd u-boot
- git checkout v2023.01 - the latest release.
- make mvebu_mcbin-88f8040_defconfig
- Change CONFIG_DEFAULT_DEVICE_TREE to "armada-8040-mcbin-singleshot"
(inspired by this SolidRun doc:
https://github.com/SolidRun/documentation/blob/bsp/8040/u-boot.md).
- Add arch/arm/dts/armada-8040-mcbin-singleshot.dts. Can be obtained
e.g. from the latest Marvell kernel sources
(https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/marvell/).
- make
- Built fine.
- Build TF-A:
- cd ../trusted-firmware-a/
- git checkout v2.8.0 - the latest release, as per changelog
(https://trustedfirmware-a.readthedocs.io/en/latest/change-log.html).
- make PLAT=a80x0_mcbin MV_DDR_PATH=../mv-ddr-marvell
SCP_BL2=../binaries-marvell/mrvl_scp_bl2.img BL33=../u-boot/u-boot.bin
mrvl_flash
- Built fine.
Then I flashed the flash-image.bin onto my SD card: dd
if=trusted-firmware-a/build/a80x0_mcbin/release/flash-image.bin
of=/dev/mmcblk0 seek=4096 conv=fdatasync,notrunc (as per
https://archlinuxarm.org/platforms/armv8/marvell/macchiatobin).
It boots, but complains about a missing serial driver and resets in a loop:
---
BootROM - 2.03
Starting CP-0 IOROM 1.07
Booting from SD 0 (0x29)
Found valid image at boot postion 0x002
lNOTICE: Starting binary extension
NOTICE: SVC: DEV ID: 8040, FREQ Mode: 0xd
NOTICE: SVC: AVS work point changed from 0x29 to 0x29
mv_ddr: devel-g541616b (Mar 05 2023 - 14:15:32)
mv_ddr: completed successfully
NOTICE: Cold boot
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.8(release):v2.8
NOTICE: BL1: Built : 14:15:45, Mar 5 2023
NOTICE: BL1: Booting BL2
NOTICE: BL2: v2.8(release):v2.8
NOTICE: BL2: Built : 14:15:48, Mar 5 2023
NOTICE: SCP_BL2 contains 7 concatenated images
NOTICE: Load image to CP1 MG
NOTICE: Loading MG image from address 0x402305c Size 0xe0f0 to MG at
0xf4100000
NOTICE: Load image to CP0 MG
NOTICE: Loading MG image from address 0x403114c Size 0xe0f0 to MG at
0xf2100000
NOTICE: Skipping MSS CP3 related image
NOTICE: Skipping MSS CP2 related image
NOTICE: Load image to CP1 MSS AP0
NOTICE: SECURELY Loading MSS FW from addr. 0x4042c34 Size 0x1cfc to MSS
at 0xf4280000
NOTICE: CP MSS startup is postponed
NOTICE: Done
NOTICE: Load image to CP0 MSS AP0
NOTICE: SECURELY Loading MSS FW from addr. 0x4044930 Size 0x1cfc to MSS
at 0xf2280000
NOTICE: CP MSS startup is postponed
NOTICE: Done
NOTICE: Load image to AP0 MSS
NOTICE: Loading MSS FW from addr. 0x404662c Size 0x5400 to MSS at
0xf0580000
NOTICE: Done
NOTICE: SCP Image doesn't contain PM firmware
NOTICE: BL1: Booting BL31
lNOTICE: Starting CP0 MSS CPU
NOTICE: Starting CP1 MSS CPU
NOTICE: MSS PM is not supported in this build
NOTICE: BL31: v2.8(release):v2.8
NOTICE: BL31: Built : 14:15:55, Mar 5 2023
<debug_uart>
No serial driver found
resetting ...
---
Can anyone advise how to fix this? Is this list even the right place to
ask such questions?
Maciej
--
Maciej Sieczka
http://www.sieczka.org
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)
** CID 383288: (CHECKED_RETURN)
/mbedtls/library/bignum.c: 1670 in mbedtls_mpi_exp_mod()
/mbedtls/library/bignum.c: 1867 in mbedtls_mpi_exp_mod()
________________________________________________________________________________________________________
*** CID 383288: (CHECKED_RETURN)
/mbedtls/library/bignum.c: 1670 in mbedtls_mpi_exp_mod()
1664 *
1665 * To achieve this, we make a copy of X and we use the table entry in each
1666 * calculation from this point on.
1667 */
1668 const size_t x_index = 0;
1669 mbedtls_mpi_init( &W[x_index] );
>>> CID 383288: (CHECKED_RETURN)
>>> Calling "mbedtls_mpi_copy" without checking return value (as is done elsewhere 43 out of 46 times).
1670 mbedtls_mpi_copy( &W[x_index], X );
1671
1672 j = N->n + 1;
1673 /* All W[i] and X must have at least N->n limbs for the mpi_montmul()
1674 * and mpi_montred() calls later. Here we ensure that W[1] and X are
1675 * large enough, and later we'll grow other W[i] to the same length.
/mbedtls/library/bignum.c: 1867 in mbedtls_mpi_exp_mod()
1861 MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &W[x_index], N, &W[x_index] ) );
1862 }
1863
1864 /*
1865 * Load the result in the output variable.
1866 */
>>> CID 383288: (CHECKED_RETURN)
>>> Calling "mbedtls_mpi_copy" without checking return value (as is done elsewhere 43 out of 46 times).
1867 mbedtls_mpi_copy( X, &W[x_index] );
1868
1869 cleanup:
1870
1871 /* The first bit of the sliding window is always 1 and therefore the first
1872 * half of the table was unused. */
** CID 383287: Null pointer dereferences (FORWARD_NULL)
________________________________________________________________________________________________________
*** CID 383287: Null pointer dereferences (FORWARD_NULL)
/mbedtls/library/rsa_alt_helpers.c: 134 in mbedtls_rsa_deduce_primes()
128
129 for( ; attempt < num_primes; ++attempt )
130 {
131 mbedtls_mpi_lset( &K, primes[attempt] );
132
133 /* Check if gcd(K,N) = 1 */
>>> CID 383287: Null pointer dereferences (FORWARD_NULL)
>>> Passing "P" to "mbedtls_mpi_gcd", which dereferences null "P->p".
134 MBEDTLS_MPI_CHK( mbedtls_mpi_gcd( P, &K, N ) );
135 if( mbedtls_mpi_cmp_int( P, 1 ) != 0 )
136 continue;
137
138 /* Go through K^T + 1, K^(2T) + 1, K^(4T) + 1, ...
139 * and check whether they have nontrivial GCD with N. */
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
mmc_enumerate() is the only caller of mmc_send_op_cond().
mmc_enumerate() calls mmc_reset_to_idle() just before calling
mmc_send_op_cond(). No need to do that again in mmc_send_op_cond().
Signed-off-by: Baruch Siach <baruch(a)tkos.co.il>
Change-Id: Ib8c8ed1a559e3fecb315245f91bb3dc1f547d820
---
Sending the patch to the list once again. review.trustedfirmware.org
does not work for me.
https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…
---
drivers/mmc/mmc.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 2b727d4e7696..57f47482013a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -452,11 +452,6 @@ static int mmc_send_op_cond(void)
int ret, n;
unsigned int resp_data[4];
- ret = mmc_reset_to_idle();
- if (ret != 0) {
- return ret;
- }
-
for (n = 0; n < SEND_OP_COND_MAX_RETRIES; n++) {
ret = mmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7,
--
2.39.2
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Hi,
In ARM TBBR, there is a requirement
“R0100_TBBR_AFM_FLASHING” (The AP firmware must switch to the Non-Trusted world for executing the SoC firmware loader),
But there is no requirement for secure boot as long as I finish chain if ROT verification.
So, can I implement FWU in BL2 which is verified and load from BL1 (ROM)?
For example,
BL1(ROM) -> Load and verify BL2U with new image from SD to secure RAM -> execute BL2U in Secure RAM then write new image to NAND flash
Best regards,
Jun
This event has been updated
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Agenda UpdateTitle:PSCI OS-initiated mode in TF-APresented by:Maulik Shah,
Ulf Hansson, Wing LiAgenda:1. Overview of OS-initiated mode2. Why
OS-initiated mode?3. Implementation details and testing in TF-AThanks
AllJoanna===============================We run an open technical forum call
for anyone to participate and it is not restricted to Trusted Firmware
project members. It will operate under the guidance of the TF TSC. Feel
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This event has been updated
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Agenda UpdateTitle:PSCI OS-initiated mode in TF-APresented by:Maulik Shah,
Ulf Hansson, Wing LiAgenda:1. Overview of OS-initiated mode2. Why
OS-initiated mode?3. Implementation details and testing in TF-AThanks
AllJoanna===============================We run an open technical forum call
for anyone to participate and it is not restricted to Trusted Firmware
project members. It will operate under the guidance of the TF TSC. Feel
free to forward this invite to colleagues. Invites are via the TF-A mailing
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Hi,
I have one question about SIP Service Calls range and it's range checking.
Based on DEN0028E SIP Service Calls ranges are
0x82000000-0x8200FFFF SMC32: SiP Service Calls
0xC2000000-0xC200FFFF SMC64: SiP Service Calls
That's the ranges which we are using for implementing SOC specific SMC handlers
and I found that in past it was also added code which is out of this range.
Specifically in Xilinx ZynqMP you can see code like this
if (is_em_fid(smc_fid)) {
return em_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
flags);
}
where EM range is 0x820e0001- 0x820e0003 is out of our range which is assigned
to us. But there is no failure at all that we are out of ranged in spec.
Shouldn't this be enforced by core itself?
That's why I just wanted to know your opinion about it. We will definitely
implement better masking to find out that 0x00fe0000 are all zeros.
But that bit 16 is based on DEN0028E related to smcccv1.3 which I think we are
not supporting now that's why should be 0 too.
But definitely some information about this bit should be useful.
Thanks,
Michal
--
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w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
External email: Use caution opening links or attachments
We are pleased to announce the release of the Trusted Firmware-A LTS version 2.8.0 [1]. To help with the verification and stability of the release, we also created side branches for Trusted Firmware-A Tests [2] and TF-A OpenCI Scripts/Jobs [3].
These went live on 13th February 2023. The trusted-firmware-a repository is now open again.
On behalf of the TF-A LTS project maintainers, I would like to thank the Trustedfirmware.org TF-A Project community for the support and guidance.
Notable features of the TF-A LTS Version 2.8.0 Release are as follows:
TF-A Project Repository
* Resolved issues
* Workarounds for the following CPU errata
* Cortex-A510 erratum 2684597
* Cortex-A710 erratum 2282622
* Cortex-A710 erratum 2768515
* Cortex-A78 erratum 2772019
* Cortex-A78 erratum 2779479
* Cortex-A78C erratum 2772121
* Cortex-X2 erratum 2282622
* Cortex-X2 erratum 2768515
* Cortex-X3 erratum 2615812
* Neoverse N2 erratum 2743089
* Neoverse V1 erratum 2743093
* Neoverse V1 errata 2779461
* Mitigations for the security advisory #10
* Critical bug fixes for the following platforms
* Arm/CSS
* Intel
* Layerscape
* LS1046a
* LX2
* NXP
* ST
Patch Statistics
* 35 Patches merged since v2.8 Nov 2022 release
Please refer to the TF-A LTS [1] changelog for the complete summary of changes.
[1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/docs/chang…
[2] tf-a-tests.git - Trusted Firmware-A Tests<https://git.trustedfirmware.org/TF-A%2Ftf-a-tests.git/log/?h=refs%2Fheads%2…>
[3] tf-a-ci-scripts.git - Trusted Firmware A (TF-A) CI scripts<https://git.trustedfirmware.org/ci%2Ftf-a-ci-scripts.git/log/?h=refs%2Fhead…>
[4] tf-a-job-configs.git - Trusted Firmware A (TF-A) Jenkins job configs<https://git.trustedfirmware.org/ci%2Ftf-a-job-configs.git/log/?h=refs%2Fhea…>
Hi all,
As you may know, the TF-A project historically used to make heavy use of
weak functions. The code base has numerous examples of them. However,
based on previous discussions, I think we have general consensus in the
TF-A community that the disadvantages of weak functions outweigh their
benefits and for this reason we should discourage introducing new ones.
In practice, I think this policy is already enforced most of the time in
code reviews but I've now posted a patch that makes it explicit in the
project's coding guidelines and provide the rationale behind it.
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19398
Note that TF-A maintainers would still be responsible for enforcing this
policy, as the CI system won't flag that for them, mainly because I
think there might be legitimate cases for weak functions in rare
instances so we'd get some false positives from such checks.
We (at Arm) have got plans to gradually convert existing weak functions
to strongly-defined implementations across the code base but this will
take time.
Like I said, I don't expect this change to be too controversial but
please raise any concerns you may have in this email thread or on Gerrit.
Best regards,
Sandrine
Hello,
As announced in the last Tech forum, the code freeze date for the LTS branch was Feb 3, 2023. We have now merged all the patches published on the wiki [1]. The branch is still locked, and all the CI test runs have now been completed. We are trying to root cause one test failure, though.
The RC0 tag was created today, and we request platform owners test the branch [2] on their downstream platforms if they wish.
We are still on track to release on Feb 10 and will publish more updates shortly.
Thanks.
[1] ⚡ LTS Tracking for v2.8.x (trustedfirmware.org)<https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdeveloper…>.
[2] trusted-firmware-a.git - Trusted Firmware for A profile Arm CPUs<https://git.trustedfirmware.org/TF-A%2Ftrusted-firmware-a.git/log/?h=refs%2…>
External email: Use caution opening links or attachments
Hello,
As announced in the last Tech forum, the code freeze date for the LTS branch is Feb 3, 2023. We have now locked the branch and won’t be accepting any more commits.
The list of the commits that will be merged into the LTS branch can be found at ⚡ LTS Tracking for v2.8.x (trustedfirmware.org)<https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdeveloper…>. If there are commits that we missed or that need to be in the LTS branch, please reach out to us.
We will post more updates shortly.
Thanks.
This event has been updated with a note:
"Updating the agenda for the TF-A Tech Forum session on Feb 9th 2023."
Changed: description
TF-A Tech Forum
Thursday Feb 9, 2023 ⋅ 4pm – 5pm
United Kingdom Time
Title: Firmware update support in the Trusted Services projectPresented by:
Julian HallA reference implementation of the Update Agent has recently been
added to Trusted Services. The implementation provides a toolbox of
reusable components for adding banked FWU support into firmware for
A-Profile devices. The implementation conforms to the Arm FWU-A
specification for compatibility with TF-A and other boot loaders that
recognise FWU-A metadata.===================================We run an open
technical forum call for anyone to participate and it is not restricted to
Trusted Firmware project members. It will operate under the guidance of the
TF TSC. Feel free to forward this invite to colleagues. Invites are via the
TF-A mailing list and also published on the Trusted Firmware
website. Details are
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Hello,
As announced in the last Tech forum, the code freeze date for the LTS branch is Feb 3, 2023. We have started shortlisting the patches for the lts-v2.8 branch.
These are the commits that will be merged into the LTS branch. More details can be found at ⚡ LTS Tracking for v2.8.x (trustedfirmware.org)<https://developer.trustedfirmware.org/w/tf_a/tf-a_lts_meeting_minutes/track…>
1. c7e698cfd fix(cpus): workaround for Cortex-X3 erratum 2615812
2. c45791b2f fix(layerscape): fix errata a008850
3. fa0105693 fix(nxp-ddr): use CDDWW for write to read delay
4. 00bb8c37e fix(nxp-ddr): apply Max CDD values for warm boot
5. 07d8e34fd fix(nxp-drivers): fix tzc380 memory regions config
6. c0c157a68 fix(ls1046a): 4 keys secureboot failure resolved
7. 50aa0ea7a fix(lx2): init global data before using it
8. 4daeaf341 fix(sptool): add dependency to SP image
9. 5fb6946ad fix(console): fix crash on spin_unlock with cache disabled
10. ff1d2ef38 fix(el3_runtime): restore SPSR/ELR/SCR after esb
11. c42402cdf fix(intel): fix fcs_client crashed when increased param size
12. 0ca1d8fba fix(layerscape): unlock write access SMMU_CBn_ACTLR
13. b87b02cf1 fix(cpus): workaround for Cortex-A710 erratum 2768515
14. 1cfde8222 fix(cpus): workaround for Cortex-X2 erratum 2768515
15. 377846b65 fix(st): include utils.h to solve compilation error
16. 1cbe42a51 fix(el3_runtime): allow SErrors when executing in EL3
17. 1ee7c8232 fix(cpus): workaround for Neoverse N2 erratum 2743089
18. b10afcce5 fix(cpus): workaround for Cortex-A78 erratum 2772019
19. 31747f057 fix(cpus): workaround for Neoverse V1 erratum 2743093
20. fd37982a1 fix(auth): forbid junk after extensions
21. 72460f50e fix(auth): require at least one extension to be present
22. 06c01b085 fix(libc): properly define SCHAR_MIN
23. 89d85ad0a fix(cpus): workaround for Cortex-A710 erratum 2282622
24. abb8f936f fix(auth): avoid out-of-bounds read in auth_nvctr()
25. f5c51855d fix(auth): properly validate X.509 extensions
26. f9c6301d7 fix(cpus): workaround for Cortex-X2 erratum 2282622
27. 60719e4e0 fix(plat/css): fix invalid redistributor poweroff
28. 00230e37e fix(cpus): workaround for Cortex-A78C erratum 2772121
29. aea4ccf8d fix(cpus): workaround for Cortex-A510 erratum 2684597
If there are commits that we missed or that need to be in the LTS branch, please reach out to us.
Thanks.
This event has been updated
Changed: description
TF-A Tech Forum
Thursday Jan 26, 2023 ⋅ 4pm – 5pm
United Kingdom Time
Apologies the LTS Update is for this week on 26th January at 4pm GMT Not
February session.=====Just a reminder that this week the TF-A Tech Forum is
covering a LTS Release update session from the primary maintainers of the
TF-A v2.8 LTS branch:Varun WadekarOkash Khawaja Bipin Ravi Thanks
AllJoanna========We run an open technical forum call for anyone to
participate and it is not restricted to Trusted Firmware project members.
It will operate under the guidance of the TF TSC. Feel free to forward this
invite to colleagues. Invites are via the TF-A mailing list and also
published on the Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
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This event has been updated
Changed: description
TF-A Tech Forum
Thursday Feb 23, 2023 ⋅ 4pm – 5pm
United Kingdom Time
Just a reminder that this week the TF-A Tech Forum is covering a LTS
Release update session from the primary maintainers of the TF-A v2.8 LTS
branch:Varun Wadekar <vwadekar(a)nvidia.com> Okash Khawaja
<okash(a)google.com> Bipin Ravi <Bipin.Ravi(a)arm.com>Thanks
AllJoanna===============================We run an open technical forum call
for anyone to participate and it is not restricted to Trusted Firmware
project members. It will operate under the guidance of the TF TSC. Feel
free to forward this invite to colleagues. Invites are via the TF-A mailing
list and also published on the Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap
mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US
(San Jose)Dial by your location +1 646 558 8656 US (New
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Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your
local number: https://zoom.us/u/ad27hc6t7h
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Hi All,
We are in the process of migrating from mbedtls-2.28 support to 3.3 support
we plan to deprecate mbedtls-2.28 support for TF-A 3.0 Release
but would retain support for both 2.28 and 3.3 for TF-A 2.9 lifetime.
There is draft implementation available[1] for code review
which cleanups and prepares for mbedtls-3.3 support but retaining backward
compatibility for mbedtls-2.28.
Please let us know if there any objections to deprecation of mbedtls-2.28 in
TF-A 3.0.
--
Thanks
Govindraj
[1]: https://review.trustedfirmware.org/q/topic:%2522mbedtls3.3_support%2522
<https://review.trustedfirmware.org/q/topic:%2522mbedtls3.3_support%2522>
Hi,
Happy new year!
For NVIDIA Tegra platforms, we need the capability to query the BL31 version (e.g. 2.7, 2.8, 2.8.x) from the NWd at runtime. I could not find an FID that returns this value.
I propose we introduce a new runtime service in bl31 that returns the version_string to the NWd to support this requirement.
Thoughts?
-Varun
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 382954: Concurrent data access violations (MISSING_LOCK)
/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c: 173 in spm_get_status_rc_cpu_buck_ldo()
________________________________________________________________________________________________________
*** CID 382954: Concurrent data access violations (MISSING_LOCK)
/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c: 173 in spm_get_status_rc_cpu_buck_ldo()
167 dest = (struct constraint_status *)st->value;
168 do {
169 if (dest == NULL) {
170 break;
171 }
172 if (st->type == CONSTRAINT_GET_VALID) {
>>> CID 382954: Concurrent data access violations (MISSING_LOCK)
>>> Accessing "dest->is_valid" without holding lock "spm_lock". Elsewhere, "constraint_status.is_valid" is accessed with "spm_lock" held 5 out of 6 times.
173 dest->is_valid = cpubuckldo_status;
174 } else if (st->type == CONSTRAINT_COND_BLOCK) {
175 dest->is_cond_block = 0;
176 } else if (st->type == CONSTRAINT_GET_ENTER_CNT) {
177 if (st->id == MT_RM_CONSTRAINT_ID_ALL) {
178 dest->enter_cnt += cpubuckldo_enter_cnt;
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
Hi,
The recent patch [1] for the OP-TEE Dispatcher in TF-A proposes a way
of post-boot loading OP-TEE by the Linux kernel with signature
verification in the normal world only. This has previously been
discussed in this mail thread [2] about half a year ago. Ultimately,
it was concluded that this should in principle be accepted upstream as
a platform choice to allow this or not. There are concerns that what
we have in upstream TF-A should serve as good examples, and trusting
the normal world to verify secure world software might not meet that
criterion. There are also concerns about adding signature verification
to BL31
Leaving the secure world wide open until the Linux kernel has been
able to successfully load and verify an OP-TEE binary seems very
risky. Even if it's claimed that the normal world can be trusted at
this point, we're still giving up a critical level of defense without
a good reason.
I've started to review [1], but it should not be accepted for merging
without support and approval from other maintainers.
I would like to explore other options in this mail thread. In [2] it
was suggested that a remnant of bl2 could be kept to verify OP-TEE
before starting to execute it. This could be taken one step further
and load a limited OP-TEE at boot which later is updated live, almost
like what's discussed in [3]. This should minimize the impact on TF-A
and also leave OP-TEE in charge of accepting an update instead of a
divided responsibility between the normal world and TF-A.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/18635
[2] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…
[3] https://github.com/OP-TEE/optee_os/issues/5699
Thanks,
Jens
Hello everyone,
A new security vulnerability has been identified in TF-A X.509 parser,
used for trusted boot in BL1 and BL2.
Please note that this vulnerability is *not* exploitable in TF-A
upstream code. Only downstream code might be affected under specific
circumstances.
The security advisory has been published in TF-A documentation and has
all the details:
https://trustedfirmware-a.readthedocs.io/en/latest/security_advisories/secu…
Patches to fix the identified bugs have already been merged in TF-A
tree. The advisory lists the relevant patches.
I would like to thank Demi Marie Obenour from Invisible Things Lab for
responsibly disclosing this security vulnerability to
TrustedFirmware.org, for providing patches to fix the identified bugs
and further harden the X.509 parser, for providing a detailed impact
analysis and for helping put this security advisory together.
Best regards,
Sandrine Bailleux, on behalf of TF-A security team.