Hi,

This is a proposal that introduces scheduling rules in TF-M. Introduction: On ArmV8-M CPUs, NSPE and SPE share the same physical processing element(PE). A TF-M enabled system need to be able to handle asynchronous events (interrupts) regardless of current security state of the PE; and that may lead to scheduling decisions. This introduces significant complexity into TF-M. To keep the integrity of (NSPE and SPE) schedulers and call paths between NSPE and SPE, following set of rules are imposed on the TF-M scheduler design. https://developer.trustedfirmware.org/w/tf_m/design/cooperative_scheduling/

Feedback welcome!

Thanks, Ashu