Hi Suresh, Anton,

This is an interesting topic :-) Armv8-M processors has some power management registers that can be restricted to Secure world access only. System Control Register (SCR) - Bit 2 SLEEPDEEP - 0 = Normal Sleep, 1 = Deep Sleep (this can also enable WIC feature). Access permission depends on SLEEPDEEPS. - Bit 3 SLEEPDEEPS - 0 - NS privileged world can r/w to SLEEPDEEP, 1 - SLEEPDEEP is RAZ/WI to NS privileged world (This is applicable to Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55)

Cortex-M55 also has Implementation defined power model control registers (CPDLPSTATE, DPDLPSTATE) https://developer.arm.com/documentation/101273/0101/Cortex-M55-Processor-lev... If TrustZone is used (AIRCR.BFHFNMINS is 0), then these registers are Secure privileged access only.

So definitely Secure firmware should provide some APIs for Non-secure software for changing the power control settings. However, I would expect that power control APIs would likely to be at a higher level which also manage other system level power control functions (which, as Anton said, device specific). In such case having APIs for modifying SLEEPDEEP and power model control registers is not helpful (or might even end up with confusions - e.g. if a SW developer trying to use both low level and high level APIs at the same time).

Given that a Secure firmware can setup SLEEPDEEPS easily if it wants to allow/disallow access to SLEEPDEEP control, having an API for this might be overkill. Access to Cortex-M55's power model control registers is more tricky. Would an 'optional' reference API for updating power model control registers (CPDLPSTATE, DPDLPSTATE) be considered?

Regards, Joseph

From: TF-M tf-m-bounces@lists.trustedfirmware.org On Behalf Of Anton Komlev via TF-M Sent: 20 December 2021 12:32 To: tf-m@lists.trustedfirmware.org Cc: nd nd@arm.com Subject: Re: [TF-M] Power management and TFM

Hi Suresh,

The power management is out of scope of TF-M core or any PSA service. Such functionality is HW platform specific and may vary depending on HW or SW adaptation capabilities. If you concern about a specific use case, where TF-M support is expected - let's discuss it here.

Hope that helps, Anton

From: TF-M <tf-m-bounces@lists.trustedfirmware.orgmailto:tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Suresh Marisetty via TF-M Sent: Friday, December 17, 2021 8:11 PM To: tf-m@lists.trustedfirmware.orgmailto:tf-m@lists.trustedfirmware.org Subject: [TF-M] Power management and TFM

Hi,

Wondering if anybody can throw some light on any ongoing efforts on power management on a system with TFM (deep sleep, etc).

thanks Suresh Marisetty Infineon Semiconductor Corporation CYSC CSS ICW SW SSE Mobile: +5103863997 Suresh.Marisetty@infineon.commailto:Suresh.Marisetty@infineon.com