Hi Raef,
I share the issue while applying shared patchset.
Because a variable 'dma_channel_amount' is used after the DMA wipe DTCM, it causes that dma_channel_amount have wrong data when waiting for DMA channel finish.
/* Configure all DMA channels to wipe the DTCM with the random value in parallel. */ for (int idx = 0; idx < dma_channel_amount; idx++) { /* DMA channel configuration to wipe DTCM*/ }
/* Wait for all the DMA channels to finish */ for (int idx = 0; idx < dma_channel_amount; idx++) { // Error occurs at here while ((*((volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x000)) & 0x1) != 0) {} }
So i have chosen a way that use defined value using #define like below.
/* Enable the TRAM */ *(volatile uint32_t *)(TRAM_BASE_S + 0x004) = 0x00000001;
/* Generate the TRAM erase random value */ tram_erase_value = *((volatile uint32_t *)(CC3XX_BASE_S + 0x124));
/* Configure all DMA channels to wipe the DTCM with the random value in parallel. */ for (int idx = 0; idx < DMA350_DMA0_CHANNEL_COUNT; idx++) { /* LINKADDR must be cleared because the command linking is used in DMA H/W boot. */ *(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x078) = 0x00000000; *(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x038) = tram_erase_value; *(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x02c) = 0x000F0044; *(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x018) = DTCM_CPU0_BASE_S + (DTCM_SIZE / DMA350_DMA0_CHANNEL_COUNT * idx);
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x030) = 0x00010000; *(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x020) = (DTCM_SIZE / sizeof(uint64_t) / DMA350_DMA0_CHANNEL_COUNT) << 16;
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x024) = 0x00000000; *(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x00c) = 0x01200603; *(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x008) = 0x00000000;
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x000) = 0x00000001; }
/* Wait for all the DMA channels to finish */ for (int idx = 0; idx < DMA350_DMA0_CHANNEL_COUNT; idx++) { while ((*((volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x100 * idx + 0x000)) & 0x1) != 0) {} }
Please refer to it.
Best Regards RH Kim ----- 원본 메시지 ----- 보낸 사람: Raef Coles <Raef.Coles@arm.com> 받는 사람: tf-m@lists.trustedfirmware.org <tf-m@lists.trustedfirmware.org>,김륜현 <winxp4333@adtek.co.kr> 날짜: 2025-07-28 22:06:49 제목: Re: [TF-M] Re: RSE booting with HardFault issue when TRAM enabled
Ah thanks for the testing - I had indeed reused a variable after the TRAM init but before the zero. The following patchset should fix it, and remove the unneeded DMA ICS commands
https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/41222/2 https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/41224/1
Thanks, Raef
________________________________________ From: 김륜현 via TF-M <tf-m@lists.trustedfirmware.org> Sent: 28 July 2025 12:57 To: Raef Coles; tf-m@lists.trustedfirmware.org Subject: [TF-M] Re: RSE booting with HardFault issue when TRAM enabled
OK, Thank you for sharing the plan.
About applying patch you gave,(https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/40838)
Using variables immediately after TRAM enable can cause bus errors due to the same reason we discussing.
/* Enable the TRAM */
*(volatile uint32_t *)(TRAM_BASE_S + 0x004) = 0x00000001;
In actual, the access to variables in DTCM occur bus error after TRAM enabled.
So i modified that it temporarily clear to 0 without using variable.
/* Enable the TRAM */
*(volatile uint32_t *)(TRAM_BASE_S + 0x004) = 0x00000001;
/* Erase the DTCM */
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x038) = 0; // FILLVAL
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x02c) = 0x000F0044; // DESTRANSCFG
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x018) = DTCM_CPU0_BASE_S; // DESADDR
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x030) = 0x00010000; // XADDRINC
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x020) = (DTCM_SIZE / sizeof(uint64_t)) << 16; // XSIZE
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x00c) = 0x1200603; // CONFIG
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x008) = 0x00000000; // Disable All Interrupt
*(volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x000) = 0x00000001; // RUN_CMD
while ((*((volatile uint32_t *)(DMA_350_BASE_S + 0x1000 + 0x000)) & 0x1) != 0) {}
But, it needs to find a fundamental solution.
Please check it and i will share the solution if we find good idea.
Best Regards
RH Kim
----- 원본 메시지 ----- 보낸 사람: Raef Coles <Raef.Coles@arm.com> 받는 사람: 김륜현 <winxp4333@adtek.co.kr>,tf-m@lists.trustedfirmware.org <tf-m@lists.trustedfirmware.org> 날짜: 2025-07-28 19:28:00 제목: Re: Re: [TF-M] RSE booting with HardFault issue when TRAM enabled
Yeah you're right, the patch does add some duplication. In future we plan to remove the commands to generate the TRAM key, set the TRAM key, initialize the TRAM and erase the TRAM from the DMA ICS. This way it will always be handled in SW.
The issue we have is that the TRAM setup requires retrieving random values from the TRNG, and whether that is possible in the DMA ICS depends on which HW TRNG is being used. With a single register read interface (which is what the ICS assumes) it works okay, but with (for example) the cryptocell TRNG it's not possible to read using the ICS since it requires a poll on a status register and it's not possible to encode that into a DMA command.
To avoid having some TRNGs using the ICS and some using SW, we figured it was more sensible to perform the TRAM setup in SW in all cases.
I believe that the new SW flow _should_ work if the DMA flow has already been run, but if there are any issues (likely with the KMU keyslot) then the simplest solution is to just remove the DMA commands.
Raef
________________________________________ From: 김륜현 <winxp4333@adtek.co.kr> Sent: 28 July 2025 02:00 To: Raef Coles; tf-m@lists.trustedfirmware.org Subject: Re: Re: [TF-M] RSE booting with HardFault issue when TRAM enabled
Hi Raef
Thanks for your answer.
I'm trying to apply your patch our base code, but some of issue occur.
I will share the result when the patch is applied properly.
Before that, i have a question.
As i know, DMA descriptor(Program6) enables TRAM on DMA H/W boot.
(platform/ext/target/arm/rse/common/bl1/scripts)
I think that it seems to do duplicate operation as S/W about enabling TRAM.
Regarding this, is there still no fixed method for enabling TRAM?
Best Regards
RH Kim
----- 원본 메시지 ----- 보낸 사람: Raef Coles <Raef.Coles@arm.com> 받는 사람: tf-m@lists.trustedfirmware.org <tf-m@lists.trustedfirmware.org>,김륜현 <winxp4333@adtek.co.kr> 날짜: 2025-07-24 21:00:22 제목: Re: [TF-M] RSE booting with HardFault issue when TRAM enabled
Hey RH
Apologies, this has been a known issue for a while (or rather, a series of known issues that we keep fixing).
We've just merged a patch upstream which: * Replaces the function calls with fixed register writes to avoid issues with uninitialized global data * Performs DTCM initialization in all cases, avoiding relying on the DMA ICS or having to check the SP mode
You can find it here https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/40838
Unfortunately we've only been able to test it on the FVP at the moment, which has limited ECC support. If you'd be able to test the patch and let me know if it fixes your issue, that would be appreciated.
Raef
________________________________________ From: 김륜현 via TF-M <tf-m@lists.trustedfirmware.org> Sent: 24 July 2025 05:38 To: tf-m@lists.trustedfirmware.org Subject: [TF-M] RSE booting with HardFault issue when TRAM enabled
Dear TF-M developers
Hello, i'm developing and porting TF-M our platforms based on RDV3R1.
To enable TRAM, i modified a cmake config file like below(platform/ext/target/arm/rse/common/config.cmake)
- set(RSE_ENABLE_TRAM OFF CACHE BOOL "Whether TRAM encryption is enabled")
+ set(RSE_ENABLE_TRAM ON CACHE BOOL "Whether TRAM encryption is enabled")
First of all, RSE core boots with Virgin CM
In this mode, Secure Provisioning is not enabled so that the DTCM don't be initialized even if TRAM is enabled.
setup_tram_encryption()@startup_rse_bl1_1.c
tram_enable_encryption(&tram_dev_s);
if (sp_enabled == LCM_TRUE && (lcs == LCM_LCS_CM || lcs == LCM_LCS_DM)) {
bl1_trng_generate_random((uint8_t *)&random_word, sizeof(random_word));
for (idx = 0; idx < DTCM_SIZE / sizeof(uint32_t); idx++) {
((uint32_t *)DTCM_BASE_S)[idx] = random_word;
}
}
Because DTCM doesn't be initialized, the next codes which use global variable in BL1_1 data section on DTCM cause hardfault.
So, i applied the workaround by modifying condition like below.
tram_enable_encryption(&tram_dev_s);
- if (sp_enabled == LCM_TRUE && (lcs == LCM_LCS_CM || lcs == LCM_LCS_DM)) {
+ if ((lcs == LCM_LCS_CM || lcs == LCM_LCS_DM)) {
bl1_trng_generate_random((uint8_t *)&random_word, sizeof(random_word));
for (idx = 0; idx < DTCM_SIZE / sizeof(uint32_t); idx++) {
((uint32_t *)DTCM_BASE_S)[idx] = random_word;
}
}
But the global variable in uninitialized DTCM are also used in bl1_trng_generate_random().
So, i tried to initialize DTCM as 0 without calling bl1_trng_generate_random().
But after that, setting SP_ENABLED for CM Provisioning causes warm reset, TRAM is disabled but DTCM doesn't be initialized.
It causes same problem.
I know that enabling TRAM is performed DMA descriptor without RSE_ENABLE_TRAM option, it may also cause the problem because of the phenomenon that TRAM is disabled but DTCM doesn't be initialized when warm reset.
Should i modify let it use local variable? or is there anything to fix this problem?
Best Regards
RH Kim