- TF-M - lists.trustedfirmware.org

[Core Patch] Core: switch signal wait object to 'condition'

by Ken Liu (Arm Technology China)

Hi, I will update the wait object from 'event' to 'condition'. This is mainly for fixing the issue: https://developer.trustedfirmware.org/T273 'event' is actually a depth 1 semaphore, which is not good enough for signals synching case. Involve a simpler sync object 'condition' for signals (and client ACKs): https://review.trustedfirmware.org/c/trusted-firmware-m/+/712 Please help to check if you are interested in it. Thanks -Ken

6 years, 7 months

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Re: [TF-M] [EXTERNAL] Branches merging from 'feature-ipc' to 'master' is happening

by Ken Liu (Arm Technology China)

Hi Alan, Expected to be merged before end of Mar 13th if there is no more raised concern ;) -Ken > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, > Alan via TF-M > Sent: Tuesday, March 12, 2019 11:27 AM > To: tf-m(a)lists.trustedfirmware.org > Subject: Re: [TF-M] [EXTERNAL] Branches merging from 'feature-ipc' to 'master' > is happening > > Yay! When? > > > On Mar 11, 2019, at 6:57 PM, Ken Liu (Arm Technology China) via TF-M <tf- > m(a)lists.trustedfirmware.org> wrote: > > > > Hi TF-M Subscribers, > > The branch 'feature-ipc' is going to be merged into 'master', and here is the > patch: > > https://review.trustedfirmware.org/c/trusted-firmware-m/+/677 > > > > After the merging, the IPC feature will be available in the 'master' branch, > future updates on the IPC part will happen in 'master' branch, too. > > For those patches pushed towards 'feature-ipc' will be reviewed and we > suggest push new patchset to 'master' branch. > > > > Please reply to this thread without hesitation if there are any questions. > > > > Thanks. > > > > -Ken > > -- > > TF-M mailing list > > TF-M(a)lists.trustedfirmware.org > > https://lists.trustedfirmware.org/mailman/listinfo/tf-m > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 7 months

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Re: [TF-M] [EXTERNAL] Branches merging from 'feature-ipc' to 'master' is happening

by DeMars, Alan

Yay! When? > On Mar 11, 2019, at 6:57 PM, Ken Liu (Arm Technology China) via TF-M <tf-m(a)lists.trustedfirmware.org> wrote: > > Hi TF-M Subscribers, > The branch 'feature-ipc' is going to be merged into 'master', and here is the patch: > https://review.trustedfirmware.org/c/trusted-firmware-m/+/677 > > After the merging, the IPC feature will be available in the 'master' branch, future updates on the IPC part will happen in 'master' branch, too. > For those patches pushed towards 'feature-ipc' will be reviewed and we suggest push new patchset to 'master' branch. > > Please reply to this thread without hesitation if there are any questions. > > Thanks. > > -Ken > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 7 months

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Branches merging from 'feature-ipc' to 'master' is happening

by Ken Liu (Arm Technology China)

Hi TF-M Subscribers, The branch 'feature-ipc' is going to be merged into 'master', and here is the patch: https://review.trustedfirmware.org/c/trusted-firmware-m/+/677 After the merging, the IPC feature will be available in the 'master' branch, future updates on the IPC part will happen in 'master' branch, too. For those patches pushed towards 'feature-ipc' will be reviewed and we suggest push new patchset to 'master' branch. Please reply to this thread without hesitation if there are any questions. Thanks. -Ken

6 years, 7 months

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TF-M v1.0-Beta Blog

by Shebu Varghese Kuriakose

Hi, Here is a blog on the recent TF-M tag v1.0-Beta and how it enables PSA certification https://www.trustedfirmware.org/blog/Trusted-Firmware-M-v10-Beta-Enabling-P… Regards, Shebu

6 years, 7 months

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Re: [TF-M] Trusted boot - rollback protection

by David Brown

On Mon, Mar 11, 2019 at 01:43:19PM +0000, Tamas Ban via TF-M wrote: >https://developer.trustedfirmware.org/w/tf_m/design/trusted_boot/rollback_p… Oh, and a little terminology comment about the Trusted non-volatile (NV) counters. This section should use "increase" and "decrease" not "increment" and "decrement". There is no requirement that the counter only be incremented (having 1 added to the value), only that it be set to a larger value than the current value. You should probably also add a discussion as to how testing will be done with a HW security counter. Again, my suggestion is to not add an additional counter, but just use the existing version field (minus the build number) as the security counter value. David

6 years, 7 months

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Trusted boot - rollback protection

by Tamas Ban

Hi all, Please see the following link for a design proposal on anti-rollback protection in trusted boot: https://developer.trustedfirmware.org/w/tf_m/design/trusted_boot/rollback_p… Comments are welcome! Regards Tamas Ban

6 years, 7 months

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Re: [TF-M] multiple services within the same SP

by Andrew Thoelke

Hi Alan, I can answer this from the PSA Firmware Framework specification point of view, Ken (or others in the TF-M team) can clarify how closely the TF-M behaviour matches this. In the manifest each service has a "signal" attribute which is a C identifier that is given the signal value for that service. The value is allocated by the TF-M tools and should be available to the SP source code via a generated header file - the specification places these definitions in the psa_manifest/<manifestfilename>.h header file, matching the name of the manifest file itself. When the SP receives a set of signals from psa_wait(), it can identify which signals are asserted using these identifiers to test the signal bits. The example RoT Service in Appendix D of the PSA Firmware Framework demonstrates this. Regards, Andrew -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 08 March 2019 13:52 To: tf-m(a)lists.trustedfirmware.org Subject: [TF-M] multiple services within the same SP In a multi-service SP, how does the SP know which SID has been used to connect to it? -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years, 7 months

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Re: [TF-M] multiple services within the same SP

by Ken Liu (Arm Technology China)

Hi Alan, Services are listed in SP. SPM could enumerate the services in a SP by the list. You can check the member variable ' service_list' of ' tfm_spm_ipc_partition_t' to know details. -Ken > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, > Alan via TF-M > Sent: Friday, March 8, 2019 9:52 PM > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] multiple services within the same SP > > In a multi-service SP, how does the SP know which SID has been used to connect > to it? > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years, 7 months

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multiple services within the same SP

by DeMars, Alan

In a multi-service SP, how does the SP know which SID has been used to connect to it?

6 years, 7 months

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Re: [TF-M] META: TF-M Mailing list configuration

by Bill Fletcher

Hi David, Thanks for raising this. I'll contact you directly to review the Mailman configuration. Regards Bill On Thu, 28 Feb 2019, 05:04 David Brown via TF-M, < tf-m(a)lists.trustedfirmware.org> wrote: > I have noticed that this mailing list seems to be configured in a > non-ideal way. > > Primarily, the messages are sent from the list address itself, and a > reply-to header is inserted for the original sender. This at least > often will allow someone to reply to the original sender. > > There are a few problems with this. One is that this tends to break > messages that have been copied to more than one list, especially for > recipients who subscribe to both lists. Admittedly it is better than > the all-to-common practice of setting Reply-to to the list itself, > which effectively steals all replies from any other recipients or > lists that were originally included. > > Secondly, however, this kind of violates the intent of the reply-to > field, which was intended for the originator of the message to be able > to give an alternative address they wish for replies to go to. > > I don't know how this list is hosted, and usually this kind of > configuration results from an ISP that rejects messages. But, I know > a lot of mailing lists are managed with mailman without these > problems, so it should be possible to get this working in a more > homogenous way. > > Lists admins, feel free to contact me if you want any assistance in > trying to configure the list better. > > Thanks, > David > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m >

6 years, 8 months

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META: TF-M Mailing list configuration

by David Brown

I have noticed that this mailing list seems to be configured in a non-ideal way. Primarily, the messages are sent from the list address itself, and a reply-to header is inserted for the original sender. This at least often will allow someone to reply to the original sender. There are a few problems with this. One is that this tends to break messages that have been copied to more than one list, especially for recipients who subscribe to both lists. Admittedly it is better than the all-to-common practice of setting Reply-to to the list itself, which effectively steals all replies from any other recipients or lists that were originally included. Secondly, however, this kind of violates the intent of the reply-to field, which was intended for the originator of the message to be able to give an alternative address they wish for replies to go to. I don't know how this list is hosted, and usually this kind of configuration results from an ISP that rejects messages. But, I know a lot of mailing lists are managed with mailman without these problems, so it should be possible to get this working in a more homogenous way. Lists admins, feel free to contact me if you want any assistance in trying to configure the list better. Thanks, David

6 years, 8 months

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Re: [TF-M] SecureFault when starting the OS

by Antonio De Angelis

Hi Thomas, Thanks for the feedback. An additional question from me to understand better the issue: are you rebuilding RTX from source, not using the pre-built binaries distributed with CMSIS_5? Since this commit: https://github.com/ARM-software/CMSIS_5/commit/8bce76b03565359f31cd20ed86c2… CMSIS_5 has changed from using __DOMAIN_NS to DOMAIN_NS macro for better MISRA compliance. I think to officially support newer releases of CMSIS, we should update our instructions and define DOMAIN_NS in addition to __DOMAIN_NS, as this define will come into picture for integrations which actually rebuild RTX from the CMSIS_5 repo sources. Thanks, Antonio -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M Sent: 26 February 2019 09:58 To: tf-m(a)lists.trustedfirmware.org Subject: Re: [TF-M] SecureFault when starting the OS Thanks Miklos and Antonio, You were both spot on. Turned out I had not define DOMAIN_NS=1, which change the last byte from FD to BC. I need to figure out why I need to add that when the documentation says __DOMAIN_NS=1 should be sufficient. Cheers, /Thomas Den 2019-02-25 kl. 17:13, skrev Antonio De Angelis via TF-M: > Hi Thomas, > > As you correctly identified, the value of the EXC_RETURN is not appropriate for the state the exception was taken from. As a quick double check, you can set it manually from a debugger to 0xFFFFFFBC before the exception return takes place and in that case the exception return will happen correctly. You can find more details on the meaning of each bit of the EXC_RETURN register at the following link: https://static.docs.arm.com/100701/0100/armv8_m_processor_exception_handlin… (section 1.10). > > In general, once TF-M has finished booting and has jumped to the NS state, the OS initialisation should take place (you can see as an example in the NS app how the RTX kernel initialisation happens). If the OS manipulates directly the Link Register, it needs to be aware that it's running from the NS state (this can imply a build time configuration step) so that it will set up correctly the default value of the EXC_RETURN when an exception happens. You can find more details in docs/user_guides/os_migration_guide_armv8m.md . > > Thanks, > Antonio > > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of > Thomas Törnblom via TF-M > Sent: 25 February 2019 15:34 > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] SecureFault when starting the OS > > In my work to port TF-M to IAR EWARM I have now gotten the MPC set up so that the startup will properly switch to the NS code. > > I'm now running into an issue where I get a SecureFault when attempting to start the OS. > > The idle and timer threads have been configured and the timer thread has been put on run.curr and SVC_Exit issues a BX LR, which results in a SecureFault. > > SFSR indicates that it is an INVER (Invalid Exception Return): > --- > Invalid exception return flag. This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state. The possible values of this bit are: > 0 Error has not occurred. > 1 Error has occurred. > -- > > LR was 0xfffffffd (DCRS=1, ES=1) and the security bit was cleared, so it appears to be the second condition that triggered the exception. > > What am I missing here? > > Is the OS supposed to be started from NS mode? > > I am still using the ARM.TFM.1.1.0, ARM.Musca_A1_BSP.2.0.0, > ARM.mbedTLS.1.3.1 and ARM.CMSIS.5.5.0-dev2 packs. > > Thanks, > /Thomas > > > *Thomas Törnblom*, /Product Engineer/ > IAR Systems AB > Box 23051, Strandbodgatan 1 > SE-750 23 Uppsala, SWEDEN > Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 > E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> > Website: www.iar.com <http://www.iar.com> > Twitter: www.twitter.com/iarsystems > <http://www.twitter.com/iarsystems> > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems> -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] SecureFault when starting the OS

by Thomas Törnblom

Thanks Miklos and Antonio, You were both spot on. Turned out I had not define DOMAIN_NS=1, which change the last byte from FD to BC. I need to figure out why I need to add that when the documentation says __DOMAIN_NS=1 should be sufficient. Cheers, /Thomas Den 2019-02-25 kl. 17:13, skrev Antonio De Angelis via TF-M: > Hi Thomas, > > As you correctly identified, the value of the EXC_RETURN is not appropriate for the state the exception was taken from. As a quick double check, you can set it manually from a debugger to 0xFFFFFFBC before the exception return takes place and in that case the exception return will happen correctly. You can find more details on the meaning of each bit of the EXC_RETURN register at the following link: https://static.docs.arm.com/100701/0100/armv8_m_processor_exception_handlin… (section 1.10). > > In general, once TF-M has finished booting and has jumped to the NS state, the OS initialisation should take place (you can see as an example in the NS app how the RTX kernel initialisation happens). If the OS manipulates directly the Link Register, it needs to be aware that it's running from the NS state (this can imply a build time configuration step) so that it will set up correctly the default value of the EXC_RETURN when an exception happens. You can find more details in docs/user_guides/os_migration_guide_armv8m.md . > > Thanks, > Antonio > > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M > Sent: 25 February 2019 15:34 > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] SecureFault when starting the OS > > In my work to port TF-M to IAR EWARM I have now gotten the MPC set up so that the startup will properly switch to the NS code. > > I'm now running into an issue where I get a SecureFault when attempting to start the OS. > > The idle and timer threads have been configured and the timer thread has been put on run.curr and SVC_Exit issues a BX LR, which results in a SecureFault. > > SFSR indicates that it is an INVER (Invalid Exception Return): > --- > Invalid exception return flag. This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state. The possible values of this bit are: > 0 Error has not occurred. > 1 Error has occurred. > -- > > LR was 0xfffffffd (DCRS=1, ES=1) and the security bit was cleared, so it appears to be the second condition that triggered the exception. > > What am I missing here? > > Is the OS supposed to be started from NS mode? > > I am still using the ARM.TFM.1.1.0, ARM.Musca_A1_BSP.2.0.0, > ARM.mbedTLS.1.3.1 and ARM.CMSIS.5.5.0-dev2 packs. > > Thanks, > /Thomas > > > *Thomas Törnblom*, /Product Engineer/ > IAR Systems AB > Box 23051, Strandbodgatan 1 > SE-750 23 Uppsala, SWEDEN > Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 > E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> > Website: www.iar.com <http://www.iar.com> > Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems> > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>

6 years, 8 months

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Re: [TF-M] SecureFault when starting the OS

by Antonio De Angelis

Hi Thomas, As you correctly identified, the value of the EXC_RETURN is not appropriate for the state the exception was taken from. As a quick double check, you can set it manually from a debugger to 0xFFFFFFBC before the exception return takes place and in that case the exception return will happen correctly. You can find more details on the meaning of each bit of the EXC_RETURN register at the following link: https://static.docs.arm.com/100701/0100/armv8_m_processor_exception_handlin… (section 1.10). In general, once TF-M has finished booting and has jumped to the NS state, the OS initialisation should take place (you can see as an example in the NS app how the RTX kernel initialisation happens). If the OS manipulates directly the Link Register, it needs to be aware that it's running from the NS state (this can imply a build time configuration step) so that it will set up correctly the default value of the EXC_RETURN when an exception happens. You can find more details in docs/user_guides/os_migration_guide_armv8m.md . Thanks, Antonio -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M Sent: 25 February 2019 15:34 To: tf-m(a)lists.trustedfirmware.org Subject: [TF-M] SecureFault when starting the OS In my work to port TF-M to IAR EWARM I have now gotten the MPC set up so that the startup will properly switch to the NS code. I'm now running into an issue where I get a SecureFault when attempting to start the OS. The idle and timer threads have been configured and the timer thread has been put on run.curr and SVC_Exit issues a BX LR, which results in a SecureFault. SFSR indicates that it is an INVER (Invalid Exception Return): --- Invalid exception return flag. This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state. The possible values of this bit are: 0 Error has not occurred. 1 Error has occurred. -- LR was 0xfffffffd (DCRS=1, ES=1) and the security bit was cleared, so it appears to be the second condition that triggered the exception. What am I missing here? Is the OS supposed to be started from NS mode? I am still using the ARM.TFM.1.1.0, ARM.Musca_A1_BSP.2.0.0, ARM.mbedTLS.1.3.1 and ARM.CMSIS.5.5.0-dev2 packs. Thanks, /Thomas *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems> -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years, 8 months

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Re: [TF-M] SecureFault when starting the OS

by Miklos Balint

Hi Thomas, According to TF-M's design, an RTOS is meant to be started/run in NS. If a non-secure SVC handler is called from thread mode (PSP, no FP, default stacking), the value of LR should be 0xFFFF_FFBC on exception entry. In my experience some v7-M RTOS implementations don't save the EXC_RETURN value on SVC entry but have a default value hard-coded at SVC exit. In a v7-M system the default EXC_RETURN value (assuming no SVC from handlers, and PSP used for thread mode) would be 0xFFFF_FFFD as you describe below, but that's not the case for a NS RTOS in v8-M. (The two bits that are different are EXC_RETURN.S (bit [6]) to indicate NS stack, and EXC_RETURN.ES (bit [0]) to indicate that the Exception was taken to NS) A recommended and future-proof solution is for the RTOS to save the EXC_RETURN value stored in LR on SVC entry, and when returning from the SVC, to restore that and branch, or, if a switch is needed from MSP to PSP, to set EXC_RETURN.SPSEL as needed, but leave the rest of the EXC_RETURN value unchanged. Let me know if this helps, or please provide further details if I failed to catch the root cause. Regards Miklos -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M Sent: 25 February 2019 16:34 To: tf-m(a)lists.trustedfirmware.org Subject: [TF-M] SecureFault when starting the OS In my work to port TF-M to IAR EWARM I have now gotten the MPC set up so that the startup will properly switch to the NS code. I'm now running into an issue where I get a SecureFault when attempting to start the OS. The idle and timer threads have been configured and the timer thread has been put on run.curr and SVC_Exit issues a BX LR, which results in a SecureFault. SFSR indicates that it is an INVER (Invalid Exception Return): --- Invalid exception return flag. This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state. The possible values of this bit are: 0 Error has not occurred. 1 Error has occurred. -- LR was 0xfffffffd (DCRS=1, ES=1) and the security bit was cleared, so it appears to be the second condition that triggered the exception. What am I missing here? Is the OS supposed to be started from NS mode? I am still using the ARM.TFM.1.1.0, ARM.Musca_A1_BSP.2.0.0, ARM.mbedTLS.1.3.1 and ARM.CMSIS.5.5.0-dev2 packs. Thanks, /Thomas *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems> -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years, 8 months

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SecureFault when starting the OS

by Thomas Törnblom

In my work to port TF-M to IAR EWARM I have now gotten the MPC set up so that the startup will properly switch to the NS code. I'm now running into an issue where I get a SecureFault when attempting to start the OS. The idle and timer threads have been configured and the timer thread has been put on run.curr and SVC_Exit issues a BX LR, which results in a SecureFault. SFSR indicates that it is an INVER (Invalid Exception Return): --- Invalid exception return flag. This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state. The possible values of this bit are: 0 Error has not occurred. 1 Error has occurred. -- LR was 0xfffffffd (DCRS=1, ES=1) and the security bit was cleared, so it appears to be the second condition that triggered the exception. What am I missing here? Is the OS supposed to be started from NS mode? I am still using the ARM.TFM.1.1.0, ARM.Musca_A1_BSP.2.0.0, ARM.mbedTLS.1.3.1 and ARM.CMSIS.5.5.0-dev2 packs. Thanks, /Thomas *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>

6 years, 8 months

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Some comments on twincpu mailbox design

by David Hu (Arm Technology China)

Hi Danny, Could you please check my comments on [Mailbox design](https://developer.trustedfirmware.org/w/tf_m/design/twin-cpu/mailbo… in below? I’d like to discuss about some high-level designs at the very first time. We can discuss about details later. 😊 1. As designed in Concepts section, secure core has a single dispatcher thread, which is the main thread on the secure core. AFAIK, there is no such main thread in current TF-M Inter-Process Communication model implementation. Do you mind taking a look at the section "Interaction in thread model" in our [TF-M presentation](https://events.linuxfoundation.org/wp-content/uploads/2017/12… On the other hand, implementing a dedicated thread in TF-M to handling the mailbox events can be a solution. But it might also bring some difficulties in implementation. I'd like to discuss in detail with Transport Layer together. 2. I like the concept of mailbox event. One of the key points is, after the information carried via mailbox arrives in TF-M, how to deliver it to TF-M core. We can have further discussions on the details. 3. PSA Firmware Framework specifies the parameters and return value for PSA Client APIs. Do you think if it is necessary to cover the mailbox message structure containing information of parameters and return value in mailbox design? Thank you. Best regards, Hu Ziji

6 years, 8 months

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Re: [TF-M] What is the behavior of SPM between `TZ_StoreContext_S()` and `TZ_LoadContext_S()`

by Ken Liu (Arm Technology China)

Hi Alan, From my point of view, TZ_StoreContext_S() indicates the non-secure thread accesses secure service is getting switching out, no one should access secure services before a calling of TZ_LoadContext_S(). This case could be covered in below condition in PSA FF client APIs (Picked on line from page 49 of PSA FF 1.0 beta0): "Calling psa_connect() is a fatal error and will not return if any of the following conditions are met: * ... * The caller is not authorized to access the RoT Service, see RoT Service access control on page 28. * ..." Pining the calling non-secure thread is the proper way - which means, 'Does not return' to the non-secure thread in this case. There should be no such an API to peek the status of SPM from caller out of SPM. And there should be a similar API for SPM (only) to retrieve the current MemoryID (or information could be represented as MemoryID). BR -Ken > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, > Alan via TF-M > Sent: Thursday, February 21, 2019 10:54 PM > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] What is the behavior of SPM between `TZ_StoreContext_S()` and > `TZ_LoadContext_S()` > > Are calls to psa_connect/call/close allowed after `TZ_StoreContext_S()` has > been called but before `TZ_LoadContext_S()` is called? If not, does that result in > a panic or simply error return codes? > > Is there a secure-side SPM API that can be invoked from a custom veneer > function to determine if the SPM is in the zone between `TZ_StoreContext_S()` > and `TZ_LoadContext_S()`? > > Is there an API that returns the current MemoryId? > > Alan > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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What is the behavior of SPM between `TZ_StoreContext_S()` and `TZ_LoadContext_S()`

by DeMars, Alan

Are calls to psa_connect/call/close allowed after `TZ_StoreContext_S()` has been called but before `TZ_LoadContext_S()` is called? If not, does that result in a panic or simply error return codes? Is there a secure-side SPM API that can be invoked from a custom veneer function to determine if the SPM is in the zone between `TZ_StoreContext_S()` and `TZ_LoadContext_S()`? Is there an API that returns the current MemoryId? Alan

6 years, 8 months

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Re: [TF-M] Musca-A SAU setup issues

by Mate Toth-Pal

Hi Thomas, (The code snippets are from the commit with hash 5c1756fbab6097f5688583d11dea5d1271d2d774 on https://review.trustedfirmware.org . I only added some comments at certain points) This symptom is usually caused by a misconfigured MPC. The MPC initialisation is also called from platform\ext\target\musca_a\spm_hal.c: ---------- 8< ---------- void tfm_spm_hal_init_isolation_hw(void) { /* Configures non-secure memory spaces in the target */ sau_and_idau_cfg(); mpc_init_cfg(); /* <- initialise MPC */ ppc_init_cfg(); } ---------- >8 ---------- Looking at mpc_init_cfg: ---------- 8< ---------- void mpc_init_cfg(void) { /* ... */ Driver_QSPI_MPC.Initialize(); Driver_QSPI_MPC.ConfigRegion(memory_regions.non_secure_partition_base, memory_regions.non_secure_partition_limit, ARM_MPC_ATTR_NONSECURE); /* ... */ /* Lock down the MPC configuration */ Driver_QSPI_MPC.LockDown(); /* ... */ /* Add barriers to assure the MPC configuration is done before continue * the execution. */ __DSB(); __ISB(); } ---------- 8< ---------- It is possible to change the MPC behaviour, to raise a bus fault on invalid access instead of the RAZ/WI behaviour, by setting the CFG_SEC_RESP bit in the MPC's control register. You should do something like this after Driver_QSPI_MPC initialisation (see https://developer.arm.com/products/architecture/cpu-architecture/m-profile/… ): ---------- 8< ---------- uint32_t mpc_ctrl; Driver_QSPI_MPC.GetCtrlConfig(&mpc_ctrl); Driver_QSPI_MPC.SetCtrlConfig(mpc_ctrl | 0x10); ---------- 8< ---------- If you don't get the bus fault after this, further troubleshooting is needed. Regards, Mate -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M Sent: 15 February 2019 15:57 To: tf-m(a)lists.trustedfirmware.org Subject: [TF-M] Musca-A SAU setup issues I am working on porting TF-M to the IAR Embedded Workbench for ARM (EWARM) toolchain and I'm having some issues getting it to start properly. I started out using the ARM.TFM.1.1.0, ARM.Musca_A1_BSP.2.0.0, ARM.mbedTLS.1.3.1 and ARM.CMSIS.5.5.0-dev2 CMSIS packs and I've had to fix things in all of the packs to make the project build with our compiler, some things just to add our tools, some things that were just gcc:isms that are non standard-C. The TF-M code is based on a snapshot of https://git.trustedfirmware.org/trusted-firmware-m.git repository of the following hash: 5c1756fbab6097f5688583d11dea5d1271d2d774 I know that some of these packs are old and I'm also working on a port of the bits on trustedfirmware.org, but I would like to bring the old version up first. The (current) issue I have is that the NS code region becomes inaccessible from the secure part after setting the SAU up and I assume I am missing something. in tfm_core_init() there are calls to: --- tfm_spm_hal_init_isolation_hw(); configure_ns_code(); --- tfm_spm_hal_init_isolation_hw() calls sau_and_idau_cfg(), which sets up: --- /* Configures SAU regions to be non-secure */ SAU->RNR = TFM_NS_REGION_CODE; SAU->RBAR = (memory_regions.non_secure_partition_base & SAU_RBAR_BADDR_Msk); SAU->RLAR = (memory_regions.non_secure_partition_limit & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; --- After this piece is run, the NS vector table becomes all zeros when viewed from secure mode. This causes the configure_ns_code() call above to fail to pick up the ns_msp and ns_entry addresses, they become 0. If I swap the calls around so they become: --- configure_ns_code(); tfm_spm_hal_init_isolation_hw(); --- then ns_msp and ns_entry are picked up OK. How is this supposed to work? When the SAU is setup I get RAZ/WI when accessing NS memory from S mode, the other way around results is a security violation, which is properly handled by the SecureFault_Handler(). What am I missing? I run into other problems later, but that may very well a consequence of earlier issues. Thanks, /Thomas -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems> -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] SYSTICK ownership

by DeMars, Alan

My concern was the value one would provide for the "line_num" field within the manifest. The SYSTICK uses vector 15 which I believe would correspond to "line_num" = -1. I'm not sure the design accommodates negative line_nums. Also, disabling the SYSTICK interrupt while servicing its interrupt can't be handled in the normal way user IRQs are disabled. Special case code would be required in the SPM to support the SYSTICK as a secure partition interrupt. Alan -----Original Message----- From: TF-M [mailto:tf-m-bounces@lists.trustedfirmware.org] On Behalf Of Ken Liu (Arm Technology China) via TF-M Sent: Monday, February 18, 2019 5:34 PM To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: [EXTERNAL] Re: [TF-M] SYSTICK ownership Hi Alan, From your description, it looks like you want to use secure SYSTICK as an interrupt for Secure Partition, is this correct? In this case, it is similar to the secure interrupt usage. Since the interrupt handling is under developing, I will add a note in the task to remind how we could add SYSTICK as an interrupt in the manifest. BR -Ken > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, > Alan via TF-M > Sent: Saturday, February 16, 2019 7:02 AM > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] SYSTICK ownership > > If not used anywhere else, can a Secure Partition own the secure SYSTICK timer > and its interrupt? > If so, how is it specified in the SP manifest? > > Alan > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] SYSTICK ownership

by Ken Liu (Arm Technology China)

Hi Alan, From your description, it looks like you want to use secure SYSTICK as an interrupt for Secure Partition, is this correct? In this case, it is similar to the secure interrupt usage. Since the interrupt handling is under developing, I will add a note in the task to remind how we could add SYSTICK as an interrupt in the manifest. BR -Ken > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, > Alan via TF-M > Sent: Saturday, February 16, 2019 7:02 AM > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] SYSTICK ownership > > If not used anywhere else, can a Secure Partition own the secure SYSTICK timer > and its interrupt? > If so, how is it specified in the SP manifest? > > Alan > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] interrupts not supported on feature-ipc branch?

by DeMars, Alan

Thanks! I'll check back. -----Original Message----- From: TF-M [mailto:tf-m-bounces@lists.trustedfirmware.org] On Behalf Of Ken Liu (Arm Technology China) via TF-M Sent: Monday, February 18, 2019 5:16 PM To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: [EXTERNAL] Re: [TF-M] interrupts not supported on feature-ipc branch? Hi Alan, There would be a merge to master in recent days; so master branch will support PSA IPC soon. The interrupts for IPC is under developing, you can check the roadmap to know the plan. Thanks. -Ken > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, > Alan via TF-M > Sent: Saturday, February 16, 2019 7:37 AM > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] interrupts not supported on feature-ipc branch? > > I guess interrupts are only supported on the master branch. > > When will the master branch support PSA IPC? > > Or, when will the feature-ipc branch support interrupts? > > Alan > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] interrupts not supported on feature-ipc branch?

by Ken Liu (Arm Technology China)

Hi Alan, There would be a merge to master in recent days; so master branch will support PSA IPC soon. The interrupts for IPC is under developing, you can check the roadmap to know the plan. Thanks. -Ken > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, > Alan via TF-M > Sent: Saturday, February 16, 2019 7:37 AM > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] interrupts not supported on feature-ipc branch? > > I guess interrupts are only supported on the master branch. > > When will the master branch support PSA IPC? > > Or, when will the feature-ipc branch support interrupts? > > Alan > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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New PSA API proposal

by DeMars, Alan

I obtained the following benchmarks for the 3 PSA APIs psa_connect(), psa_call(), and psa_close() using the attached implementation of a Secure Partition (my_sp.c) and building both my NS application and the SPE image with -O3 optimizations: psa_connect() 2133 cycles psa_call() 2650 cycles psa_close() 2136 cycles The psa_call() numbers were achieved by passing 'MY_SP_MSG_TYPE_NULL' as the message type to my test SP, thus eliminating any invec and outvec processing from the benchmark. The secure partition had been regenerated using the attached tfm manifest to reduce the number of user-provided SPs to just 2: the feature-ipc branch's test PSA service and my test PSA service. With these benchmarks in mind and after reviewing the new PSA-compliant SST API implementations, I propose that a new, more efficient, PSA IPC API be provided for those user-facing SP service requests which require no state in the secure partition. Below is the psa_sst_common() function shared by all of the new PSA compliant sst APIS (snipped from interface/src/tfm_sst_api_ipc.c): static psa_status_t psa_sst_common(uint32_t sid, uint32_t minor_version, const psa_invec *in_vecs, size_t in_len, psa_outvec *out_vecs, size_t out_len) { psa_handle_t handle; psa_status_t status; handle = psa_connect(sid, minor_version); if (handle <= 0) { return PSA_SST_ERR_PARAM_ERROR; } status = psa_call(handle, in_vecs, in_len, out_vecs, out_len); if (status < 0) { status = PSA_SST_ERR_SYSTEM_ERROR; } psa_close(handle); return status; } I propose that the functionality and signature of 'psa_sst_common' be promoted to a formal PSA API. For lack of a better name, call this new API 'psa_ccc()', to convey the meaning that it combines the CONNECT, CALL, and CLOSE functions. Internally, the SPM would skip allocating and deallocating a handle, then pass message type 'PSA_IPC_CCC' to the SP. Here is a crude representation of how the PSA_IPC_CCC message type could be handled by a Secure Partition: case PSA_IPC_CCC: if (inuse) { psa_reply(msg.handle, PSA_CONNECTION_REFUSED); } else { inuse = 1; /* to handle potential SP pre-emption during my_sp_call() case */ r = my_sp_call(&msg); psa_reply(msg.handle, r); inuse = 0; } break; Please consider this proposal. The new API would save the overhead of entering and exiting the SP 3 times for SP service requests that require no state. Alan

6 years, 8 months

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Re: [TF-M] IRQ handling by Secure Partitions proposal

by DeMars, Alan

Miklos, Thank you for those clarifications. Sorry it's taken so long to reply. I think I now have a basic grasp of how interrupts owned by SPs are managed. Regarding item 4) below, what is the proposal for informing a calling NS thread that a service request can't complete until some future asynchronous event (ie a peripheral interrupt) occurs? Will this be in the form of special psa_call() return codes or is the SP expected to use outvecs to convey that information? How will the calling thread know when the service request can be completed? The idea of a dedicated non-secure interrupt that the SP/SPM triggers has been mentioned several times. Some kind of asynchronous callback dispatcher as hinted at in the "Concurrent secure service requests" paragraph here: https://developer.trustedfirmware.org/w/tf_m/design/ns_client_management/ Is this mechanism being designed by TFM or is this functionality going to be left to the various users of the reference PSA implementation? Should I begin designing this myself? I guess the overarching question is, does the PSA proposal support secure peripheral drivers, and if so, how? Alan -----Original Message----- From: TF-M [mailto:tf-m-bounces@lists.trustedfirmware.org] On Behalf Of Miklos Balint via TF-M Sent: Tuesday, February 05, 2019 8:02 AM To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: [EXTERNAL] Re: [TF-M] IRQ handling by Secure Partitions proposal Hi Alan, 0, One thing to point out is that my proposal only covers the "Library" or function-call-based model that was the only one implemented on TF-M master branch at the time of writing. PSA Firmware Framework v1.0 with its IPC mechanism has its own design of how interrupts are supposed to be handled by secure threads - my proposal intends to complement that with the same functionality for the other operating model. This clarification addresses point 5 as well, I believe. 1, SPM "Acknowledges the interrupt": this is not the best wording. Actually this is very bad wording. What I meant to say is that SPM's own interrupt handler is started - which is a hardware action, not one by SPM - and SPM ISR in turn masks the interrupt line in NVIC. As you rightly point out, the peripheral itself is of no concern to SPM, that's the business for partition code, either in its own Partition ISR, or a service function. 2. This means that secure PSP is saved for the pre-empted context, set to the stack of the partition that's the owner of the interrupt line, and any additional housekeeping associated with a context switch (PSPLIM setup, isolation re-configuration, privilege setting - all according to the properties of the partition that is to be activated). Lastly, a mock context is created on the partition stack so that the Partition ISR can be activated with an exception return from the SPM ISR. 3a. The Partition ISR is activated by SPM ISR by doing an exception return to the start address of e.g. UART1_ISR() function. In order for this TF-M first needs to create the mock context mentioned in my point 2. The discussion of the stack frame in the text is meant to clarify that there are two possibilities that need to be considered: if the partition is idle, i.e. there are no ongoing service requests in its context, its stack pointer is either at a default value or - potentially - there's no stack associated with the partition. In that case a stack frame needs to be initialized and the mock context set up there. If the partition is handling a request, its original stack pointer needs to be used as the start address for the mock context used for exception return. 3b. After execution of the Partition ISR, execution is returned to the SPM ISR. At this point, SPM can decide to either re-activate the original context that had been pre-empted by the interrupt, or, can take a scheduling decision to activate a different context, e.g. the partition that had called psa_wait(). 4. The current implementation does not allow for the pre-emption of a secure context by non-secure scheduling events, but that is a limitation that could likely be lifted depending on some basic policies that have to be set up by the system integrator. In such a case the NS thread would be blocked waiting on the completion of the secure service, but a pre-emptive NS OS could schedule a different thread if the time slice of the caller thread runs out. Other options are subject to investigation at this point. ... Please let me know if any of the points I've addressed provide clarity instead of making the design more obscure, in which case I would update the design proposal with the extra information. :) And of course let me know if you have further questions. Regards Miklos -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 02 February 2019 04:29 To: tf-m(a)lists.trustedfirmware.org Subject: [Tf-m] IRQ handling by Secure Partitions proposal Regarding the "SPM behavior" discussion in the "Secure Partition Interrupt Handling" proposal: 1) What is meant by the SPM "Acknowledges the interrupt"? I understand "masks the hardware interrupt line" but I don't see how the SPM can know how to acknowledge a particular peripheral's interrupt. I think acknowledging the interrupt should be done by the "Partition ISR" dedicated to the interrupt, or within the corresponding SP's main loop upon return from psa_wait(). 2) What does "Sets up execution environment for the secure partition" mean, precisely? 3) Can you expand on the "Execute Partition ISR" paragraph a little? I assume you mean that, for instance, the registered UART1_isr() function is called. The discussion of the ISR stack frame I don't really follow. And from the description, I'm not sure when the SP is scheduled to run again to deal with the ISR it was waiting for. 4) A secure partition that depends on an interrupt begs the question of what happens to the NS thread that has called into the SP requesting some service that depends on a subsequent asynchronous event (ISR) to complete the request. The psa_call() function as currently implemented doesn't "block" in the traditional OS sense (ie the thread's context and state are not saved in a manner that allows another task thread to run while the psa_call() is stalled in the SPM waiting for an ISR. 5) The details of SP thread pre-emption and re-entrancy need to be described. Alan -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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interrupts not supported on feature-ipc branch?

by DeMars, Alan

I guess interrupts are only supported on the master branch. When will the master branch support PSA IPC? Or, when will the feature-ipc branch support interrupts? Alan

6 years, 8 months

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SYSTICK ownership

by DeMars, Alan

If not used anywhere else, can a Secure Partition own the secure SYSTICK timer and its interrupt? If so, how is it specified in the SP manifest? Alan

6 years, 8 months

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Musca-A SAU setup issues

by Thomas Törnblom

I am working on porting TF-M to the IAR Embedded Workbench for ARM (EWARM) toolchain and I'm having some issues getting it to start properly. I started out using the ARM.TFM.1.1.0, ARM.Musca_A1_BSP.2.0.0, ARM.mbedTLS.1.3.1 and ARM.CMSIS.5.5.0-dev2 CMSIS packs and I've had to fix things in all of the packs to make the project build with our compiler, some things just to add our tools, some things that were just gcc:isms that are non standard-C. The TF-M code is based on a snapshot of https://git.trustedfirmware.org/trusted-firmware-m.git repository of the following hash: 5c1756fbab6097f5688583d11dea5d1271d2d774 I know that some of these packs are old and I'm also working on a port of the bits on trustedfirmware.org, but I would like to bring the old version up first. The (current) issue I have is that the NS code region becomes inaccessible from the secure part after setting the SAU up and I assume I am missing something. in tfm_core_init() there are calls to: --- tfm_spm_hal_init_isolation_hw(); configure_ns_code(); --- tfm_spm_hal_init_isolation_hw() calls sau_and_idau_cfg(), which sets up: --- /* Configures SAU regions to be non-secure */ SAU->RNR = TFM_NS_REGION_CODE; SAU->RBAR = (memory_regions.non_secure_partition_base & SAU_RBAR_BADDR_Msk); SAU->RLAR = (memory_regions.non_secure_partition_limit & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; --- After this piece is run, the NS vector table becomes all zeros when viewed from secure mode. This causes the configure_ns_code() call above to fail to pick up the ns_msp and ns_entry addresses, they become 0. If I swap the calls around so they become: --- configure_ns_code(); tfm_spm_hal_init_isolation_hw(); --- then ns_msp and ns_entry are picked up OK. How is this supposed to work? When the SAU is setup I get RAZ/WI when accessing NS memory from S mode, the other way around results is a security violation, which is properly handled by the SecureFault_Handler(). What am I missing? I run into other problems later, but that may very well a consequence of earlier issues. Thanks, /Thomas -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>

6 years, 8 months

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Re: [TF-M] SPM crashes when built with any non zero optimization level

by Gyorgy Szing

Hi Alan, Please check this ticket https://developer.trustedfirmware.org/T234 Is it possible you are affected by the same issue? /George -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 14 February 2019 06:59 To: tf-m(a)lists.trustedfirmware.org Subject: [TF-M] SPM crashes when built with any non zero optimization level Is anyone else having the problem that enabling optimizations when building the secure image causes the secure partition manager to crash when entered through any of the psa_xxx() IPC veneers? Using GCC -O1, -O2, or -O3 compile options, something seems to go wrong with the SVC context. Everything behaves correctly when built with no optimizations. Alan -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years, 8 months

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SPM crashes when built with any non zero optimization level

by DeMars, Alan

Is anyone else having the problem that enabling optimizations when building the secure image causes the secure partition manager to crash when entered through any of the psa_xxx() IPC veneers? Using GCC -O1, -O2, or -O3 compile options, something seems to go wrong with the SVC context. Everything behaves correctly when built with no optimizations. Alan

6 years, 8 months

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Re: [TF-M] [EXTERNAL] Re: Clarification of pre-existing TFM secure service alignment with PSA APIs

by DeMars, Alan

Ken, Thank you confirming my understanding. The new NS interface code in those commits clearly demonstrate the underlying calls to psa_connect(), psa_call(), and psa_close(). Alan > On Feb 11, 2019, at 6:38 PM, Ken Liu (Arm Technology China) via TF-M <tf-m(a)lists.trustedfirmware.org> wrote: > > Hi Alan, > After PSA IPC model takes place, existing services need to be modified to support it. > The action is not a re-implement actually. The basic idea is creating an IPC SP body > and calls existing secure service functions. There are also some commits for reference: > https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/473/ > https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/474/ > > There are IPC compatible items in roadmap reflects the plan: > https://developer.trustedfirmware.org/w/tf_m/planning/ > > Thanks > > -Ken > >> -----Original Message----- >> From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, >> Alan via TF-M >> Sent: Tuesday, February 12, 2019 9:39 AM >> To: tf-m(a)lists.trustedfirmware.org >> Subject: [TF-M] Clarification of pre-existing TFM secure service alignment with >> PSA APIs >> >> Is my understanding correct that the existing set of secure services (audit, crypto, >> sst, etc) that use the "Library" or function-call-based-model to enter the SPE are >> being redesigned to conform to the PSA IPC model, meaning that each service >> will be re-implemented as a SP with a forever loop? >> >> If so, does this mean that the existing set of NS-facing APIs associated with each >> secure service will be re-implemented as libraries that funnel all of their calls >> into the SPE through the 3 PSA IPC calls (psa_connect(), psa_call(), and >> psa_close())? >> >> Alan >> -- >> TF-M mailing list >> TF-M(a)lists.trustedfirmware.org >> https://lists.trustedfirmware.org/mailman/listinfo/tf-m > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] tz_context APIs

by DeMars, Alan

I'm thinking that the real concern is that the caller should be in 'privileged mode' rather than specifically in handler mode. Is this correct? If so, perhaps the caller's mode check can be converted to affirm 'privileged mode' rather than handler mode. If not, I don't understand what additional security is gained by being in handler mode. Alan -----Original Message----- From: TF-M [mailto:tf-m-bounces@lists.trustedfirmware.org] On Behalf Of Miklos Balint via TF-M Sent: Wednesday, February 13, 2019 6:47 AM To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: [EXTERNAL] Re: [TF-M] tz_context APIs One fundamental reason for driving context changes from handler mode is to have privilege and isolation control when switching contexts. So it all boils down to the requirements of a particular deployment. If there is no compartmentalization and privilege control in NSPE, i.e. all NS threads and the OS have identical access policies to secure assets, it should be possible to lift this requirement and accept NSPE context change notifications that transition from NSPE to SPE in thread mode. This, however, only results in a performance improvement if SPE also bypasses handler mode for this operation, requiring slightly more than skin-deep modifications in TF-M to handle all possible (ab)uses of the secure context management feature. I think this can be a valid choice for a specific implementation, but support for this as a configuration switch in the upstream and threat modelling the alternate setting would be a stretch in our team's current roadmap. /M -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 13 February 2019 05:11 To: tf-m(a)lists.trustedfirmware.org Subject: [TF-M] tz_context APIs Why do all the APIs declared in tz_context.h need to be called from NS Handler mode? Is this a hard requirement or can it be configured 'OFF'? For performance reasons, our OS doesn't trap into handler mode to perform thread management like creation, scheduling, and context switching. Having to switch to handler mode without a very compelling reason seems like unnecessary overhead in performance-critical code. Alan -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] [Tf-m] [EXTERNAL] Re: Non-secure Client Management

by DeMars, Alan

Hi Miklos, Thank you for the roadmap info. I’ll check this out and provide feedback in a separate email. Yes, my concern is regarding the few dozen cycles of overhead. No, this is not a major limitation but it does seem needlessly wasteful to me. I think your proposal to alter the behavior of TZ_LoadContext_S as you suggest is an excellent idea. My understanding of the TZ_LoadContext_S semantics is “until the next TZ_LoadContext_S call, all calls into the SPM will be from this context”. If that is a correct understanding, then assuming the previously active MemoryId should be stored seems like a safe and always true inference. Alan > On Feb 7, 2019, at 2:42 AM, Miklos Balint via TF-M <tf-m(a)lists.trustedfirmware.org> wrote: > > Hi Alan, > > https://developer.trustedfirmware.org/w/tf_m/planning/ has a roadmap of planned feature support by calendar quarter. NSPM for the thread-based design is not explicitly highlighted but I would expect it to be implemented as part of the Q2 SPM work or Q3 Scheduler work the latest. > Any feedback on that or any other aspect of the roadmap is very welcome so we can take that into account when updating the plans. > > For the TZ functions, please note that these are not proprietary to TF-M but form a standard CMSIS API, a generic RTOS feature for TrustZone-enabled devices: > https://www.keil.com/pack/doc/CMSIS/Core/html/group__context__trustzone__fu… > > Since these calls are direct function calls between NSPE and SPE, the overhead should be in the order of a few dozen clock cycles each, not much more than regular RTOS context switch hooks that would be available in several RTOSes. > Are you concerned that this overhead is a major limitation? > > If so, one enhancement TF-M could provide to support a simplified non-CMSIS-compliant NSPE RTOS implementation is for TZ_LoadContext_S to implement the functionality you described for "SwitchContext", taking only the new MemoryId as argument - the old id is stored in the NSPM database anyway, so the context to be Stored in this case can be inferred by TF-M. If the new context is not secure-accessing, FreeContext can be used as defined by CMSIS. > This way TF-M does not introduce proprietary new functions for functionality already defined by the standard. > Please note that this solution would still need to be analysed for security implications as TF-M would be making additional assumptions on NSPE state - although I don't see a reason for concern at this point. > > /M > > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M > Sent: 03 February 2019 15:18 > To: Ken Liu (Arm Technology China) <Ken.Liu(a)arm.com> > Cc: nd <nd(a)arm.com>; tf-m(a)lists.trustedfirmware.org > Subject: Re: [Tf-m] [EXTERNAL] Re: Non-secure Client Management > > Ken, > > Thank you for your prompt response. Please see my replies below. > > Alan > >> Hi Alan, >> The proposed APIs are implemented for library mode. It will not work under IPC mode in 'feature-ipc' branch. The support of NSPM for IPC will come later. > > Is their a feature rollout schedule that I can follow? > >> The TZ_LoadContext_S() and TZ_StoreContext_S() need to be called every time while secure service accessed NS thread get entering/leaving. It is not combined into one function, because not all NS threads need to access secure service. For those NS threads which do not need to access secure service, these TZ_ APIs are unnecessary to be called. For example, if NS scheduler switches from one secure service accessed thread into the other generic thread, only TZ_StoreContext_S() needs to be called before context switching. > > To avoid the rather burdensome overhead of calling into the SPM twice on those NS context switches in which either the leaving or entering contexts are secure accessing threads, I propose that a NULL TZ_MemoryId_t be defined so that a single TZ_SwitchContext_S() function with two TZ_MemoryId_t arguments can be called. The NULL TZ_MemoryId_t would be passed to identify an entering or leaving context that is not secure accessing. > >> The method of blocking the caller client is based on scenarios. If there are some 'wait' is necessary while secure service is working (waiting for secure hardware IRQ as an example), the method you mentioned may be involved (special return value with an NS IRQ notification). This functionality is not in place right now. >> >> -Ken >> >>> -----Original Message----- >>> From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of >>> DeMars, Alan via TF-M >>> Sent: Sunday, February 3, 2019 9:17 AM >>> To: tf-m(a)lists.trustedfirmware.org >>> Subject: [Tf-m] Non-secure Client Management >>> >>> Regarding the Non-secure Client Management proposal: >>> >>> >>> https://developer.trustedfirmware.org/w/tf_m/design/ns_client_managem >>> ent/ >>> >>> I notice that the veneers for the proposed APIs are in s_veneers.o. >>> Does this mean that the proposal has been adopted and implemented? Is >>> it functional in the current feature-ipc branch? >>> >>> I have a question about the TZ_LoadContext_S() and TZ_StoreContext_S() APIs: >>> Is it expected that each context switch in the NS world will be >>> signaled by calls to each of these APIs indicating the "entering" >>> context and "leaving" context respectively? If so, then why not >>> collapse these two APIs into one called >>> TZ_SwitchContext__S() and pass both the "entering" and "leaving" >>> TZ_MemoryId_t's as arguments? >>> >>> Or is TZ_StoreContext_S() only to be called when a NS context will >>> never call into the SPM again? If that is the case, why isn't >>> TZ_FreeModuleContext_S() sufficient? >>> >>> Regarding the "Concurrent secure service requests" discussion, what >>> does "a non-secure client is blocked on an asynchronous secure service completion"? >>> Would this be achieved by a special return status from psa_call() >>> indicating that the current service request is in process and will >>> complete later on? The psa_call() calling thread would then block on >>> a semaphore that would be released by a dedicated NS IRQ interrupt? Is any of this functionality in place yet? >>> >>> Alan > > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] [Tf-m] [EXTERNAL] Re: Non-secure Client Management

by DeMars, Alan

Miklos, In regards to the roadmap, just to confirm my understanding, does the "[TF-M Core] Interrupt Handling Enhancements" bullet due in Q1`19 refer to the interrupt support as described in section 3.4 "Secure peripheral drivers" of the PSA Firmware Framework document? When will SP pre-emption and blocking be supported? A secure peripheral driver that doesn't allow the NS thread to block while waiting for something to complete is a non-starter for us. As well, a SP thread that can't be pre-empted by a higher priority NS thread is almost as unpalatable for us. Alan -----Original Message----- From: TF-M [mailto:tf-m-bounces@lists.trustedfirmware.org] On Behalf Of Miklos Balint via TF-M Sent: Thursday, February 07, 2019 2:43 AM To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: Re: [TF-M] [Tf-m] [EXTERNAL] Re: Non-secure Client Management Hi Alan, https://developer.trustedfirmware.org/w/tf_m/planning/ has a roadmap of planned feature support by calendar quarter. NSPM for the thread-based design is not explicitly highlighted but I would expect it to be implemented as part of the Q2 SPM work or Q3 Scheduler work the latest. Any feedback on that or any other aspect of the roadmap is very welcome so we can take that into account when updating the plans. For the TZ functions, please note that these are not proprietary to TF-M but form a standard CMSIS API, a generic RTOS feature for TrustZone-enabled devices: https://www.keil.com/pack/doc/CMSIS/Core/html/group__context__trustzone__fu… Since these calls are direct function calls between NSPE and SPE, the overhead should be in the order of a few dozen clock cycles each, not much more than regular RTOS context switch hooks that would be available in several RTOSes. Are you concerned that this overhead is a major limitation? If so, one enhancement TF-M could provide to support a simplified non-CMSIS-compliant NSPE RTOS implementation is for TZ_LoadContext_S to implement the functionality you described for "SwitchContext", taking only the new MemoryId as argument - the old id is stored in the NSPM database anyway, so the context to be Stored in this case can be inferred by TF-M. If the new context is not secure-accessing, FreeContext can be used as defined by CMSIS. This way TF-M does not introduce proprietary new functions for functionality already defined by the standard. Please note that this solution would still need to be analysed for security implications as TF-M would be making additional assumptions on NSPE state - although I don't see a reason for concern at this point. /M -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 03 February 2019 15:18 To: Ken Liu (Arm Technology China) <Ken.Liu(a)arm.com> Cc: nd <nd(a)arm.com>; tf-m(a)lists.trustedfirmware.org Subject: Re: [Tf-m] [EXTERNAL] Re: Non-secure Client Management Ken, Thank you for your prompt response. Please see my replies below. Alan > Hi Alan, > The proposed APIs are implemented for library mode. It will not work under IPC mode in 'feature-ipc' branch. The support of NSPM for IPC will come later. Is their a feature rollout schedule that I can follow? > The TZ_LoadContext_S() and TZ_StoreContext_S() need to be called every time while secure service accessed NS thread get entering/leaving. It is not combined into one function, because not all NS threads need to access secure service. For those NS threads which do not need to access secure service, these TZ_ APIs are unnecessary to be called. For example, if NS scheduler switches from one secure service accessed thread into the other generic thread, only TZ_StoreContext_S() needs to be called before context switching. To avoid the rather burdensome overhead of calling into the SPM twice on those NS context switches in which either the leaving or entering contexts are secure accessing threads, I propose that a NULL TZ_MemoryId_t be defined so that a single TZ_SwitchContext_S() function with two TZ_MemoryId_t arguments can be called. The NULL TZ_MemoryId_t would be passed to identify an entering or leaving context that is not secure accessing. > The method of blocking the caller client is based on scenarios. If there are some 'wait' is necessary while secure service is working (waiting for secure hardware IRQ as an example), the method you mentioned may be involved (special return value with an NS IRQ notification). This functionality is not in place right now. > > -Ken > >> -----Original Message----- >> From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of >> DeMars, Alan via TF-M >> Sent: Sunday, February 3, 2019 9:17 AM >> To: tf-m(a)lists.trustedfirmware.org >> Subject: [Tf-m] Non-secure Client Management >> >> Regarding the Non-secure Client Management proposal: >> >> >> https://developer.trustedfirmware.org/w/tf_m/design/ns_client_managem >> ent/ >> >> I notice that the veneers for the proposed APIs are in s_veneers.o. >> Does this mean that the proposal has been adopted and implemented? Is >> it functional in the current feature-ipc branch? >> >> I have a question about the TZ_LoadContext_S() and TZ_StoreContext_S() APIs: >> Is it expected that each context switch in the NS world will be >> signaled by calls to each of these APIs indicating the "entering" >> context and "leaving" context respectively? If so, then why not >> collapse these two APIs into one called >> TZ_SwitchContext__S() and pass both the "entering" and "leaving" >> TZ_MemoryId_t's as arguments? >> >> Or is TZ_StoreContext_S() only to be called when a NS context will >> never call into the SPM again? If that is the case, why isn't >> TZ_FreeModuleContext_S() sufficient? >> >> Regarding the "Concurrent secure service requests" discussion, what >> does "a non-secure client is blocked on an asynchronous secure service completion"? >> Would this be achieved by a special return status from psa_call() >> indicating that the current service request is in process and will >> complete later on? The psa_call() calling thread would then block on >> a semaphore that would be released by a dedicated NS IRQ interrupt? Is any of this functionality in place yet? >> >> Alan -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] tz_context APIs

by Miklos Balint

One fundamental reason for driving context changes from handler mode is to have privilege and isolation control when switching contexts. So it all boils down to the requirements of a particular deployment. If there is no compartmentalization and privilege control in NSPE, i.e. all NS threads and the OS have identical access policies to secure assets, it should be possible to lift this requirement and accept NSPE context change notifications that transition from NSPE to SPE in thread mode. This, however, only results in a performance improvement if SPE also bypasses handler mode for this operation, requiring slightly more than skin-deep modifications in TF-M to handle all possible (ab)uses of the secure context management feature. I think this can be a valid choice for a specific implementation, but support for this as a configuration switch in the upstream and threat modelling the alternate setting would be a stretch in our team's current roadmap. /M -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 13 February 2019 05:11 To: tf-m(a)lists.trustedfirmware.org Subject: [TF-M] tz_context APIs Why do all the APIs declared in tz_context.h need to be called from NS Handler mode? Is this a hard requirement or can it be configured 'OFF'? For performance reasons, our OS doesn't trap into handler mode to perform thread management like creation, scheduling, and context switching. Having to switch to handler mode without a very compelling reason seems like unnecessary overhead in performance-critical code. Alan -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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tz_context APIs

by DeMars, Alan

Why do all the APIs declared in tz_context.h need to be called from NS Handler mode? Is this a hard requirement or can it be configured 'OFF'? For performance reasons, our OS doesn't trap into handler mode to perform thread management like creation, scheduling, and context switching. Having to switch to handler mode without a very compelling reason seems like unnecessary overhead in performance-critical code. Alan

6 years, 8 months

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Re: [TF-M] Clarification of pre-existing TFM secure service alignment with PSA APIs

by Ken Liu (Arm Technology China)

Hi Alan, After PSA IPC model takes place, existing services need to be modified to support it. The action is not a re-implement actually. The basic idea is creating an IPC SP body and calls existing secure service functions. There are also some commits for reference: https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/473/ https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/474/ There are IPC compatible items in roadmap reflects the plan: https://developer.trustedfirmware.org/w/tf_m/planning/ Thanks -Ken > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, > Alan via TF-M > Sent: Tuesday, February 12, 2019 9:39 AM > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] Clarification of pre-existing TFM secure service alignment with > PSA APIs > > Is my understanding correct that the existing set of secure services (audit, crypto, > sst, etc) that use the "Library" or function-call-based-model to enter the SPE are > being redesigned to conform to the PSA IPC model, meaning that each service > will be re-implemented as a SP with a forever loop? > > If so, does this mean that the existing set of NS-facing APIs associated with each > secure service will be re-implemented as libraries that funnel all of their calls > into the SPE through the 3 PSA IPC calls (psa_connect(), psa_call(), and > psa_close())? > > Alan > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Clarification of pre-existing TFM secure service alignment with PSA APIs

by DeMars, Alan

Is my understanding correct that the existing set of secure services (audit, crypto, sst, etc) that use the "Library" or function-call-based-model to enter the SPE are being redesigned to conform to the PSA IPC model, meaning that each service will be re-implemented as a SP with a forever loop? If so, does this mean that the existing set of NS-facing APIs associated with each secure service will be re-implemented as libraries that funnel all of their calls into the SPE through the 3 PSA IPC calls (psa_connect(), psa_call(), and psa_close())? Alan

6 years, 8 months

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Re: [TF-M] How to run PSA API compliance tests with TF-M SST service

by Marc Moreno Berengue

Hi all, All the patches needed to pass all the PSA API Compliance tests have been merged into TF-M master branch, so there is no need for step [2] below, just checkout the TF-M master branch. Thanks, Marc Moreno ________________________________ From: Marc Moreno Berengue Sent: 01 February 2019 18:17 To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: [TF-M] How to run PSA API compliance tests with TF-M SST service <mailto:nd@arm.com>Hi all, The Secure Storage (SST) service has been updated to align it with the PSA Protected Storage APIs version 1.0. There are a set of patches which implements this change. Please, find more information about those changes in the following ticket: https://developer.trustedfirmware.org/T218 It's possible to run the PSA API Compliance tests (https://github.com/ARM-software/psa-arch-tests/tree/master/api-tests/dev_ap…) with the TF-M SST service by following the instructions below. (The instructions assume that psa-arch-tests and trusted-firmware-m directories are at the same level in the filesystem): 1. Checkout https://github.com/ARM-software/psa-arch-tests/ 2. Checkout https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/589/ 3. Copy the `interface/include/psa_protected_storage.h` to `interface/include/psa/protected_storage.h` as this is the header name expected by the PSA API Compliance tests 4. Build the SST tests for the PSA API compliance as described in the `psa-arch-tests/api-tests` for one of the supported targets, providing the include path of the TF-M interface (i.e. trusted-firmware-m/interface/include). Set crypto and internal trusted storage as not implemented in `psa-arch-tests/api-tests/platform/targets/<TARGET_NAME>/Makefile`. Set PSA_CRYPTO_IMPLEMENTED:=0 and PSA_INTERNAL_TRUSTED_STORAGE_IMPLEMENTED:=0 * The list of tests being run is specified in the file `psa-arch-tests/api-tests/dev_apis/protected_storage/testsuite.db` * For example, this command will build the tests for AN521 "./tools/scripts/setup.sh --target tgt_dev_apis_tfm_an521 --toolchain ARMCLANG --cpu_arch armv8m_ml --verbose 2 --suite protected_storage --include ../../trusted-firmware-m/interface/include --archive_tests" 5. Build TF-M by using the ConfigPsaApiTest.cmake, enabling the PSA API Compliance tests for SST service by adding the following cmake switch during the configuration step: "-DPSA_API_TEST_SECURE_STORAGE=ON" * For example, this command will build the TF-M + NS app with PSA API Protected Storage tests for AN521 "cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink -f ../ConfigPsaApiTest.cmake` -DTARGET_PLATFORM=AN521 -DCOMPILER=ARMCLANG -DPSA_API_TEST_SECURE_STORAGE=ON ../" This will make our NS test app run a subset of the PSA API compliance tests for SST service. Thanks, Marc Moreno

6 years, 8 months

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Re: [TF-M] [EXTERNAL] Re: generated header files

by DeMars, Alan

Mate, Thank you! I was able to regenerate from an edited .yaml file and get exactly what I needed. Alan > On Feb 7, 2019, at 11:47 PM, Mate Toth-Pal via TF-M <tf-m(a)lists.trustedfirmware.org> wrote: > > Hi Alan, > > Currently the generation of these files is a manual step that should be done prior to build. > > The script that does the generation is the tools/tfm_parse_manifest_list.py python script. The script has to be run with no command line parameters from the TF-M source root dir. The location of two files, tools\tfm_generated_file_list.yaml and tools\tfm_manifest_list.yaml are hardcoded into the script, and they specify the files the script works on. > > tfm_manifest_list.yaml contains the list of partition manifest files. These yaml files provide the information that template files have to be filled with. > tfm_generated_file_list.yaml contains the list of files to be generated. The script assumes, that for each <generated_file_path>/<generated_file_name> there is a file <generated_file_path>/<generated_file_name>.template file, which is used as a template for generation. > > Please note, that the current version of this script on master contains a custom parser and substituting code, however we have a plan to replace it to the Jinja2 template parser engine. Please see the proposal here: https://developer.trustedfirmware.org/w/tf_m/design/code_generation_with_ji… > > Regards, > Mate > > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M > Sent: 07 February 2019 22:35 > To: tf-m(a)lists.trustedfirmware.org > Subject: [TF-M] generated header files > > I'm using the feature-ipc branch and I notice a lot of these warnings in TF-M header files: > > /*********** WARNING: This is an auto-generated file. Do not edit! ***********/ > > When are these files generated? I assume they're derived from associated manifest files. > > When I use cmake to create a "ConfigCoreIPC.cmake" build area, I don't see any header files being generated in the process. Any changes I've made to header files with these warnings are still present. Is there a TF-M cmake configuration that regenerates these files? If so, how do I invoke it so I can more properly reconfigure a custom SP? > > Alan > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] How to run PSA API compliance tests with TF-M Crypto

by Antonio De Angelis

Hi all, All the patches needed to pass all the PSA API Compliance tests from the ew_beta0 branch have been merged into TF-M master branch, so there is no need for step [2] below, just checkout the TF-M master branch. Thanks, Antonio -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Antonio De Angelis via TF-M Sent: 31 January 2019 21:42 To: tf-m(a)lists.trustedfirmware.org Cc: nd <nd(a)arm.com> Subject: Re: [Tf-m] How to run PSA API compliance tests with TF-M Crypto Hi all, after a restructuring of the patches in the pull request, the patch that needs to be checked out at step [2] in the instructions in the mail below is amended to: 2. Checkout https://review.trustedfirmware.org/c/trusted-firmware-m/+/588/ Thanks, Antonio ________________________________ From: Antonio De Angelis Sent: 30 January 2019 17:21 To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: How to run PSA API compliance tests with TF-M Crypto Hi all, It’s possible to run a subset of the PSA API Compliance tests with the TF-M Crypto service by following the instructions below (it assumes that psa-arch-tests and trusted-firmware-m directories are at the same level in the filesystem): 1. Checkout https://github.com/ARM-software/psa-arch-tests/tree/ew_beta0 (ew_beta0 branch of the PSA API Compliance tests repo) 2. Checkout https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/561/ 3. Copy the interface/include/psa_crypto.h to interface/include/psa/crypto.h as this is the header name expected by the PSA API Compliance tests 4. Build the Crypto tests for the PSA API compliance as described in the psa-arch-tests/api-tests for one of the supported targets, providing the include path of the TF-M interface (i.e. trusted-firmware-m/interface/include) * The list of tests being run is specified in the file psa-arch-tests/api-tests/dev_apis/crypto/testsuite.db * For example, this command will build the tests for AN521 “./tools/scripts/setup.sh --target tgt_dev_apis_tfm_an521 --toolchain ARMCLANG --cpu_arch armv8m_ml --verbose 2 --suite crypto --include ../../trusted-firmware-m/interface/include --archive_tests” 5. Build TF-M by using the ConfigPsaApiTest.cmake, enabling the PSA API Compliance tests for Crypto by adding the following cmake switch during the configuration step: “-DPSA_API_TEST_CRYPTO=ON” * For example, this command will build the TF-M + NS app with PSA API Crypto tests for AN521 “cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink -f ../ConfigPsaApiTest.cmake` -DTARGET_PLATFORM=AN521 -DCOMPILER=ARMCLANG -DPSA_API_TEST_CRYPTO=ON ../” This will make our NS test app run a subset of the PSA API compliance tests for Crypto. We are currently working on fixing the remaining failures. Thanks, Antonio -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] generated header files

by Mate Toth-Pal

Hi Alan, Currently the generation of these files is a manual step that should be done prior to build. The script that does the generation is the tools/tfm_parse_manifest_list.py python script. The script has to be run with no command line parameters from the TF-M source root dir. The location of two files, tools\tfm_generated_file_list.yaml and tools\tfm_manifest_list.yaml are hardcoded into the script, and they specify the files the script works on. tfm_manifest_list.yaml contains the list of partition manifest files. These yaml files provide the information that template files have to be filled with. tfm_generated_file_list.yaml contains the list of files to be generated. The script assumes, that for each <generated_file_path>/<generated_file_name> there is a file <generated_file_path>/<generated_file_name>.template file, which is used as a template for generation. Please note, that the current version of this script on master contains a custom parser and substituting code, however we have a plan to replace it to the Jinja2 template parser engine. Please see the proposal here: https://developer.trustedfirmware.org/w/tf_m/design/code_generation_with_ji… Regards, Mate -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 07 February 2019 22:35 To: tf-m(a)lists.trustedfirmware.org Subject: [TF-M] generated header files I'm using the feature-ipc branch and I notice a lot of these warnings in TF-M header files: /*********** WARNING: This is an auto-generated file. Do not edit! ***********/ When are these files generated? I assume they're derived from associated manifest files. When I use cmake to create a "ConfigCoreIPC.cmake" build area, I don't see any header files being generated in the process. Any changes I've made to header files with these warnings are still present. Is there a TF-M cmake configuration that regenerates these files? If so, how do I invoke it so I can more properly reconfigure a custom SP? Alan -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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generated header files

by DeMars, Alan

I'm using the feature-ipc branch and I notice a lot of these warnings in TF-M header files: /*********** WARNING: This is an auto-generated file. Do not edit! ***********/ When are these files generated? I assume they're derived from associated manifest files. When I use cmake to create a "ConfigCoreIPC.cmake" build area, I don't see any header files being generated in the process. Any changes I've made to header files with these warnings are still present. Is there a TF-M cmake configuration that regenerates these files? If so, how do I invoke it so I can more properly reconfigure a custom SP? Alan

6 years, 8 months

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Re: [TF-M] [Tf-m] [EXTERNAL] Re: Non-secure Client Management

by Miklos Balint

Hi Alan, https://developer.trustedfirmware.org/w/tf_m/planning/ has a roadmap of planned feature support by calendar quarter. NSPM for the thread-based design is not explicitly highlighted but I would expect it to be implemented as part of the Q2 SPM work or Q3 Scheduler work the latest. Any feedback on that or any other aspect of the roadmap is very welcome so we can take that into account when updating the plans. For the TZ functions, please note that these are not proprietary to TF-M but form a standard CMSIS API, a generic RTOS feature for TrustZone-enabled devices: https://www.keil.com/pack/doc/CMSIS/Core/html/group__context__trustzone__fu… Since these calls are direct function calls between NSPE and SPE, the overhead should be in the order of a few dozen clock cycles each, not much more than regular RTOS context switch hooks that would be available in several RTOSes. Are you concerned that this overhead is a major limitation? If so, one enhancement TF-M could provide to support a simplified non-CMSIS-compliant NSPE RTOS implementation is for TZ_LoadContext_S to implement the functionality you described for "SwitchContext", taking only the new MemoryId as argument - the old id is stored in the NSPM database anyway, so the context to be Stored in this case can be inferred by TF-M. If the new context is not secure-accessing, FreeContext can be used as defined by CMSIS. This way TF-M does not introduce proprietary new functions for functionality already defined by the standard. Please note that this solution would still need to be analysed for security implications as TF-M would be making additional assumptions on NSPE state - although I don't see a reason for concern at this point. /M -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 03 February 2019 15:18 To: Ken Liu (Arm Technology China) <Ken.Liu(a)arm.com> Cc: nd <nd(a)arm.com>; tf-m(a)lists.trustedfirmware.org Subject: Re: [Tf-m] [EXTERNAL] Re: Non-secure Client Management Ken, Thank you for your prompt response. Please see my replies below. Alan > Hi Alan, > The proposed APIs are implemented for library mode. It will not work under IPC mode in 'feature-ipc' branch. The support of NSPM for IPC will come later. Is their a feature rollout schedule that I can follow? > The TZ_LoadContext_S() and TZ_StoreContext_S() need to be called every time while secure service accessed NS thread get entering/leaving. It is not combined into one function, because not all NS threads need to access secure service. For those NS threads which do not need to access secure service, these TZ_ APIs are unnecessary to be called. For example, if NS scheduler switches from one secure service accessed thread into the other generic thread, only TZ_StoreContext_S() needs to be called before context switching. To avoid the rather burdensome overhead of calling into the SPM twice on those NS context switches in which either the leaving or entering contexts are secure accessing threads, I propose that a NULL TZ_MemoryId_t be defined so that a single TZ_SwitchContext_S() function with two TZ_MemoryId_t arguments can be called. The NULL TZ_MemoryId_t would be passed to identify an entering or leaving context that is not secure accessing. > The method of blocking the caller client is based on scenarios. If there are some 'wait' is necessary while secure service is working (waiting for secure hardware IRQ as an example), the method you mentioned may be involved (special return value with an NS IRQ notification). This functionality is not in place right now. > > -Ken > >> -----Original Message----- >> From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of >> DeMars, Alan via TF-M >> Sent: Sunday, February 3, 2019 9:17 AM >> To: tf-m(a)lists.trustedfirmware.org >> Subject: [Tf-m] Non-secure Client Management >> >> Regarding the Non-secure Client Management proposal: >> >> >> https://developer.trustedfirmware.org/w/tf_m/design/ns_client_managem >> ent/ >> >> I notice that the veneers for the proposed APIs are in s_veneers.o. >> Does this mean that the proposal has been adopted and implemented? Is >> it functional in the current feature-ipc branch? >> >> I have a question about the TZ_LoadContext_S() and TZ_StoreContext_S() APIs: >> Is it expected that each context switch in the NS world will be >> signaled by calls to each of these APIs indicating the "entering" >> context and "leaving" context respectively? If so, then why not >> collapse these two APIs into one called >> TZ_SwitchContext__S() and pass both the "entering" and "leaving" >> TZ_MemoryId_t's as arguments? >> >> Or is TZ_StoreContext_S() only to be called when a NS context will >> never call into the SPM again? If that is the case, why isn't >> TZ_FreeModuleContext_S() sufficient? >> >> Regarding the "Concurrent secure service requests" discussion, what >> does "a non-secure client is blocked on an asynchronous secure service completion"? >> Would this be achieved by a special return status from psa_call() >> indicating that the current service request is in process and will >> complete later on? The psa_call() calling thread would then block on >> a semaphore that would be released by a dedicated NS IRQ interrupt? Is any of this functionality in place yet? >> >> Alan

6 years, 8 months

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Re: [TF-M] IRQ handling by Secure Partitions proposal

by Miklos Balint

Hi Alan, 0, One thing to point out is that my proposal only covers the "Library" or function-call-based model that was the only one implemented on TF-M master branch at the time of writing. PSA Firmware Framework v1.0 with its IPC mechanism has its own design of how interrupts are supposed to be handled by secure threads - my proposal intends to complement that with the same functionality for the other operating model. This clarification addresses point 5 as well, I believe. 1, SPM "Acknowledges the interrupt": this is not the best wording. Actually this is very bad wording. What I meant to say is that SPM's own interrupt handler is started - which is a hardware action, not one by SPM - and SPM ISR in turn masks the interrupt line in NVIC. As you rightly point out, the peripheral itself is of no concern to SPM, that's the business for partition code, either in its own Partition ISR, or a service function. 2. This means that secure PSP is saved for the pre-empted context, set to the stack of the partition that's the owner of the interrupt line, and any additional housekeeping associated with a context switch (PSPLIM setup, isolation re-configuration, privilege setting - all according to the properties of the partition that is to be activated). Lastly, a mock context is created on the partition stack so that the Partition ISR can be activated with an exception return from the SPM ISR. 3a. The Partition ISR is activated by SPM ISR by doing an exception return to the start address of e.g. UART1_ISR() function. In order for this TF-M first needs to create the mock context mentioned in my point 2. The discussion of the stack frame in the text is meant to clarify that there are two possibilities that need to be considered: if the partition is idle, i.e. there are no ongoing service requests in its context, its stack pointer is either at a default value or - potentially - there's no stack associated with the partition. In that case a stack frame needs to be initialized and the mock context set up there. If the partition is handling a request, its original stack pointer needs to be used as the start address for the mock context used for exception return. 3b. After execution of the Partition ISR, execution is returned to the SPM ISR. At this point, SPM can decide to either re-activate the original context that had been pre-empted by the interrupt, or, can take a scheduling decision to activate a different context, e.g. the partition that had called psa_wait(). 4. The current implementation does not allow for the pre-emption of a secure context by non-secure scheduling events, but that is a limitation that could likely be lifted depending on some basic policies that have to be set up by the system integrator. In such a case the NS thread would be blocked waiting on the completion of the secure service, but a pre-emptive NS OS could schedule a different thread if the time slice of the caller thread runs out. Other options are subject to investigation at this point. ... Please let me know if any of the points I've addressed provide clarity instead of making the design more obscure, in which case I would update the design proposal with the extra information. :) And of course let me know if you have further questions. Regards Miklos -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 02 February 2019 04:29 To: tf-m(a)lists.trustedfirmware.org Subject: [Tf-m] IRQ handling by Secure Partitions proposal Regarding the "SPM behavior" discussion in the "Secure Partition Interrupt Handling" proposal: 1) What is meant by the SPM "Acknowledges the interrupt"? I understand "masks the hardware interrupt line" but I don't see how the SPM can know how to acknowledge a particular peripheral's interrupt. I think acknowledging the interrupt should be done by the "Partition ISR" dedicated to the interrupt, or within the corresponding SP's main loop upon return from psa_wait(). 2) What does "Sets up execution environment for the secure partition" mean, precisely? 3) Can you expand on the "Execute Partition ISR" paragraph a little? I assume you mean that, for instance, the registered UART1_isr() function is called. The discussion of the ISR stack frame I don't really follow. And from the description, I'm not sure when the SP is scheduled to run again to deal with the ISR it was waiting for. 4) A secure partition that depends on an interrupt begs the question of what happens to the NS thread that has called into the SP requesting some service that depends on a subsequent asynchronous event (ISR) to complete the request. The psa_call() function as currently implemented doesn't "block" in the traditional OS sense (ie the thread's context and state are not saved in a manner that allows another task thread to run while the psa_call() is stalled in the SPM waiting for an ISR. 5) The details of SP thread pre-emption and re-entrancy need to be described. Alan -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 8 months

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Re: [TF-M] [Tf-m] Issues porting to new toolchain

by Mate Toth-Pal

Hi Thomas, 1) If you can provide implementations in standard C, then yes, it can be a benefit 2) Yes, I think that would make the code review easier. 3) You are right, adding ifdefs to C files should not be the way to go. As GNUARM doesn't provide symbols like this, we could easily solve this problem by creating the symbols in the ld file to be the same as the ones generated by the ARMCLANG toolchain. One option is to do the same for the EWARM toolchain as for GNUARM. I had a quick look at the EWARM Development Guide, and it seems that the linker configuration file supports this feature (exporting symbols, and using expressions with start/end addresses of elf sections). Another way to go would be to move the REGION_DECLARE, REGION_NAME, and related macros to a compiler specific header file, like tfm_compiler.h. Then this file could be placed in the platforms' toolchain specific directories. This solution would have the benefit, that the multiple definitions of the macros would be reduced to a single one. However to me this seems to be a greater effort: - The build system have to be modified to add the platform specific folder as include folder for compilation - The macros should be restructured a bit, as there would be a need for LOAD_REGION_DECLARE(...), EXECUTION_REGION_DECLARE_RW(...), EXECUTION_REGION_DECLARE_RO(...) and more (at least based on my quick look at the code) - All the source files have to be updated to use the new macros and include the specific header 4) The way to solve this could be to create a new function in the Compiler<tooolchain>Common.cmake files, called something like get_pre_include_parameter, that generates the proper option (--preinclude of -include) and call that function in BuildMbedtls.cmake Regards, Mate -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M Sent: 04 February 2019 15:41 To: DeMars, Alan via TF-M <tf-m(a)lists.trustedfirmware.org> Subject: [Tf-m] Issues porting to new toolchain Greetings, I am working on adding IAR Embedded Workbench for ARM (EWARM) as a supported toolchain for TF-M and I would like to discuss some of the issues I've run into before I start issuing PR:s. 1) The current TF-M source uses non-standard gcc extensions which EWARM does not support. I assume it should not be an issue converting this code into standard C, that would only help porting to other toolchains as well. 2) Should I create separate PR:s for these changes and the toolchain changes? 3) In some places (tfm_core.c, ...) there are hardwired references to symbols like Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base, Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit. Our toolchain would use symbols like TFM_UNPRIV_SCRATCH$$Base and TFM_UNPRIV_SCRATCH$$Limit instead. What to do about this? Adding #ifdefs in the .c files will be messy and I'd like some cleaner solution. 4) Some common cmake files contains hardwired option names like "-include" (BuildMbedtls.cmake) Our toolchain uses "--preinclude" instead and I think this ought to be handled in the compiler specific cmake files instead. -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems> -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 9 months

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Issues porting to new toolchain

by Thomas Törnblom

Greetings, I am working on adding IAR Embedded Workbench for ARM (EWARM) as a supported toolchain for TF-M and I would like to discuss some of the issues I've run into before I start issuing PR:s. 1) The current TF-M source uses non-standard gcc extensions which EWARM does not support. I assume it should not be an issue converting this code into standard C, that would only help porting to other toolchains as well. 2) Should I create separate PR:s for these changes and the toolchain changes? 3) In some places (tfm_core.c, ...) there are hardwired references to symbols like Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base, Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit. Our toolchain would use symbols like TFM_UNPRIV_SCRATCH$$Base and TFM_UNPRIV_SCRATCH$$Limit instead. What to do about this? Adding #ifdefs in the .c files will be messy and I'd like some cleaner solution. 4) Some common cmake files contains hardwired option names like "-include" (BuildMbedtls.cmake) Our toolchain uses "--preinclude" instead and I think this ought to be handled in the compiler specific cmake files instead. -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>

6 years, 9 months

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Re: [Tf-m] [TF-M] How to run PSA API compliance tests with TF-M SST service

by Shebu Varghese Kuriakose

Adding TF-M mailing list and Prasanth Hi Murat, Looking at the list of subscribed members, you are not yet registered to TF-M mailing list. Please try subscribing using the link in https://www.trustedfirmware.org/contact/. You will receive a mail which you need to acknowledge before you get subscribed. Check your spam as well for the mail asking for acknowledgement. On the topic below, the extended tests are for testing against the optional/extended SST Protected Storage APIs. These APIs are optional and so not required to pass for PSA Functional API certification. The SST patch set below doesn’t support those optional SST PS APIs. From what I last heard, Marc and team has verified all the other mandatory SST PS Tests on MuscaA using the patches below. TF-M team or Prasanth might be able to advise on what might be going wrong. Regards, Shebu -----Original Message----- From: murat(a)za-ya.co <murat(a)za-ya.co> Sent: Sunday, February 3, 2019 10:29 AM To: Marc Moreno Berengue <Marc.MorenoBerengue(a)arm.com> Cc: nd <nd(a)arm.com>; Shebu Varghese Kuriakose <Shebu.VargheseKuriakose(a)arm.com> Subject: RE: [Tf-m] [TF-M] How to run PSA API compliance tests with TF-M SST service Dear Marc, Thank you for introductions. We are now running PSA SST tests on Musca board, and as we see there are only three test suites (p011, p012, p013), the other test suites are empty. And when we run the PSA SST tests, SST tests skip even existing three test cases. This is because the first test case asks for supported API and expects " PSA_PS_SUPPORT_SET_EXTENDED " static const test_data p011_data[] = { { VAL_PS_GET_SUPPORT, PSA_PS_SUPPORT_SET_EXTENDED /* Check if optional PS API supported */ }, And TF-m (https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/589/ ) does not the support extended PSA API yet as we see from enum tfm_sst_err_t tfm_sst_get_support(uint32_t *support_flags) { /* * This function returns a bitmask with flags set for all of the optional * features supported by the SST service implementation. * * SST service does not support the optional extended PSA PS API yet. <<<<<<<<<<<<<<<<<<<<< NO SUPPORT */ *support_flags = 0; <<<<<<<<<<<<<<<<<<<<< NO SUPPORT return TFM_SST_ERR_SUCCESS; } And PSA Test Suite skips the all remaining test case if there is no EXTENDED API Support. 0.000 - 00>Test Case not needed as Optional PS APIs are not supported. 0.000 - 00>TEST RESULT: SKIPPED (Skip Code=0x2b) 0.000 - 00>****************************************** 0.000 - 00>************ Protected Storage Suite Report ********** 0.000 - 00>TOTAL TESTS : 3 0.000 - 00>TOTAL PASSED : 0 0.000 - 00>TOTAL SIM ERROR : 0 0.000 - 00>TOTAL FAILED : 0 0.000 - 00>TOTAL SKIPPED : 3 0.000 - 00>****************************************** 0.000 - 00>Entering standby.. Is it the expected behaviour for Musca Port or are we missing something? (We are registered but we don’t receive any e-mail from the TF-m mail list, I don’t know how to see your response 😊 ) Thank you. Best Regards. Murat -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Marc Moreno Berengue via TF-M Sent: 01 February 2019 18:25 To: tf-m(a)lists.trustedfirmware.org Cc: nd <nd(a)arm.com> Subject: [Tf-m] [TF-M] How to run PSA API compliance tests with TF-M SST service Hi all, The Secure Storage (SST) service has been updated to align it with the PSA Protected Storage APIs version 1.0. There are a set of patches which implements this change. Please, find more information about those changes in the following ticket: https://developer.trustedfirmware.org/T218 It's possible to run the PSA API Compliance tests (https://github.com/ARM-software/psa-arch-tests/tree/master/api-tests/dev_ap…) with the TF-M SST service by following the instructions below. (The instructions assume that psa-arch-tests and trusted-firmware-m directories are at the same level in the filesystem): 1. Checkout https://github.com/ARM-software/psa-arch-tests/ 2. Checkout https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/589/ 3. Copy the `interface/include/psa_protected_storage.h` to `interface/include/psa/protected_storage.h` as this is the header name expected by the PSA API Compliance tests 4. Build the SST tests for the PSA API compliance as described in the `psa-arch-tests/api-tests` for one of the supported targets, providing the include path of the TF-M interface (i.e. trusted-firmware-m/interface/include). Set crypto and internal trusted storage as not implemented in `psa-arch-tests/api-tests/platform/targets/<TARGET_NAME>/Makefile`. Set PSA_CRYPTO_IMPLEMENTED:=0 and PSA_INTERNAL_TRUSTED_STORAGE_IMPLEMENTED:=0 * The list of tests being run is specified in the file `psa-arch-tests/api-tests/dev_apis/protected_storage/testsuite.db` * For example, this command will build the tests for AN521 "./tools/scripts/setup.sh --target tgt_dev_apis_tfm_an521 --toolchain ARMCLANG --cpu_arch armv8m_ml --verbose 2 --suite protected_storage --include ../../trusted-firmware-m/interface/include --archive_tests" 5. Build TF-M by using the ConfigPsaApiTest.cmake, enabling the PSA API Compliance tests for SST service by adding the following cmake switch during the configuration step: "-DPSA_API_TEST_SECURE_STORAGE=ON" * For example, this command will build the TF-M + NS app with PSA API Protected Storage tests for AN521 "cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink -f ../ConfigPsaApiTest.cmake` -DTARGET_PLATFORM=AN521 -DCOMPILER=ARMCLANG -DPSA_API_TEST_SECURE_STORAGE=ON ../" This will make our NS test app run a subset of the PSA API compliance tests for SST service. Thanks, Marc Moreno -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 9 months

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Re: [Tf-m] [EXTERNAL] Re: Non-secure Client Management

by DeMars, Alan

Ken, Thank you for your prompt response. Please see my replies below. Alan > Hi Alan, > The proposed APIs are implemented for library mode. It will not work under IPC mode in 'feature-ipc' branch. The support of NSPM for IPC will come later. Is their a feature rollout schedule that I can follow? > The TZ_LoadContext_S() and TZ_StoreContext_S() need to be called every time while secure service accessed NS thread get entering/leaving. It is not combined into one function, because not all NS threads need to access secure service. For those NS threads which do not need to access secure service, these TZ_ APIs are unnecessary to be called. For example, if NS scheduler switches from one secure service accessed thread into the other generic thread, only TZ_StoreContext_S() needs to be called before context switching. To avoid the rather burdensome overhead of calling into the SPM twice on those NS context switches in which either the leaving or entering contexts are secure accessing threads, I propose that a NULL TZ_MemoryId_t be defined so that a single TZ_SwitchContext_S() function with two TZ_MemoryId_t arguments can be called. The NULL TZ_MemoryId_t would be passed to identify an entering or leaving context that is not secure accessing. > The method of blocking the caller client is based on scenarios. If there are some 'wait' is necessary while secure service is working (waiting for secure hardware IRQ as an example), the method you mentioned may be involved (special return value with an NS IRQ notification). This functionality is not in place right now. > > -Ken > >> -----Original Message----- >> From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, >> Alan via TF-M >> Sent: Sunday, February 3, 2019 9:17 AM >> To: tf-m(a)lists.trustedfirmware.org >> Subject: [Tf-m] Non-secure Client Management >> >> Regarding the Non-secure Client Management proposal: >> >> >> https://developer.trustedfirmware.org/w/tf_m/design/ns_client_management/ >> >> I notice that the veneers for the proposed APIs are in s_veneers.o. Does this >> mean that the proposal has been adopted and implemented? Is it functional in >> the current feature-ipc branch? >> >> I have a question about the TZ_LoadContext_S() and TZ_StoreContext_S() APIs: >> Is it expected that each context switch in the NS world will be signaled by calls to >> each of these APIs indicating the "entering" context and "leaving" context >> respectively? If so, then why not collapse these two APIs into one called >> TZ_SwitchContext__S() and pass both the "entering" and "leaving" >> TZ_MemoryId_t's as arguments? >> >> Or is TZ_StoreContext_S() only to be called when a NS context will never call into >> the SPM again? If that is the case, why isn't TZ_FreeModuleContext_S() >> sufficient? >> >> Regarding the "Concurrent secure service requests" discussion, what does "a >> non-secure client is blocked on an asynchronous secure service completion"? >> Would this be achieved by a special return status from psa_call() indicating that >> the current service request is in process and will complete later on? The psa_call() >> calling thread would then block on a semaphore that would be released by a >> dedicated NS IRQ interrupt? Is any of this functionality in place yet? >> >> Alan >> -- >> TF-M mailing list >> TF-M(a)lists.trustedfirmware.org >> https://lists.trustedfirmware.org/mailman/listinfo/tf-m > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 9 months

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Re: [Tf-m] Non-secure Client Management

by Ken Liu (Arm Technology China)

Hi Alan, The proposed APIs are implemented for library mode. It will not work under IPC mode in 'feature-ipc' branch. The support of NSPM for IPC will come later. The TZ_LoadContext_S() and TZ_StoreContext_S() need to be called every time while secure service accessed NS thread get entering/leaving. It is not combined into one function, because not all NS threads need to access secure service. For those NS threads which do not need to access secure service, these TZ_ APIs are unnecessary to be called. For example, if NS scheduler switches from one secure service accessed thread into the other generic thread, only TZ_StoreContext_S() needs to be called before context switching. The method of blocking the caller client is based on scenarios. If there are some 'wait' is necessary while secure service is working (waiting for secure hardware IRQ as an example), the method you mentioned may be involved (special return value with an NS IRQ notification). This functionality is not in place right now. -Ken > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, > Alan via TF-M > Sent: Sunday, February 3, 2019 9:17 AM > To: tf-m(a)lists.trustedfirmware.org > Subject: [Tf-m] Non-secure Client Management > > Regarding the Non-secure Client Management proposal: > > > https://developer.trustedfirmware.org/w/tf_m/design/ns_client_management/ > > I notice that the veneers for the proposed APIs are in s_veneers.o. Does this > mean that the proposal has been adopted and implemented? Is it functional in > the current feature-ipc branch? > > I have a question about the TZ_LoadContext_S() and TZ_StoreContext_S() APIs: > Is it expected that each context switch in the NS world will be signaled by calls to > each of these APIs indicating the "entering" context and "leaving" context > respectively? If so, then why not collapse these two APIs into one called > TZ_SwitchContext__S() and pass both the "entering" and "leaving" > TZ_MemoryId_t's as arguments? > > Or is TZ_StoreContext_S() only to be called when a NS context will never call into > the SPM again? If that is the case, why isn't TZ_FreeModuleContext_S() > sufficient? > > Regarding the "Concurrent secure service requests" discussion, what does "a > non-secure client is blocked on an asynchronous secure service completion"? > Would this be achieved by a special return status from psa_call() indicating that > the current service request is in process and will complete later on? The psa_call() > calling thread would then block on a semaphore that would be released by a > dedicated NS IRQ interrupt? Is any of this functionality in place yet? > > Alan > -- > TF-M mailing list > TF-M(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 9 months

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Non-secure Client Management

by DeMars, Alan

Regarding the Non-secure Client Management proposal: https://developer.trustedfirmware.org/w/tf_m/design/ns_client_management/ I notice that the veneers for the proposed APIs are in s_veneers.o. Does this mean that the proposal has been adopted and implemented? Is it functional in the current feature-ipc branch? I have a question about the TZ_LoadContext_S() and TZ_StoreContext_S() APIs: Is it expected that each context switch in the NS world will be signaled by calls to each of these APIs indicating the "entering" context and "leaving" context respectively? If so, then why not collapse these two APIs into one called TZ_SwitchContext__S() and pass both the "entering" and "leaving" TZ_MemoryId_t's as arguments? Or is TZ_StoreContext_S() only to be called when a NS context will never call into the SPM again? If that is the case, why isn't TZ_FreeModuleContext_S() sufficient? Regarding the "Concurrent secure service requests" discussion, what does "a non-secure client is blocked on an asynchronous secure service completion"? Would this be achieved by a special return status from psa_call() indicating that the current service request is in process and will complete later on? The psa_call() calling thread would then block on a semaphore that would be released by a dedicated NS IRQ interrupt? Is any of this functionality in place yet? Alan

6 years, 9 months

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IRQ handling by Secure Partitions proposal

by DeMars, Alan

Regarding the "SPM behavior" discussion in the "Secure Partition Interrupt Handling" proposal: 1) What is meant by the SPM "Acknowledges the interrupt"? I understand "masks the hardware interrupt line" but I don't see how the SPM can know how to acknowledge a particular peripheral's interrupt. I think acknowledging the interrupt should be done by the "Partition ISR" dedicated to the interrupt, or within the corresponding SP's main loop upon return from psa_wait(). 2) What does "Sets up execution environment for the secure partition" mean, precisely? 3) Can you expand on the "Execute Partition ISR" paragraph a little? I assume you mean that, for instance, the registered UART1_isr() function is called. The discussion of the ISR stack frame I don't really follow. And from the description, I'm not sure when the SP is scheduled to run again to deal with the ISR it was waiting for. 4) A secure partition that depends on an interrupt begs the question of what happens to the NS thread that has called into the SP requesting some service that depends on a subsequent asynchronous event (ISR) to complete the request. The psa_call() function as currently implemented doesn't "block" in the traditional OS sense (ie the thread's context and state are not saved in a manner that allows another task thread to run while the psa_call() is stalled in the SPM waiting for an ISR. 5) The details of SP thread pre-emption and re-entrancy need to be described. Alan

6 years, 9 months

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Re: [Tf-m] Required GCC tools for reference implementation

by Tamas Ban

There is an ongoing activity to merge the feature-ipc branch to master. Tamas -----Original Message----- From: DeMars, Alan <ademars(a)ti.com> Sent: 01 February 2019 23:16 To: Tamas Ban <Tamas.Ban(a)arm.com> Cc: nd <nd(a)arm.com> Subject: RE: Required GCC tools for reference implementation Excellent! Will this change be merged into the feature-ipc branch soon? Alan -----Original Message----- From: TF-M [mailto:tf-m-bounces@lists.trustedfirmware.org] On Behalf Of Tamas Ban via TF-M Sent: Friday, February 01, 2019 2:01 PM To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: [EXTERNAL] Re: [Tf-m] Required GCC tools for reference implementation Hi Alan, Since this change the GNUARM v7.3 also supported: https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/421/ Tamas -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 01 February 2019 20:59 To: tf-m(a)lists.trustedfirmware.org Subject: [Tf-m] Required GCC tools for reference implementation Is there a compelling reason that the reference implementation of the PSA requires the use of the gcc-arm-none-eabi-6-2017-q1-update gnu tools? The linker in these tools generates a non-standard s_veneers.o file that cannot be consumed by some CLANG linkers. It should be a relocatable object file with absolute symbols, but instead it's static executable file. If I use a newer GCC linker (ie: gcc-arm-none-eabi-7-2017-q4-major) for the final link of the secure image, the generated s_veneers.o file is of the correct type. Alan DeMars -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 9 months

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Re: [Tf-m] Required GCC tools for reference implementation

by Tamas Ban

Hi Alan, Since this change the GNUARM v7.3 also supported: https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/421/ Tamas -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of DeMars, Alan via TF-M Sent: 01 February 2019 20:59 To: tf-m(a)lists.trustedfirmware.org Subject: [Tf-m] Required GCC tools for reference implementation Is there a compelling reason that the reference implementation of the PSA requires the use of the gcc-arm-none-eabi-6-2017-q1-update gnu tools? The linker in these tools generates a non-standard s_veneers.o file that cannot be consumed by some CLANG linkers. It should be a relocatable object file with absolute symbols, but instead it's static executable file. If I use a newer GCC linker (ie: gcc-arm-none-eabi-7-2017-q4-major) for the final link of the secure image, the generated s_veneers.o file is of the correct type. Alan DeMars -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 9 months

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Required GCC tools for reference implementation

by DeMars, Alan

Is there a compelling reason that the reference implementation of the PSA requires the use of the gcc-arm-none-eabi-6-2017-q1-update gnu tools? The linker in these tools generates a non-standard s_veneers.o file that cannot be consumed by some CLANG linkers. It should be a relocatable object file with absolute symbols, but instead it's static executable file. If I use a newer GCC linker (ie: gcc-arm-none-eabi-7-2017-q4-major) for the final link of the secure image, the generated s_veneers.o file is of the correct type. Alan DeMars

6 years, 9 months

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[TF-M] How to run PSA API compliance tests with TF-M SST service

by Marc Moreno Berengue

Hi all, The Secure Storage (SST) service has been updated to align it with the PSA Protected Storage APIs version 1.0. There are a set of patches which implements this change. Please, find more information about those changes in the following ticket: https://developer.trustedfirmware.org/T218 It's possible to run the PSA API Compliance tests (https://github.com/ARM-software/psa-arch-tests/tree/master/api-tests/dev_ap…) with the TF-M SST service by following the instructions below. (The instructions assume that psa-arch-tests and trusted-firmware-m directories are at the same level in the filesystem): 1. Checkout https://github.com/ARM-software/psa-arch-tests/ 2. Checkout https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/589/ 3. Copy the `interface/include/psa_protected_storage.h` to `interface/include/psa/protected_storage.h` as this is the header name expected by the PSA API Compliance tests 4. Build the SST tests for the PSA API compliance as described in the `psa-arch-tests/api-tests` for one of the supported targets, providing the include path of the TF-M interface (i.e. trusted-firmware-m/interface/include). Set crypto and internal trusted storage as not implemented in `psa-arch-tests/api-tests/platform/targets/<TARGET_NAME>/Makefile`. Set PSA_CRYPTO_IMPLEMENTED:=0 and PSA_INTERNAL_TRUSTED_STORAGE_IMPLEMENTED:=0 * The list of tests being run is specified in the file `psa-arch-tests/api-tests/dev_apis/protected_storage/testsuite.db` * For example, this command will build the tests for AN521 "./tools/scripts/setup.sh --target tgt_dev_apis_tfm_an521 --toolchain ARMCLANG --cpu_arch armv8m_ml --verbose 2 --suite protected_storage --include ../../trusted-firmware-m/interface/include --archive_tests" 5. Build TF-M by using the ConfigPsaApiTest.cmake, enabling the PSA API Compliance tests for SST service by adding the following cmake switch during the configuration step: "-DPSA_API_TEST_SECURE_STORAGE=ON" * For example, this command will build the TF-M + NS app with PSA API Protected Storage tests for AN521 "cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink -f ../ConfigPsaApiTest.cmake` -DTARGET_PLATFORM=AN521 -DCOMPILER=ARMCLANG -DPSA_API_TEST_SECURE_STORAGE=ON ../" This will make our NS test app run a subset of the PSA API compliance tests for SST service. Thanks, Marc Moreno

6 years, 9 months

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How to run PSA API compliance tests with TF-M Crypto

by Antonio De Angelis

Hi all, It's possible to run a subset of the PSA API Compliance tests with the TF-M Crypto service by following the instructions below (it assumes that psa-arch-tests and trusted-firmware-m directories are at the same level in the filesystem): 1. Checkout https://github.com/ARM-software/psa-arch-tests/tree/ew_beta0 (ew_beta0 branch of the PSA API Compliance tests repo) 2. Checkout https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/561/ 3. Copy the interface/include/psa_crypto.h to interface/include/psa/crypto.h as this is the header name expected by the PSA API Compliance tests 4. Build the Crypto tests for the PSA API compliance as described in the psa-arch-tests/api-tests for one of the supported targets, providing the include path of the TF-M interface (i.e. trusted-firmware-m/interface/include) * The list of tests being run is specified in the file psa-arch-tests/api-tests/dev_apis/crypto/testsuite.db * For example, this command will build the tests for AN521 "./tools/scripts/setup.sh --target tgt_dev_apis_tfm_an521 --toolchain ARMCLANG --cpu_arch armv8m_ml --verbose 2 --suite crypto --include ../../trusted-firmware-m/interface/include --archive_tests" 5. Build TF-M by using the ConfigPsaApiTest.cmake, enabling the PSA API Compliance tests for Crypto by adding the following cmake switch during the configuration step: "-DPSA_API_TEST_CRYPTO=ON" * For example, this command will build the TF-M + NS app with PSA API Crypto tests for AN521 "cmake -G"Unix Makefiles" -DPROJ_CONFIG=`readlink -f ../ConfigPsaApiTest.cmake` -DTARGET_PLATFORM=AN521 -DCOMPILER=ARMCLANG -DPSA_API_TEST_CRYPTO=ON ../" This will make our NS test app run a subset of the PSA API compliance tests for Crypto. We are currently working on fixing the remaining failures. Thanks, Antonio

6 years, 9 months

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IPC patches merged into branch 'feature-ipc'

by Ken Liu (Arm Technology China)

Hi Subscribers, Group of IPC patches has been merged into branch 'feature-ipc'. The features are: * PSA Firmware Framework API (based on scheduler and message queue) and example partitions. * Isolation level 1 * Verified on AN521 You can find the design link here: https://developer.trustedfirmware.org/w/tf_m/design/ipc_design/ Some issues are identified and need to be solved. We will publish the list of improvements soon. Any feedback please mail to tf-m(a)lists.trustedfirmware.org<mailto:tf-m@lists.trustedfirmware.org> You can also create questions and issues at https://developer.trustedfirmware.org Thanks. -Ken

6 years, 9 months

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Re: [Tf-m] Replace custom code generating scripts with Jinja2

by Ken Liu (Arm Technology China)

Hi Mate, Thanks for the proposal. It looks nice. I have read the "Improvements over the current solution" part and I think the "More advanced functionality" is the point I am interested in. There are some necessary jobs to be done in the code generating scripts for IPC; hope using this tool could help on that. One thing we are investigating is: * We need to put PSA RoT and APP RoT into different groups in linker script; current tool just put all partitions together and ignores partition type. Can you help to check if the new tool could make this change easier? Thanks. -Ken ________________________________ From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> on behalf of Mate Toth-Pal via TF-M <tf-m(a)lists.trustedfirmware.org> Sent: Monday, January 21, 2019 8:37:58 PM To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: [Tf-m] Replace custom code generating scripts with Jinja2 Hi All, Based on the design proposal published here: https://developer.trustedfirmware.org/w/tf_m/design/code_generation_with_ji… I am planning to replace the code generation tool currently used in the TF-M with the Jinja2 template engine. I already prepared the change that implements this. It is available for review and testing in this gerrit review: https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/507/ Please note, that this introduces a new tool dependency: jinja2 v2.10 python library have to be installed to generate code from the partition manifests. Earlier than 2.10 versions won't work, as one of the templates relies on the namespace feature introduced in this version. Based on this change I also would like to make the secure sct files automatically generated (just like the secure ld files). The gerrit review for this change is here: https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/509/ Should you have any questions, suggestions, objections, please do not hesitate to contact! Thanks, Mate -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 9 months

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Replace custom code generating scripts with Jinja2

by Mate Toth-Pal

Hi All, Based on the design proposal published here: https://developer.trustedfirmware.org/w/tf_m/design/code_generation_with_ji… I am planning to replace the code generation tool currently used in the TF-M with the Jinja2 template engine. I already prepared the change that implements this. It is available for review and testing in this gerrit review: https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/507/ Please note, that this introduces a new tool dependency: jinja2 v2.10 python library have to be installed to generate code from the partition manifests. Earlier than 2.10 versions won't work, as one of the templates relies on the namespace feature introduced in this version. Based on this change I also would like to make the secure sct files automatically generated (just like the secure ld files). The gerrit review for this change is here: https://review.trustedfirmware.org/#/c/trusted-firmware-m/+/509/ Should you have any questions, suggestions, objections, please do not hesitate to contact! Thanks, Mate

6 years, 9 months

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Re: [Tf-m] ARM.TFM CMSIS pack questions

by Darshpreet Sabharwal

Hi Thomas >> Is there any work in progress on updating the TFM CMSIS Pack to use the updated TFM sources? Yes, we are aiming to release an updated TF-M pack this month with updated TF-M source code. Regards Darshpreet -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M Sent: 09 January 2019 15:45 To: tf-m(a)lists.trustedfirmware.org Subject: Re: [Tf-m] ARM.TFM CMSIS pack questions Thanks Antonio, I now think I know what the dependency on CMSIS 5.2.0 is. In tfm_id_mngr_dummy.c, which seems to have been removed recently, there are a couple of calls into private functions of the RTX5 library which are declared "static" in the later versions of CMSIS, and this causes link errors when using later versions of CMSIS. Is there any work in progress on updating the TFM CMSIS Pack to use the updated TFM sources? Thanks, Thomas Den 2019-01-08 kl. 15:20, skrev Antonio De Angelis via TF-M: > Hi Thomas, > > After this patch has been merged in November: > http://git.trustedfirmware.org/trusted-firmware-m.git/commit/?id=2b328 > e94bcae2d762169bd30f3d7ebc0c2880b5b > > We don't have any reliance on CMSIS 5.2.0 internals anymore and we use only the public CMSIS interface in the Non-Secure API. As a result, I don't see any reason now that stops us from using newer versions of CMSIS. I have actually tried to build TF-M and run regression using CMSIS 5.3.0 and it works as expected. Can you try to see if you're able to build with CMSIS 5.5.0 as well? In case you see issues, I should be able to have a look to understand them better and come with a solution. > > Thanks, > Antonio > > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of > Thomas Törnblom via TF-M > Sent: 07 January 2019 11:48 > To: tf-m(a)lists.trustedfirmware.org > Subject: [Tf-m] ARM.TFM CMSIS pack questions > > Greetings! > > I am working on adding support for IAR Embedded Workbench for ARM > (EWARM) to the ARM.TFM.1.1.0 CMSIS Pack and in the ReadMe.txt file in the pack there is a list of limitations, of which I would like an explanation for the following: > --- > 2. The Non-Secure API supports CMSIS 5.2.0 version only. > --- > > What specifically requires version 5.2.0 that would not work with a later version? > > The problem is that I've run across some issues that needs fixing in the ARM.CMSIS pack as well, so I've fixed these in the upcoming 5.5.0 version and would like to know what the issues are using this version with TFM? > > Thanks, > /Thomas > -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems> -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 9 months

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Re: [Tf-m] ARM.TFM CMSIS pack questions

by Thomas Törnblom

Thanks Antonio, I now think I know what the dependency on CMSIS 5.2.0 is. In tfm_id_mngr_dummy.c, which seems to have been removed recently, there are a couple of calls into private functions of the RTX5 library which are declared "static" in the later versions of CMSIS, and this causes link errors when using later versions of CMSIS. Is there any work in progress on updating the TFM CMSIS Pack to use the updated TFM sources? Thanks, Thomas Den 2019-01-08 kl. 15:20, skrev Antonio De Angelis via TF-M: > Hi Thomas, > > After this patch has been merged in November: > http://git.trustedfirmware.org/trusted-firmware-m.git/commit/?id=2b328e94bc… > > We don't have any reliance on CMSIS 5.2.0 internals anymore and we use only the public CMSIS interface in the Non-Secure API. As a result, I don't see any reason now that stops us from using newer versions of CMSIS. I have actually tried to build TF-M and run regression using CMSIS 5.3.0 and it works as expected. Can you try to see if you're able to build with CMSIS 5.5.0 as well? In case you see issues, I should be able to have a look to understand them better and come with a solution. > > Thanks, > Antonio > > -----Original Message----- > From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M > Sent: 07 January 2019 11:48 > To: tf-m(a)lists.trustedfirmware.org > Subject: [Tf-m] ARM.TFM CMSIS pack questions > > Greetings! > > I am working on adding support for IAR Embedded Workbench for ARM > (EWARM) to the ARM.TFM.1.1.0 CMSIS Pack and in the ReadMe.txt file in the pack there is a list of limitations, of which I would like an explanation for the following: > --- > 2. The Non-Secure API supports CMSIS 5.2.0 version only. > --- > > What specifically requires version 5.2.0 that would not work with a later version? > > The problem is that I've run across some issues that needs fixing in the ARM.CMSIS pack as well, so I've fixed these in the upcoming 5.5.0 version and would like to know what the issues are using this version with TFM? > > Thanks, > /Thomas > -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>

6 years, 9 months

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Re: [Tf-m] ARM.TFM CMSIS pack questions

by Antonio De Angelis

Hi Thomas, After this patch has been merged in November: http://git.trustedfirmware.org/trusted-firmware-m.git/commit/?id=2b328e94bc… We don't have any reliance on CMSIS 5.2.0 internals anymore and we use only the public CMSIS interface in the Non-Secure API. As a result, I don't see any reason now that stops us from using newer versions of CMSIS. I have actually tried to build TF-M and run regression using CMSIS 5.3.0 and it works as expected. Can you try to see if you're able to build with CMSIS 5.5.0 as well? In case you see issues, I should be able to have a look to understand them better and come with a solution. Thanks, Antonio -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Thomas Törnblom via TF-M Sent: 07 January 2019 11:48 To: tf-m(a)lists.trustedfirmware.org Subject: [Tf-m] ARM.TFM CMSIS pack questions Greetings! I am working on adding support for IAR Embedded Workbench for ARM (EWARM) to the ARM.TFM.1.1.0 CMSIS Pack and in the ReadMe.txt file in the pack there is a list of limitations, of which I would like an explanation for the following: --- 2. The Non-Secure API supports CMSIS 5.2.0 version only. --- What specifically requires version 5.2.0 that would not work with a later version? The problem is that I've run across some issues that needs fixing in the ARM.CMSIS pack as well, so I've fixed these in the upcoming 5.5.0 version and would like to know what the issues are using this version with TFM? Thanks, /Thomas -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems> -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 9 months

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ARM.TFM CMSIS pack questions

by Thomas Törnblom

Greetings! I am working on adding support for IAR Embedded Workbench for ARM (EWARM) to the ARM.TFM.1.1.0 CMSIS Pack and in the ReadMe.txt file in the pack there is a list of limitations, of which I would like an explanation for the following: --- 2. The Non-Secure API supports CMSIS 5.2.0 version only. --- What specifically requires version 5.2.0 that would not work with a later version? The problem is that I've run across some issues that needs fixing in the ARM.CMSIS pack as well, so I've fixed these in the upcoming 5.5.0 version and would like to know what the issues are using this version with TFM? Thanks, /Thomas -- *Thomas Törnblom*, /Product Engineer/ IAR Systems AB Box 23051, Strandbodgatan 1 SE-750 23 Uppsala, SWEDEN Mobile: +46 76 180 17 80 Fax: +46 18 16 78 01 E-mail: thomas.tornblom(a)iar.com <mailto:thomas.tornblom@iar.com> Website: www.iar.com <http://www.iar.com> Twitter: www.twitter.com/iarsystems <http://www.twitter.com/iarsystems>

6 years, 9 months

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TF-m Musca_A Tickets

by murat＠za-ya.co

Hi all, We are trying to run the TF-m on Musca-A board, but we have found some blocker issues * T-165: Musca A wrong offset for Secure/NonSecure ROM Alias <https://developer.trustedfirmware.org/T165> * T-166: Is it missing to initialise the MPC for Non-Secure QSPI address range? <https://developer.trustedfirmware.org/T166> Once we apply the fixes mentioned in the tickets, TF-m works well on Musca Board so, could you please review tickets, we might create PRs for them. Best Regards. Murat Cakmak

6 years, 10 months

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IPC design and implementation ready for review

by Ken Liu (Arm Technology China)

Hi folks, The IPC design and implementation for PSA API are now pushed for review. This design showcases: - PSA Firmware Framework compatible IPC implementation You can find the design document here: https://developer.trustedfirmware.org/w/tf_m/design/ipc_design/ And issue tracker with gerrit items commented: https://developer.trustedfirmware.org/T113 Discussion and review comments are welcome. We will continue work on IPC topics for missing pieces. Thanks. -Ken

6 years, 10 months

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Re: [Tf-m] Uniform secure service signature proposal

by Antonio De Angelis

Hi Miklos, thanks for the feedback. I think that having the prototype as shown below, would be very helpful from services point of view. Best regards, Antonio ________________________________ From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> on behalf of Miklos Balint via TF-M <tf-m(a)lists.trustedfirmware.org> Sent: 15 December 2018 15:39:12 To: tf-m(a)lists.trustedfirmware.org Cc: nd Subject: Re: [Tf-m] Uniform secure service signature proposal To clarify: my suggestion is to update the signature to be identical to a RoT service call: psa_status_t secure_function_name(struct psa_invec *in_vec, size_t in_len, struct psa_outvec *out_vec, size_t out_len); If that is accepted, I would update the proposal accordingly. Thanks /Miklos (wmnt) -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Miklos Balint via TF-M Sent: 15 December 2018 16:33 To: tf-m(a)lists.trustedfirmware.org Subject: Re: [Tf-m] Uniform secure service signature proposal Hi Antonio, Thanks for the comment. You are right, the return value of secure services should be explicitly typed to make its usage clear. The thought process behind the current proposal was to provide a similar look-and-feel to the psa_call( ) function in the PSA Firmware Framework, i.e. to return something that is in line with psa_status_t since, as you mentioned, PSA services are already expected to provide a status code of type psa_status_t. While the proposal failed to mention this, the restrictions present in TF-M currently for services with proprietary signatures would not apply to services with uniform signatures. So while at present services are expected to respect the reserved range of return values defined by TF-M, that would not be the case for services with uniform signatures. The analogy would be that the value provided to psa_reply() as a status code in the PSA Firmware Framework (described in version 1.0-beta-0 chapter 4.3.3 of that document) should be the return value from a secure service function with a "uniform signature" in my proposal. Mate is working on some prototype code for this change in the return value to demonstrate. Let me know if this would work for you or if anyone has additional comments related to the topic/proposal. Thanks /Miklos (wmnt) -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Antonio De Angelis via TF-M Sent: 12 December 2018 16:16 To: tf-m(a)lists.trustedfirmware.org Cc: nd <nd(a)arm.com> Subject: Re: [Tf-m] Uniform secure service signature proposal Hi Miklos/Mate, Thanks for the detailed proposal. I have a comment/question regarding the return type to be used in the unified signature. int32_t secure_function_name(struct psa_invec *in_vec, size_t in_len, struct psa_outvec *out_vec, size_t out_len); The type returned is a int32_t. As a service developer, I have to be aware that although the type returned by the service is a int32_t, there is a set of reserved return codes which are reserved by the TF-M framework and can't be used freely by the service itself (as described in interface/include/tfm_api.h through the enum tfm_status_e type, only allowed values are below the TFM_PARTITION_SPECIFIC_ERROR_MIN). As a consequence, the services right now need to define their own return type and make sure the values don't clash with the values reserved by TF-M. *Question is*: what is your opinion on explicitly marking the return type here with a dedicated type (instead of a plain int32_t) which enforces the fact that not all possible return values are usable by the service/secure function? In addition to this, in case the feedback is positive, I think that the new type we choose/define should be aligned as much as possible with the patterns of the return types used by the service API's and this would help secure service developers. Currently in fact, as TF-M is reserving return values between 0x01 and 0x1F, an intermediate translation step is required, for everything different than TFM_SUCCESS, to align the values returned by services to the values that the API's return (take again in example the Crypto service which returns psa_status_t, when the return values are propagated back to the API interface, the TFM_PARTITION_SPECIFIC_ERROR_MIN needs to be removed every time). If we define our new type as to be still based on int32_t, but with TF-M reserved values in a very high range (e.g. between -0x1F and -0x1) this would save the translation step and won't clash with the return values that are defined by the services (or, at least, this seems to be the current trend). Thanks in advance for any feedback on this observation. Thanks, Antonio -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 10 months

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IRQ handling by Secure Partitions proposal

by Miklos Balint

Hi all, Apologies. Opening a new thread for the new design proposal: Please see the following link for a design proposal on IRQ handling by Secure Partitions in TF-M: https://developer.trustedfirmware.org/w/tf_m/design/secure_partition_interr… Any comments are welcome - preferably on this thread :) Regards /Miklos (wmnt)

6 years, 10 months

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Uniform secure service signature proposal

by Miklos Balint

Hi all, Mate and myself have created a design proposal for uniform secure service signatures to provide more compatibility between PSA Firmware Framework and TF-M, to provide framework-level parameter sanitization for services and automatic non-secure callable veneer generation for the functions. https://developer.trustedfirmware.org/w/tf_m/design/uniform_secure_service_… Regards /Miklos (wmnt) IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years, 10 months

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Re: [Tf-m] Uniform secure service signature proposal

by Miklos Balint

To clarify: my suggestion is to update the signature to be identical to a RoT service call: psa_status_t secure_function_name(struct psa_invec *in_vec, size_t in_len, struct psa_outvec *out_vec, size_t out_len); If that is accepted, I would update the proposal accordingly. Thanks /Miklos (wmnt) -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Miklos Balint via TF-M Sent: 15 December 2018 16:33 To: tf-m(a)lists.trustedfirmware.org Subject: Re: [Tf-m] Uniform secure service signature proposal Hi Antonio, Thanks for the comment. You are right, the return value of secure services should be explicitly typed to make its usage clear. The thought process behind the current proposal was to provide a similar look-and-feel to the psa_call( ) function in the PSA Firmware Framework, i.e. to return something that is in line with psa_status_t since, as you mentioned, PSA services are already expected to provide a status code of type psa_status_t. While the proposal failed to mention this, the restrictions present in TF-M currently for services with proprietary signatures would not apply to services with uniform signatures. So while at present services are expected to respect the reserved range of return values defined by TF-M, that would not be the case for services with uniform signatures. The analogy would be that the value provided to psa_reply() as a status code in the PSA Firmware Framework (described in version 1.0-beta-0 chapter 4.3.3 of that document) should be the return value from a secure service function with a "uniform signature" in my proposal. Mate is working on some prototype code for this change in the return value to demonstrate. Let me know if this would work for you or if anyone has additional comments related to the topic/proposal. Thanks /Miklos (wmnt) -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Antonio De Angelis via TF-M Sent: 12 December 2018 16:16 To: tf-m(a)lists.trustedfirmware.org Cc: nd <nd(a)arm.com> Subject: Re: [Tf-m] Uniform secure service signature proposal Hi Miklos/Mate, Thanks for the detailed proposal. I have a comment/question regarding the return type to be used in the unified signature. int32_t secure_function_name(struct psa_invec *in_vec, size_t in_len, struct psa_outvec *out_vec, size_t out_len); The type returned is a int32_t. As a service developer, I have to be aware that although the type returned by the service is a int32_t, there is a set of reserved return codes which are reserved by the TF-M framework and can't be used freely by the service itself (as described in interface/include/tfm_api.h through the enum tfm_status_e type, only allowed values are below the TFM_PARTITION_SPECIFIC_ERROR_MIN). As a consequence, the services right now need to define their own return type and make sure the values don't clash with the values reserved by TF-M. *Question is*: what is your opinion on explicitly marking the return type here with a dedicated type (instead of a plain int32_t) which enforces the fact that not all possible return values are usable by the service/secure function? In addition to this, in case the feedback is positive, I think that the new type we choose/define should be aligned as much as possible with the patterns of the return types used by the service API's and this would help secure service developers. Currently in fact, as TF-M is reserving return values between 0x01 and 0x1F, an intermediate translation step is required, for everything different than TFM_SUCCESS, to align the values returned by services to the values that the API's return (take again in example the Crypto service which returns psa_status_t, when the return values are propagated back to the API interface, the TFM_PARTITION_SPECIFIC_ERROR_MIN needs to be removed every time). If we define our new type as to be still based on int32_t, but with TF-M reserved values in a very high range (e.g. between -0x1F and -0x1) this would save the translation step and won't clash with the return values that are defined by the services (or, at least, this seems to be the current trend). Thanks in advance for any feedback on this observation. Thanks, Antonio -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m

6 years, 10 months

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Re: [Tf-m] Uniform secure service signature proposal

by Miklos Balint

Hi Antonio, Thanks for the comment. You are right, the return value of secure services should be explicitly typed to make its usage clear. The thought process behind the current proposal was to provide a similar look-and-feel to the psa_call( ) function in the PSA Firmware Framework, i.e. to return something that is in line with psa_status_t since, as you mentioned, PSA services are already expected to provide a status code of type psa_status_t. While the proposal failed to mention this, the restrictions present in TF-M currently for services with proprietary signatures would not apply to services with uniform signatures. So while at present services are expected to respect the reserved range of return values defined by TF-M, that would not be the case for services with uniform signatures. The analogy would be that the value provided to psa_reply() as a status code in the PSA Firmware Framework (described in version 1.0-beta-0 chapter 4.3.3 of that document) should be the return value from a secure service function with a "uniform signature" in my proposal. Mate is working on some prototype code for this change in the return value to demonstrate. Let me know if this would work for you or if anyone has additional comments related to the topic/proposal. Thanks /Miklos (wmnt) -----Original Message----- From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Antonio De Angelis via TF-M Sent: 12 December 2018 16:16 To: tf-m(a)lists.trustedfirmware.org Cc: nd <nd(a)arm.com> Subject: Re: [Tf-m] Uniform secure service signature proposal Hi Miklos/Mate, Thanks for the detailed proposal. I have a comment/question regarding the return type to be used in the unified signature. int32_t secure_function_name(struct psa_invec *in_vec, size_t in_len, struct psa_outvec *out_vec, size_t out_len); The type returned is a int32_t. As a service developer, I have to be aware that although the type returned by the service is a int32_t, there is a set of reserved return codes which are reserved by the TF-M framework and can't be used freely by the service itself (as described in interface/include/tfm_api.h through the enum tfm_status_e type, only allowed values are below the TFM_PARTITION_SPECIFIC_ERROR_MIN). As a consequence, the services right now need to define their own return type and make sure the values don't clash with the values reserved by TF-M. *Question is*: what is your opinion on explicitly marking the return type here with a dedicated type (instead of a plain int32_t) which enforces the fact that not all possible return values are usable by the service/secure function? In addition to this, in case the feedback is positive, I think that the new type we choose/define should be aligned as much as possible with the patterns of the return types used by the service API's and this would help secure service developers. Currently in fact, as TF-M is reserving return values between 0x01 and 0x1F, an intermediate translation step is required, for everything different than TFM_SUCCESS, to align the values returned by services to the values that the API's return (take again in example the Crypto service which returns psa_status_t, when the return values are propagated back to the API interface, the TFM_PARTITION_SPECIFIC_ERROR_MIN needs to be removed every time). If we define our new type as to be still based on int32_t, but with TF-M reserved values in a very high range (e.g. between -0x1F and -0x1) this would save the translation step and won't clash with the return values that are defined by the services (or, at least, this seems to be the current trend). Thanks in advance for any feedback on this observation. Thanks, Antonio -- TF-M mailing list TF-M(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-m IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years, 10 months

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Re: [Tf-m] Uniform secure service signature proposal

by Antonio De Angelis

Hi Miklos/Mate, Thanks for the detailed proposal. I have a comment/question regarding the return type to be used in the unified signature. int32_t secure_function_name(struct psa_invec *in_vec, size_t in_len, struct psa_outvec *out_vec, size_t out_len); The type returned is a int32_t. As a service developer, I have to be aware that although the type returned by the service is a int32_t, there is a set of reserved return codes which are reserved by the TF-M framework and can't be used freely by the service itself (as described in interface/include/tfm_api.h through the enum tfm_status_e type, only allowed values are below the TFM_PARTITION_SPECIFIC_ERROR_MIN). As a consequence, the services right now need to define their own return type and make sure the values don't clash with the values reserved by TF-M. *Question is*: what is your opinion on explicitly marking the return type here with a dedicated type (instead of a plain int32_t) which enforces the fact that not all possible return values are usable by the service/secure function? In addition to this, in case the feedback is positive, I think that the new type we choose/define should be aligned as much as possible with the patterns of the return types used by the service API's and this would help secure service developers. Currently in fact, as TF-M is reserving return values between 0x01 and 0x1F, an intermediate translation step is required, for everything different than TFM_SUCCESS, to align the values returned by services to the values that the API's return (take again in example the Crypto service which returns psa_status_t, when the return values are propagated back to the API interface, the TFM_PARTITION_SPECIFIC_ERROR_MIN needs to be removed every time). If we define our new type as to be still based on int32_t, but with TF-M reserved values in a very high range (e.g. between -0x1F and -0x1) this would save the translation step and won't clash with the return values that are defined by the services (or, at least, this seems to be the current trend). Thanks in advance for any feedback on this observation. Thanks, Antonio

6 years, 10 months

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Attestation implementation proposal

by Laurence Lundblade

Hi folks, I’m a contractor doing an implementation of attestation based on EAT <https://tools.ietf.org/html/draft-mandyam-eat-01> for TF-M. Tamas asked that I post the proposed architecture here for discussion. It is in this ticket: https://developer.trustedfirmware.org/T152 LL

6 years, 11 months

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