Hello Jacky, Hello Ye,
On 07.09.23 15:49, Ahmad Fatoum wrote:
On 07.09.23 13:04, ZHIZHIKIN Andrey wrote:
From what I know, and If I read Section 4 of AN12263 [1], it is the BootROM itself that performs cache maintenance operations. The readout of whether cache is enabled has been missing on certain i.MX6 SOCs (listed in the same section), hence there was a need to inform the BootROM of those SOCs that cache is enabled. This is implemented in U-Boot commit 53c8a510e7 ("arm: imx: hab: Optimise flow of authenticate_image on hab_entry fail"), however the commit description does not explicitly states that this indication is addressed.
[snip]
Thanks! That would indeed make sense. That way barebox wouldn't discard dirty lines and U-Boot works, because it happens to have the same memory attributes as TF-A avoiding coherency loss.
A confirmation from NXP that BootROM does cache maintenance for report_status would be appreciated. Jacky?
Could you confirm that the BootROM on i.MX8M does cache maintenance internally as on i.MX6?
Thanks, Ahmad