[TF-A] Re: Does FVP_Base_RevC-2xAEMvA platform model has a full support for address translation at PL2 stage-1 MMU in aarch32?

Hi Marek,

On 08/08/2025 15:38, Marek via TF-A wrote:

Have you ever succeeded in performing a Stage-1 MMU translation using LPAE (Long Physical Address Extension) on the FVP_Base_RevC-2xAEMvA platform model running in AArch32 Hyp mode (CONFIG64=0) into any other Memory but Strongly-Ordered? [...] Is there a chance FVP_Base_RevC-2xAEMvA doesn't support the 1-stage MMU translation for anything else but Strongly-Ordered?

I don't think anyone on the team has any particular experience on this. I'm not sure if you've asked this via other channels, but I did query the model people who after a great delay have said that it is meant to work and are going to look into whether it's broken.

Thanks, Boyan