Hi Okash,
From an initial scan of the CPU TRMs, the caches (L1 I-Cache/D-Cache and/or L2 Cache) supported for "Direct access to internal memory" under this feature could be different for different CPUs. So, it is reasonable to have platform hook to do this and take of this for the caches required/applicable per the platform config and convert the "unconditional cleans and invalidates caches" that TF-A does, to something conditional to the "core power mode not equal to Debug Recovery".
We would be happy to help review any patch for this.
--Bipin