Hi Amit
To quote the TRM: "All L1 and L2 cache disabling, L1 and L2 cache flushing, and communication with the L3 memory system is performed in hardware after the WFI is executed, under the direction of the power controller."
Regards
Dan.
-----Original Message----- From: Nagal, Amit via TF-A tf-a@lists.trustedfirmware.org Sent: Tuesday, February 20, 2024 11:20 AM To: tf-a@lists.trustedfirmware.org Subject: [TF-A] L3 cache flush
Hi,
Referring https://github.com/ARM-software/arm-trusted- firmware/blob/master/lib/cpus/aarch64/aem_generic.S#L51:L53 Software cache maintenance is done till L3 .
Referring https://github.com/ARM-software/arm-trusted- firmware/blob/master/lib/cpus/aarch64/cortex_a78.S#L188:L190 for cortex a78 , it is mentioned that HW will do the cache maintenance . is HW cache maintenance done till L3 for cortex a78 case too ?
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