HI Achin,
There is no log from CPU1 when I set log level as 40. The BL31 size limitation prevent me to set log level as 50. Could you help confirm that all manifest file related packing is done in optee-os side for Cortex-A53 case? I mean nothing should checked in TF-A side for invalid manifest case. I see code just check NULL pointer and emit "Invalid or absent SPM Core manifest".
Regards, Jun
Achin Gupta Achin.Gupta@arm.com 于2021年4月22日周四 下午5:09写道：
Hi Jun,
It seems to me that OP-TEE is not initialising at all since the SPMD in EL3 cannot locate its manifest file.
This should not cause an issue when Linux later attempts to turn on secondary CPUs. Are there any TF-A logs on CPU1 at all?
cheers, Achin ________________________________ From: Jun Nie jun.nie@linaro.org Sent: 22 April 2021 08:26 To: Olivier Deprez Olivier.Deprez@arm.com Cc: tf-a@lists.trustedfirmware.org tf-a@lists.trustedfirmware.org; Achin Gupta Achin.Gupta@arm.com; Gyorgy Szing Gyorgy.Szing@arm.com; Manish Pandey2 Manish.Pandey2@arm.com Subject: Re: How does SPM impact PSCI functions?
Hi Olivier,
BTW: Below log is emitted by the LInux kernel. Does FFA logic in OPTEE impact PSCI function?
[ 0.071691] psci: failed to boot CPU1 (-95)
Regards, Jun
Jun Nie jun.nie@linaro.org 于2021年4月22日周四 下午3:17写道：
Hi Olivier,
Below are git repo, log and build option. But OPTEE log disappear after TF-A enabling SPM. I guess it is due to manifest loading failure and OPTEE is skipped in boot chain. For the OP_TEE, I ported the SPM patches on branch https://git.trustedfirmware.org/OP-TEE/optee_os.git/log/?h=psa-development, except the last one: 1ba62d4 SPMC: Pass device regions to SP. That patch introduce build failure. Thanks for your time!
https://git.linaro.org/people/jun.nie/trusted-firmware-a.git/tree/?h=imx_lf_... https://git.linaro.org/people/jun.nie/optee_os.git/tree/?h=imx_5.4.70_2.3.0%...
U-Boot SPL 2020.04 (Jan 01 1970 - 00:00:00 +0000) DDRINFO: start DRAM init DDRINFO: DRAM rate 4000MTS DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 sha256,rsa2048:dev+ ## Checking hash(es) for Image fip@1 ... sha256+ OK ## Checking hash(es) for Image atf@1 ... sha256+ OK NOTICE: BL2: v2.4(release):7f4ae6330 NOTICE: BL2: Built : 00:00:00, Jan 1 1970 INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 INFO: Loading image id=3 at address 0x940000 INFO: Image id=3 loaded: 0x940000 - 0x94f15e INFO: BL2: Loading image id 4 INFO: Loading image id=4 at address 0x56000000 INFO: Image id=4 loaded: 0x56000000 - 0x5600001c INFO: OPTEE ep=0x56000000 INFO: OPTEE header info: INFO: magic=0x4554504f INFO: version=0x2 INFO: arch=0x1 INFO: flags=0x0 INFO: nb_images=0x1 INFO: BL2: Loading image id 21 INFO: Loading image id=21 at address 0x56000000 INFO: Image id=21 loaded: 0x56000000 - 0x56098438 INFO: BL2: Skip loading image id 22 INFO: BL2: Loading image id 5 INFO: Loading image id=5 at address 0x40200000 INFO: Image id=5 loaded: 0x40200000 - 0x402decce NOTICE: BL2: Booting BL31 INFO: Entry point address = 0x940000 INFO: SPSR = 0x3cd NOTICE: BL31: v2.4(release):7f4ae6330 NOTICE: BL31: Built : 00:00:00, Jan 1 1970 INFO: GICv3 with legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: BL31: Initializing runtime services ERROR: Invalid or absent SPM Core manifest. ERROR: Error initializing runtime service std_svc INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x40200000 INFO: SPSR = 0x3c9
U-Boot 2020.04 (Jan 01 1970 - 00:00:00 +0000) CPU: i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz) CPU: Industrial temperature grade (-40C to 105C) at 31C
ATF build option: 19 PLAT=imx8mp SPD=spmd SPMD_SPM_AT_SEL2=0 \ 20 NEED_BL2=yes NEED_BL32=yes NEED_BL33=yes \ 21 BL32=${DEPLOY_DIR_IMAGE}/optee/tee-header_v2.bin \ 22 BL32_EXTRA1=${DEPLOY_DIR_IMAGE}/optee/tee-pager_v2.bin \ 23 BL33=${DEPLOY_DIR_IMAGE}/u-boot.bin \ 24 CRASH_REPORTING=1 \ 25 IMX_BOOT_UART_BASE=0x30880000 \ 26 LOG_LEVEL=40 \
OPTEE build option: 46 CFG_WITH_SP=y CFG_CORE_SEL1_SPMC=y CFG_CORE_FFA=y \ 47 CROSS_COMPILE_sp_${OPTEE_ARCH}=${HOST_PREFIX} \ 48 CFG_NXP_CAAM=y CFG_RNG_PTA=y \ 49 CFG_CORE_DYN_SHM=n CFG_DT=y CFG_EXTERNAL_DTB_OVERLAY=y CFG_DT_ADDR=0x43200000 \ 50 CFG_SPM_MM_START=0x60000000 CFG_SPM_MM_SIZE=0x2000000 \ 51 EARLY_TA_PATHS="${DEPLOY_DIR_IMAGE}/dc1eef48-b17a-4ccf-ac8b-dfcff7711b14.stripped.elf ${DEPLOY_DIR_IMAGE}/d9df52d5-16a2-4bb2-9aa4-d26d3b84e8c0.stripped.elf" \ 52 CFG_EMBED_DTB_SOURCE_FILE=${B}/../sp_manifest.dts \ 53 CFG_UART_BASE=UART3_BASE \ 54 CFG_TEE_CORE_LOG_LEVEL=3 \
Regards, Jun
Olivier Deprez Olivier.Deprez@arm.com 于2021年4月22日周四 上午12:22写道：
Hi Jun,
Can you provide the TF-A and OP-TEE git trees/branches you use? TF-A SPMD upstream expects usage of FFA_SECONDARY_EP_REGISTER FF-A v1.1 ABI that your OP-TEE version might not be using.
Also please share logs from TF-A and OP-TEE boot.
Thanks, Olivier.
From: Jun Nie jun.nie@linaro.org Sent: 21 April 2021 18:03 To: tf-a@lists.trustedfirmware.org Cc: Olivier Deprez; Achin Gupta; Gyorgy Szing; Manish Pandey2 Subject: How does SPM impact PSCI functions?
Hi,
I just find that secondary CA53 CPUs boot fail with error -95(as below definition and log) in the kernel after enabling SPM with option: SPD=spmd SPMD_SPM_AT_SEL2=0. How does SPM impact PSCI functions? Or which code lines should I check to debug this?
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
[ 0.066970] smp: Bringing up secondary CPUs ... [ 0.071681] psci: failed to boot CPU1 (-95) [ 0.075454] CPU1: failed to boot: -95 [ 0.079591] psci: failed to boot CPU2 (-95) [ 0.083308] CPU2: failed to boot: -95
Regards, Jun