Hello,
It is observed that device tree functions are present under lib/libfdt/... in Trusted Firmware-A code, but this device tree are not present in symbol table and also if we remove this device tree functions in code, board was successfully booting. However, while doing Coverity build to fix MISRA-C violations getting violations from this device tree code.
So, is it possible to leave those violations please suggest? And when it will be enabled, please suggest.
Thanks & Regards
Nithin G
Hi Everyone,
I have cancelled the TF-A techforum for latter today as we have no topic scheduled to be discussed.
Calendar cancellations have been sent.
Apologies for the late notification.
Joanna
This event has been canceled with a note:
"Cancelling as we have no topics for today. Apologies for the late
cancellation. Joanna"
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Hi
I ported TF-A and OPTEE on multi-core SoC, and I checked that xtest passed
on CPU0 without failure. However, I'm failing in secondary CPU boot, and
I'd like to get some help.
I'm using ARMv8, and I'm using spintable as CPU enable method (not using
PSCI FW). TF-A is in EL3.
What I did ...
1. I released secondary CPU reset from bl31_early_platform_setup2() during
primary CPU cold booting
- set secondary CPU's RVBAR to bl31_entrypoint
- release secondary CPU reset
2. I implemeneted plat_secondary_cold_boot_setup(), which is spining until
linux kernel updates cpu-release-addr. Once linux kernel updates
cpu-release-addr, then it changes EL to EL1 and jumps to
secondary_startup() in linux
3. But secondary core goes to panic. It seems to happen when linux invokes
optee_probe()
Should I initialize some contexts (e.g. optee ..)? If so, where should I
implement the corresponding codes? I'm wondering if I'm missing something,
and I'd like to get some advice
Thanks,
--Bin
This event has been canceled with a note:
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Hello,
Trusted Firmware-A LTS version 2.8.8 is now available. This release contains the following patches.
* ec3fafa24 fix(cpus): workaround for Neoverse V2 erratum 2801372
The readthedocs update can be found at https://trustedfirmware-a.readthedocs.io/en/lts-v2.8/change-log.html.
Thanks.
Hi Boyan,
Some questions about erratum in TF-A:
1 Why workaround's flag is 0? In my mind, all flag should be 1 because there is func to check cpu revisions,
such as check_errata_2326639.
43438ad1a patch:
+ERRATA_N2_2326639 ?=0
2 After e444763d6(shorten errata flag defines) patch, introduce CPU_FLAG_LIST,
Is the workaround's flag change to 1?
e444763d6 patch:
-ERRATA_N2_2326639 ?=0
+CPU_FLAG_LIST += ERRATA_N2_2326639
Regards,
Ming
Hi All,
I wanted to let you know that next Thursday, July 27th, the TF-A Tech Forum
will be hosting a presentation on OpenCI and MISRA presented by Paul
Sokolovski of Linaro and Roberto Bagnara from Bugseng. MISRA is being
enabled on both TF-A and TF-M in OpenCI, so sending this out to both lists
since users in both domains may be interested in the session.
Meeting time and dial up info can be found in the TF community calendar
located here: https://www.trustedfirmware.org/meetings/
Best Regards,
Don Harbin
TrustedFirmware Community Manager
don.harbin(a)linaro.org
Hi,
Typically, BL31 runs in SRAM which tends to be limited. As we add
support for newer architectural features e.g. CCA, general features
and standards, the size of BL31 image will grow and become harder to
fit in most SRAMs.
This email is to share ideas on how to address this problem.
A simple approach will be to identify parts of NOBITS ELF sections of
BL31 which can be moved out to DRAM. Since NOBITS sections aren't part
of the file image, loading and authentication code doesn't have to
change. The challenge will be to come up with some criteria to help
decide what kind of buffers can be kept in DRAM vs SRAM.
Other ideas are also welcome. Please share your thoughts.
Thanks,
Okash
Hi,
We have two topics for the upcoming TF-A Tech Forum on Jul, 13th:
Certificate signer-id retrieval - Manish Badarkhe
* Quick recap
* Authentication Mechanism
* Role of public key
* What is signer ID and its usage?
* Design of signer ID retrieval for attestation
Updates to EL3 vector entry path to cater for async EA(SError) exceptions - Manish Pandey
*
Description of error synchronization during EL3 entry.
* Go through the implementation of handling of these errors in EL3 for Firmware First Handling (FFH) scenarios.
* Reflecting it back in Kernel First Handling (KFH) scenario.
* Description of the test scenarios introduced.
Regards,
Olivier.
________________________________
From: Trusted Firmware Public Meetings
Sent: 14 June 2020 19:21
To: Trusted Firmware Public Meetings <linaro.org_havjv2figrh5egaiurb229pd8c(a)group.calendar.google.com>; tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org>
Subject: [TF-A] Invitation: TF-A Tech Forum @ Every 2 weeks from 16:00 to 17:00 on Thursday (BST) (tf-a(a)lists.trustedfirmware.org)
When: 13 July 2023 17:00-18:00.
Where:
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When
Every 2 weeks from 16:00 to 17:00 on Thursday United Kingdom Time
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Hi Manish,
I'll answer on behalf of Benjamin and Sieu because I think they are offline now.
I reached out to these guys privately this morning and they said they will post patches to fix these defects.
Cheers,
Sandrine
Hi All,
It has happened in the past that developers have posted patches for review, but have been unable to respond to the comments on those patches for a long time and hence, maintainers pitched in and abandoned the patches in such cases.
I created a patch [1] to make this official because the coding-review guidelines didn't mention it today. I would appreciate your help in reviewing this patch. Please let us know if you disagree about this approach. If you'd like, we can discuss this upcoming tech-forum.
[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/21848
Thanks,
Manish Badarkhe
This event has been canceled with a note:
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FYI to all TF dev teams leveraging Open CI.
Best regards,
Don
---------- Forwarded message ---------
From: Glen Valante via Tf-openci-triage <
tf-openci-triage(a)lists.trustedfirmware.org>
Date: Fri, 23 Jun 2023 at 08:41
Subject: [Tf-openci-triage] FYI; Cambridge Lab Down
To: tf-openci-triage(a)lists.trustedfirmware.org <
tf-openci-triage(a)lists.trustedfirmware.org>
Hello All;
FYI; the Cambridge lab took a serious power hit and is down. They are
scrambling to get things back up, but it may take all weekend.
Expect LAVA failures and other strange results.
Thanks;
-g
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This event has been updated with a note:
"Session for 27th July 2023."
Changed: description
TF-A Tech Forum
Thursday Jul 27, 2023 ⋅ 4pm – 5pm
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Topic:MISRA testing in the OpenCI with BUGSENG's ECLAIR Software
Verification PlatformPresenters:Roberto Bagnara (BUGSENG) and Paul
Sokolovskyy (Linaro)Summary:Overview of MISRA C, BUGSENG's ECLAIR Software
Verification Platformand the challenges and solutions for its deployment in
the OpenCIContinuous Integration System for the TF-A and TF-M
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Hi Varun,
* for platforms with SPMD_SPM_AT_SEL2=1. These platforms already use EHF for servicing RAS interrupts today.
Can you please have a look at https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16047 ?
and https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16047/6/docs…
The model, by the FF-A specification, is to permit G0 interrupts to trap to EL3 when NWd runs.
A G0 interrupt is routed to a SP through the SPMD/SPMC by the use of EL3-SP direct messages:
https://review.trustedfirmware.org/q/topic:%22el3_direct_msg%22+(status:ope…
When SEL1/0 runs, G0 interrupts are first trapped to SEL2 and forwarded to EL3 by the FFA_EL3_INTR_HANDLE ABI.
I appreciate the legacy capability to let G0 interrupts trap to EL3 while SWd runs is not possible/recommended with this design.
This might indeed break earlier implementations; would it make sense aligning SW stacks to the latest of the FF-A spec recommendations?
I let Raghu chime in if need be.
Regards,
Olivier.
________________________________
From: Varun Wadekar via TF-A <tf-a(a)lists.trustedfirmware.org>
Sent: 06 June 2023 13:12
To: TF-A Mailing List <tf-a(a)lists.trustedfirmware.org>
Subject: [TF-A] EHF and SPMD G0 interrupt handling issues
Hi,
We are in the process of upgrading the downstream TF-A to v2.9 for platforms with SPMD_SPM_AT_SEL2=1. These platforms already use EHF for servicing RAS interrupts today.
I noticed that v2.9 has added G0 interrupt handling support to the SPMD. But I think the SPMD support still needs some work as it does not play nicely with EHF.
I have found the following issues with the implementation.
1. SPMD and EHF both register handlers for G0 interrupts. But the interrupt management framework only allows one handler for INTR_TYPE_EL3.
2. The RAS framework still uses EHF and the SPMD interrupt handler breaks that functionality.
3. The SPMD handler calls into the platform which does not have any means to invoke the RAS interrupt handler.
IMO, we should make SPMD a client of the EHF instead of creating yet another way for interrupt handling. For now, I register SPMD's G0 interrupt handler only if EL3_EXCEPTION_HANDLING=0, as a workaround.
Thoughts?
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
5 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 5 of 5 defect(s)
** CID 385350: Control flow issues (DEADCODE)
/plat/xilinx/zynqmp/zynqmp_sdei.c: 19 in arm_validate_ns_entrypoint()
________________________________________________________________________________________________________
*** CID 385350: Control flow issues (DEADCODE)
/plat/xilinx/zynqmp/zynqmp_sdei.c: 19 in arm_validate_ns_entrypoint()
13
14 #include <plat/common/platform.h>
15 #include <platform_def.h>
16
17 int arm_validate_ns_entrypoint(uintptr_t entrypoint)
18 {
>>> CID 385350: Control flow issues (DEADCODE)
>>> Execution cannot reach the expression "-1" inside this statement: "return (entrypoint >= 42947...".
19 return ((entrypoint >= BL31_BASE) && (entrypoint < BL31_LIMIT)) ? -1 : 0;
20 }
21
22 /* Private event mappings */
23 static sdei_ev_map_t zynqmp_sdei_private[] = {
24 SDEI_DEFINE_EVENT_0(ZYNQMP_SDEI_SGI_PRIVATE),
** CID 385349: (OVERRUN)
/plat/intel/soc/common/sip/socfpga_sip_fcs.c: 1404 in intel_fcs_ecdsa_hash_sign_finalize()
________________________________________________________________________________________________________
*** CID 385349: (OVERRUN)
/plat/intel/soc/common/sip/socfpga_sip_fcs.c: 1409 in intel_fcs_ecdsa_hash_sign_finalize()
1403
1404 memcpy((uint8_t *) &payload[i], (uint8_t *) hash_data_addr,
1405 src_size);
1406
1407 i += src_size / MBOX_WORD_BYTE;
1408
>>> CID 385349: (OVERRUN)
>>> Overrunning array "payload" of 17 4-byte elements by passing it to a function which accesses it at element index 134217732 (byte offset 536870931) using argument "i" (which evaluates to 134217733).
1409 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIGN_REQ,
1410 payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
1411 &resp_len);
1412
1413 memset((void *) &fcs_ecdsa_hash_sign_param,
1414 0, sizeof(fcs_crypto_service_data));
/plat/intel/soc/common/sip/socfpga_sip_fcs.c: 1404 in intel_fcs_ecdsa_hash_sign_finalize()
1398
1399 if ((i + ((src_size) / MBOX_WORD_BYTE)) >
1400 FCS_ECDSA_HASH_SIGN_CMD_MAX_WORD_SIZE) {
1401 return INTEL_SIP_SMC_STATUS_REJECTED;
1402 }
1403
>>> CID 385349: (OVERRUN)
>>> Overrunning buffer pointed to by "(uint8_t *)&payload[i]" of 68 bytes by passing it to a function which accesses it at byte offset 536870931 using argument "src_size" (which evaluates to 536870912). [Note: The source code implementation of the function has been overridden by a builtin model.]
1404 memcpy((uint8_t *) &payload[i], (uint8_t *) hash_data_addr,
1405 src_size);
1406
1407 i += src_size / MBOX_WORD_BYTE;
1408
1409 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIGN_REQ,
** CID 385348: (OVERRUN)
/plat/intel/soc/common/sip/socfpga_sip_fcs.c: 2144 in intel_fcs_ecdh_request_finalize()
________________________________________________________________________________________________________
*** CID 385348: (OVERRUN)
/plat/intel/soc/common/sip/socfpga_sip_fcs.c: 2144 in intel_fcs_ecdh_request_finalize()
2138
2139 if ((i + ((src_size) / MBOX_WORD_BYTE)) >
2140 FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE) {
2141 return INTEL_SIP_SMC_STATUS_REJECTED;
2142 }
2143
>>> CID 385348: (OVERRUN)
>>> Overrunning buffer pointed to by "(uint8_t *)&payload[i]" of 116 bytes by passing it to a function which accesses it at byte offset 536870931 using argument "src_size" (which evaluates to 536870912). [Note: The source code implementation of the function has been overridden by a builtin model.]
2144 memcpy((uint8_t *) &payload[i], (uint8_t *) pubkey, src_size);
2145 i += src_size / MBOX_WORD_BYTE;
2146
2147 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDH_REQUEST,
2148 payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
2149 &resp_len);
/plat/intel/soc/common/sip/socfpga_sip_fcs.c: 2147 in intel_fcs_ecdh_request_finalize()
2141 return INTEL_SIP_SMC_STATUS_REJECTED;
2142 }
2143
2144 memcpy((uint8_t *) &payload[i], (uint8_t *) pubkey, src_size);
2145 i += src_size / MBOX_WORD_BYTE;
2146
>>> CID 385348: (OVERRUN)
>>> Overrunning array "payload" of 29 4-byte elements by passing it to a function which accesses it at element index 134217732 (byte offset 536870931) using argument "i" (which evaluates to 134217733).
2147 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDH_REQUEST,
2148 payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
2149 &resp_len);
2150
2151 memset((void *)&fcs_ecdh_request_param, 0,
2152 sizeof(fcs_crypto_service_data));
** CID 385347: Control flow issues (NO_EFFECT)
/plat/xilinx/zynqmp/zynqmp_sdei.c: 19 in arm_validate_ns_entrypoint()
________________________________________________________________________________________________________
*** CID 385347: Control flow issues (NO_EFFECT)
/plat/xilinx/zynqmp/zynqmp_sdei.c: 19 in arm_validate_ns_entrypoint()
13
14 #include <plat/common/platform.h>
15 #include <platform_def.h>
16
17 int arm_validate_ns_entrypoint(uintptr_t entrypoint)
18 {
>>> CID 385347: Control flow issues (NO_EFFECT)
>>> This less-than-zero comparison of an unsigned value is never true. "entrypoint < 0UL".
19 return ((entrypoint >= BL31_BASE) && (entrypoint < BL31_LIMIT)) ? -1 : 0;
20 }
21
22 /* Private event mappings */
23 static sdei_ev_map_t zynqmp_sdei_private[] = {
24 SDEI_DEFINE_EVENT_0(ZYNQMP_SDEI_SGI_PRIVATE),
** CID 385346: (OVERRUN)
/plat/intel/soc/common/sip/socfpga_sip_fcs.c: 1505 in intel_fcs_ecdsa_hash_sig_verify_finalize()
________________________________________________________________________________________________________
*** CID 385346: (OVERRUN)
/plat/intel/soc/common/sip/socfpga_sip_fcs.c: 1510 in intel_fcs_ecdsa_hash_sig_verify_finalize()
1504
1505 memcpy((uint8_t *) &payload[i],
1506 (uint8_t *) hash_sig_pubkey_addr, src_size);
1507
1508 i += (src_size / MBOX_WORD_BYTE);
1509
>>> CID 385346: (OVERRUN)
>>> Overrunning array "payload" of 52 4-byte elements by passing it to a function which accesses it at element index 134217732 (byte offset 536870931) using argument "i" (which evaluates to 134217733).
1510 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIG_VERIFY,
1511 payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
1512 &resp_len);
1513
1514 memset((void *)&fcs_ecdsa_hash_sig_verify_param,
1515 0, sizeof(fcs_crypto_service_data));
/plat/intel/soc/common/sip/socfpga_sip_fcs.c: 1505 in intel_fcs_ecdsa_hash_sig_verify_finalize()
1499
1500 if ((i + ((src_size) / MBOX_WORD_BYTE)) >
1501 FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE) {
1502 return INTEL_SIP_SMC_STATUS_REJECTED;
1503 }
1504
>>> CID 385346: (OVERRUN)
>>> Overrunning buffer pointed to by "(uint8_t *)&payload[i]" of 208 bytes by passing it to a function which accesses it at byte offset 536870931 using argument "src_size" (which evaluates to 536870912). [Note: The source code implementation of the function has been overridden by a builtin model.]
1505 memcpy((uint8_t *) &payload[i],
1506 (uint8_t *) hash_sig_pubkey_addr, src_size);
1507
1508 i += (src_size / MBOX_WORD_BYTE);
1509
1510 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIG_VERIFY,
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
Hi,
We are in the process of upgrading the downstream TF-A to v2.9 for platforms with SPMD_SPM_AT_SEL2=1. These platforms already use EHF for servicing RAS interrupts today.
I noticed that v2.9 has added G0 interrupt handling support to the SPMD. But I think the SPMD support still needs some work as it does not play nicely with EHF.
I have found the following issues with the implementation.
1. SPMD and EHF both register handlers for G0 interrupts. But the interrupt management framework only allows one handler for INTR_TYPE_EL3.
2. The RAS framework still uses EHF and the SPMD interrupt handler breaks that functionality.
3. The SPMD handler calls into the platform which does not have any means to invoke the RAS interrupt handler.
IMO, we should make SPMD a client of the EHF instead of creating yet another way for interrupt handling. For now, I register SPMD's G0 interrupt handler only if EL3_EXCEPTION_HANDLING=0, as a workaround.
Thoughts?
I am working on qemu_sbsa platform. We are now adding a way to share
data from QEMU via TF-A to EDK2. Standard Arm way - using Secure Monitor
Calls.
I checked how other platforms do it and wrote a patch [1]. It got
reviews, went through CI and all is fine except one thing:
New source files have been identified in your patch..
plat/qemu/qemu_sbsa/sbsa_sip_svc.c
1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20871
I have read TF-A documentation linked to CI report. This new file is
covered already by PLAT=qemu_sbsa build because it is not optional. How
to make CI pass?
Same problem is with second patch [2] where I added another new source file.
2. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20953
This event has been updated with a note:
"Update for Techforum tomorrow...."
Changed: description
TF-A Tech Forum
Thursday Jun 1, 2023 ⋅ 4pm – 5pm
United Kingdom Time
Topic: SVE Enablement in RMM for Realms. Presenter: Arunachalam
GanapathyOverview: This discussion will cover the design and implementation
details on how SVE and FP/AdvSIMD state of Non secure world and Realms are
managed by RMM.=====================We run an open technical forum call for
anyone to participate and it is not restricted to Trusted Firmware project
members. It will operate under the guidance of the TF TSC. Feel free to
forward this invite to colleagues. Invites are via the TF-A mailing list
and also published on the Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
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Hi All,
We are pleased to announce the formal release of Trusted Firmware-A version 2.9 bundle of project deliverables.
This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium and TF-A OpenCI Scripts/Jobs 2.9 releases involving the tagging of multiple repositories. Aligned but not yet part of the release is Trusted Firmware-A Realm Management Monitor v0.3.0.
These went live on 23rd May 2023.
I would like to thank all of the contributors for their excellent work and achievements since the last release.
Thanks Joanna
Notable Features of the Version 2.9 Release are as follows:
TF-A/EL3 Root World
* New Features:
* Support for PSCI OS initiated mode
* Architecture feature support for FEAT_TCR2, FEAT_GCS, FEAT_HCX, FEAT_SME2, FEAT_PIE/POR, FEAT_MPAM.
* System registers access trap handler
* Introduction to dynamic detection of features
* Refactoring:
* Context management
* RAS extension exception handling and crash reporting.
* Distinguish between BL2 as TF-A entry point or BL2 running at EL3 exception level.
* General Support
* CPU Support for Chaberton and Blackhawk for TC2023
* Eighteen (18) Errata Mitigations for Cortex X2/X3/A710/A510/A78/A78C and Neoverse N2/V1 family CPU’S
* Errata Management Firmware Interface implementation supported for version 1.0 of the public specification
TF-A Boot BL1/BL2
* New Feature/Support
* Support for Trusted Boot rooted into RSS RoT on TC2022 platform.
* Support for PSA attestation scheme with Measured Boot rooted into RSS on TC2022 platform
* Migration to mbedTLS 3.x as the default cryptography library retaining backwards compatibility with mbedTLS 2.x
* Improvements and hardening of Arm CCA boot and attestation support.
* Hardening efforts in the X.509 certificate parser, including a security fix (TFV-10 CVE-2022-47630)
Hafnium/SEL2 SPM
* FF-A v1.2 ALP0 Specification Early Adoption Support
* Implemented ppartition info get ABI using GP registers.
* Group0 secure interrupt handling delegation.
* Improved console log ABI.
* FF-A v1.1 REL0 Specification Support
* Interrupt handling (S-EL0 partition signalling, added action to Other-S-Int, allow a physical interrupt to be routed to a specified PE).
* Memory sharing (structures updates supporting FF-A backwards compatibility, share/lend/donate memory to multiple borrowers, normal/secure fragmented memory sharing).
* Power management (events relayed to the SPMC and removed limitations).
* Indirect messaging (buffer synchronization and ownership transfer rules).
* General Support
* SPMC manifest to declare non-secure and secure system memory address ranges.
* Hardened SP manifest memory regions boot time validation.
* CI migration to LLVM/clang 15.0.6
* Removal of non-VHE build and test configurations.
* Added EL3 SPMC test configurations using the Hafnium's CI infrastructure.
TF-A Tests
* New Test Support
* Errata Management Firmware Interface testing
* FF-A v1.1 feature testing
* Realm Management Extension feature testing
* New Architecture Specific feature testing related to v8.8
* 1 new platform port (RD-N2-Cfg3)
TF-RMM/REL2
* New Feature/Support
* Added support to create Realms which can make use of SVE, if present in hardware.
* Refactor and improved the Stage 1 translation table library lib/xlat API to better fit RMM usage.
* Add PMU support for Realms as described by RMM v1.0 Beta0 specification.
* Support getting DRAM info from the Boot manifest dynamically at runtime.
* RMM can now support the 2nd DDR bank on FVP
* Define a unit test framework using CppUTest for RMM.
* Added unit tests for granule, slot-buffer and Stage 1 translation table lib xlat.
* Improvements to fake-host and unit tests framework.
* Build improvements in RMM
Platform Support
* 1 new platform added, the Allwinner T507 SoC
* 26 platforms updated from 14 providers
* 17 different driver updates
OpenCI
* First release done solely relying on Trustedfirmware.org OpenCI
Patch Statistics Across all Repositories
* 1403 Patches merged since v2.8 November 2022 release
Please refer to the TF-A [1], Hafnium [2] and TF-A Tests [3] changelogs for the complete summary of changes from the previous release.
TF-A [4], TF-A Test [5], Hafnium [6], TF-A OpenCI Scripts [7] and TF-A OpenCI Jobs [8] repositories are available along with the compatible TF-RMM repository [9] and changelog [10].
[1] https://trustedfirmware-a.readthedocs.io/en/v2.9/change-log.html#id1
[2] https://review.trustedfirmware.org/plugins/gitiles/hafnium/hafnium/+/HEAD/d…
[3] https://trustedfirmware-a-tests.readthedocs.io/en/v2.9/change-log.html#vers…
[4] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tag/?h=v2.9
[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tag/?h=v2.9
[6] https://git.trustedfirmware.org/hafnium/hafnium.git/tag/?h=v2.9
[7] https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tag/?h=v2.9
[8] https://git.trustedfirmware.org/ci/tf-a-job-configs.git/tag/?h=v2.9
[9] https://git.trustedfirmware.org/TF-RMM/tf-rmm.git/tag/?h=tf-rmm-v0.3.0
[10] https://tf-rmm.readthedocs.io/en/tf-rmm-v0.3.0/about/change-log.html#v0-3-0
Hi,
I am pleased to announce that Yann Gautier has now become one of the
maintainers for TF-A. This decision is based on Yann's continued efforts
and involvement in the project over the years.
A patch is under review to reflect this in TF-A documentation:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/21060
Best regards,
Sandrine (on behalf of all TF-A maintainers)
This event has been updated
Changed: description
TF-A Tech Forum
Thursday Jun 1, 2023 ⋅ 4pm – 5pm
United Kingdom Time
Provisional topic: SVE enablement for Realms. More details on this nearer
the time....=====================We run an open technical forum call for
anyone to participate and it is not restricted to Trusted Firmware project
members. It will operate under the guidance of the TF TSC. Feel free to
forward this invite to colleagues. Invites are via the TF-A mailing list
and also published on the Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
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Apologies for late notice but the TF-A TechForum is cancelled today.
We were hoping a topic would be ready however that is not the case.
I try to send notifications a day before but over looked that last night.
I will be provisionally updating the session on 2nd June with a topic.
Thanks
Joanna
This event has been canceled.
TF-A Tech Forum
Thursday May 18, 2023 ⋅ 4pm – 5pm
United Kingdom Time
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
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TF-A Community,
This is to notify that we are planning to target the Trusted Firmware-A 2.9 release during the middle of May 2023 as part of the regular 6 month cadence.
The aim is to consolidate all TF-A work since the 2.8 release. As part of this, a release candidate tag is targeted to be created and release activities commence from 10th May 2023 across all TF-A repositories.
Essentially we will not merge any major enhancements from this date until the release is made.
Please ensure any patches desired to make the 2.9 release are submitted in good time to be complete by 9th May 2023.
Any major enhancement patches still open after that date will not be merged until after the release.
This will involve the various repositories making up the broader TF-A project including the TF-A mainline, TF-A Tests, Hafnium, TF-A CI Scripts and TF-A CI Job. In addition a TF-RMM repository release will be made that is compatible with v2.9.
We will endeavour minimise the disruption on patch merging and complete release activities ASAP after we start normally completing within 7-10 working days.
Regards
Joanna Farley
Hi,
I am currently doing research to implement the Transfer List to comply with
Arm's firmware handoff spec (
https://github.com/FirmwareHandoff/firmware_handoff) in order to have a
standardized handoff approach between different firmware stages during boot.
The idea is to create a Transfer List in BL2 and cache it into a
pre-allocated memory in SRAM that can be shared between BL2 and BL3x.
A prototype currently available is creating APIs under qemu platform code
to retrieve the pre-defined memory address (The shared memory region is
defined in platform_def.h).
But I think we need to define a common API for this purpose to support all
platforms.
Please share your views or any suggestions.
Thanks.
Regards,
Raymond
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 384887: Uninitialized variables (UNINIT)
/mbedtls/library/x509.c: 1396 in mbedtls_x509_parse_subject_alt_name()
________________________________________________________________________________________________________
*** CID 384887: Uninitialized variables (UNINIT)
/mbedtls/library/x509.c: 1396 in mbedtls_x509_parse_subject_alt_name()
1390 if (ret != 0) {
1391 return ret;
1392 }
1393
1394 memset(san, 0, sizeof(mbedtls_x509_subject_alternative_name));
1395 san->type = MBEDTLS_X509_SAN_OTHER_NAME;
>>> CID 384887: Uninitialized variables (UNINIT)
>>> Using uninitialized value "other_name". Field "other_name.type_id" is uninitialized when calling "memcpy". [Note: The source code implementation of the function has been overridden by a builtin model.]
1396 memcpy(&san->san.other_name,
1397 &other_name, sizeof(other_name));
1398
1399 }
1400 break;
1401 /*
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
Hi,
Arm worked to draft a firmware handoff [1] specification, evolving it based on community feedback.
This activity followed the request of some members of the Arm ecosystem [2].
The spec (still at ALP – feedback/comments welcome!) standardizes how information is propagated between different firmware components during boot.
The spec hopes to remove the reliance on bespoke/platform-specific information handoff mechanisms, thus reducing the code maintenance burden.
The concept of entry types is present in the spec – these are data structure layouts that carry a specific type of data.
New types are meant to be added, following the needs and use-cases of the different communities.
Thus, these communities should be empowered to request new types!
To enable community contributions, the specification must be hosted in a location that is friendly to change requests.
We propose to host the spec in trustedfirmware.org (tf.org).
Tf.org hosts several open-source projects and already has an open governance model.
TF-A, and the associated community, rely on tf.org, and thus are already well equipped to maintain this specification and keep it up to date.
Tf.org is agnostic of any downstream projects that would adopt this specification (e.g. U-boot, EDK2, etc.).
We welcome the views of the communities and want to understand if there are any strong objections to what’s being proposed!
If anyone has objections, we are happy to consider alternatives and associated trade-offs.
Regards
[1] https://developer.arm.com/documentation/den0135/latest
[2] Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages - TF-A - lists.trustedfirmware.org<https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…>
This event has been canceled.
TF-A Tech Forum
Thursday May 4, 2023 ⋅ 4pm – 5pm
United Kingdom Time
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
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Hello,
We have a use case where we want to deny the CPU power off from a certain PE. The current lib/psci does not provide a way for a platform to do this. We have support to return an error from svc_off, but this does not cover the scenario where svc_off is NULL.
There are multiple ways of handling this scenario.
1. Introduce a new platform function to check if CPU_OFF is allowed on the core
2. Return an error code from the pwr_domain_off() handler and unwind the CPU_OFF request
3. Something else.
Any suggestions?
-Varun
This event has been canceled with a note:
"The original topic for this TechForum will be held on a future date. No
alternative topic has been identified for this session so cancelling."
TF-A Tech Forum
Thursday Apr 20, 2023 ⋅ 4pm – 5pm
United Kingdom Time
This session will no longer take place on this date. It will be
rescheduled.This slot is now free for another session although nothing has
yet been identified.======================================Reserving for a
discussion on Signer-id Extraction Design for Manish Badarkhe. More details
of this session will be sent closer to the session date.-----------------We
run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are
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Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
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Hello,
This is a courtesy notification that we plan to deprecate Arm
CryptoCell-712 and CryptoCell-713 drivers in TF-A release v2.9, with the
goal to remove their source code from the tree in the following TF-A
release after that.
This won't affect any upstream platforms beyond Arm Ltd platforms (under
plat/arm/ folder).
If you have any concerns with this, please raise them by Monday, April 24th.
Best regards,
Sandrine
Hi, I'm using TF-A 2.8 on mt7986 board, enable TRUSTED_BOARD_BOOT using mbedtls-3.4.0,
TF-A BL2 hanged when loading BL31, it seems that BL2 failed to get correct oid in function get_ext(drivers/auth/mbedtls/mbedtls_x509_parser.c) after calling mbedtls_oid_get_numeric_string
mbedtls_oid_get_numeric_string in 3.4.0 uses %c to print part of oid,
(https://github.com/Mbed-TLS/mbedtls/blob/v3.4.0/library/oid.c#L864)
but seems that ATF libc's snprintf doesn't support %c format, which causes mbedtls_oid_get_numeric_string to return incorrect oid
oid_str dump in get_ext
oid_str=%c.49.6.1.4.1.4128.2100.1 (mbedtls_oid_get_numeric_string)
oid_str=1.3.6.1.4.1.4128.2100.1 (TRUSTED_FW_NVCOUNTER_OID)
I try to change snprintf format %c to %u in mbedtls_oid_get_numeric_string, TF-A boots successfully
Thanks
Hi,
Concerning the following Fast Model Component:
https://developer.arm.com/documentation/100964/1121/Fast-Models-components/…
This component is already publicly documented although it is not integrated yet into the AEM FVP.
The main usage is to identify software mis-programming, where the same Physical address is accessed through more than one Physical Address Space (PAS). As such, it is intended as a development / debugging tool only. If such a mis-programming scenario happened then the memory page corresponding to the accessed physical address would get corrupted.
Notice memory encryption is not yet supported in TF-A's SW stacks. You won't find a reference for this feature in TF-A / TF-a-tests just now.
Best regards,
Sandrine
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Hi, I'm working in TF-A 2.8 with mbedtls, I notice that mbedtls-3.4.0 starts to support AES crypto extension(MBEDTLS_AESCE_C) for some security reasons,
I upgrade mbedtls from 2.28.0 to 3.4.0, and try to enable MBEDTLS_AESCE_C in TF-A. I fail to compile mbedtls aesce.c in TF-A build environment.
I use CROSS_COMPILE=aarch64-gcc-7.5.0.
It seems that AESCE needs some std libraries(e.g. arm_neon.h) supported by aarch64 gcc, while TF-A disables std libraries,
and some compile flags(e.g. -mgeneral-regs-only) are conflict with current TF-A.
I wonder is TF-A going to support MBEDTLS_AESCE_C option?
Thanks
Hi all,
I want to test the memory encryption functions in Arm CCA. Currently,
I find that Arm FVP supports a PVMemoryProtectionEngine. Thus, can I
use this engine in current TF-A or TF-A-Tests? If yes, how to use this
engine?
Sincerely,
WANG Chenxu
This event has been updated
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Reserving for a discussion on Signer-id Extraction Design for
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session date.-----------------We run an open technical forum call for
anyone to participate and it is not restricted to Trusted Firmware project
members. It will operate under the guidance of the TF TSC. Feel free to
forward this invite to colleagues. Invites are via the TF-A mailing list
and also published on the Trusted Firmware website. Details are
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Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
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Hi,
I have talked to a couple of people to figure out what TF-A project is
using for code documentation. Because I see at least in our platform
that our documentation is somewhere between doxygen and kernel-doc but
actually with a lot of mismatches.
Sanbrine mentioned sending an email to the mailing list to start to
have discussion about it.
That's why I want to know the official code documentation format and
how we should be checking that everything matches to make sure that
documentation is not out of sync from code itself.
When this is clear I will ask my team to fix all these issues.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Hello all,
We are sending this note to notify you of one of the breaking changes related to the enablement of FEAT_SVE in TF-A. This mainly impacts platforms which are configurable (FVP, QEMU, Total Compute).
FEAT_SVE has now been moved under the Feature detection mechanism wherein a CPU feature macro can have 3 possible states
* 0: FEAT_STATE_DISABLED
* 1: FEAT_STATE_ALWAYS ( Always enabled, no runtime check)
* 2: FEAT_STATE_CHECK (Dynamically check based on ID registers, done each time when feature registers are being accessed)
For platforms which have a single configuration, it's better to choose either disabled or enabled (as it is a bit faster as there is no dynamic check).
For platforms which can have different HW configurations, it makes sense to put them under FEAT_STATE_CHECK(=2), so that they will boot with any configuration of HW.
Keeping this in mind, all configurable platforms (FVP, QEMU, TC) have been modified to adopt dynamic detection(FEAT_STATE_CHECK) for FEAT_SVE. [1]
SVE Patch Reference:
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20306
Best regards,
Jayanth