- TF-A - lists.trustedfirmware.org

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 445015: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_cipher.c: 250 in mbedtls_cipher_values_from_psa() ________________________________________________________________________________________________________ *** CID 445015: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_cipher.c: 250 in mbedtls_cipher_values_from_psa() 244 cipher_id_tmp = MBEDTLS_CIPHER_ID_CHACHA20; 245 break; 246 #endif 247 default: 248 return PSA_ERROR_NOT_SUPPORTED; 249 } >>> CID 445015: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "if (cipher_id != NULL) { ...". 250 if (cipher_id != NULL) { 251 *cipher_id = cipher_id_tmp; 252 } 253 254 return mbedtls_cipher_validate_values(alg, key_type); 255 } ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 5 months

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Re: Canceled event: TF-A Tech Forum @ Thu Sep 19, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

Hi, Cancelling today's Sep 19th instance as no topic proposed. Regards, Olivier. ________________________________ From: Trusted Firmware Public Meetings Sent: 24 July 2024 17:36 To: Trusted Firmware Public Meetings <linaro.org_havjv2figrh5egaiurb229pd8c(a)group.calendar.google.com>; tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org> Subject: [TF-A] Canceled event: TF-A Tech Forum @ Thu Sep 19, 2024 5pm - 6pm (GMT+2) (tf-a(a)lists.trustedfirmware.org) When: 19 September 2024 17:00-18:00. Where: This event has been canceled. We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/<https://www.google.com/url?q=https%3A%2F%2Fwww.trustedfirmware.org%2Fmeetin…> Trusted Firmware is inviting you to a scheduled Zoom meeting. Join Zoom Meeting https://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvd…<https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fmy%2Ftruste…> One tap mobile +16465588656,,9159704974# US (New York) +16699009128,,9159704974# US (San Jose) Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-free Meeting ID: 915 970 4974 Find your local number: https://zoom.us/u/ad27hc6t7h<https://www.google.com/url?q=https%3A%2F%2Fzoom.us%2Fu%2Fad27hc6t7h&sa=D&us…> When Thursday Sep 19, 2024 ⋅ 5pm – 6pm (Central European Time - Paris) Guests tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> Invitation from Google Calendar<https://calendar.google.com/calendar/> You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more<https://support.google.com/calendar/answer/37135#forwarding>

1 year, 5 months

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Canceled event: TF-A Tech Forum @ Thu Sep 19, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled. TF-A Tech Forum Thursday Sep 19, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 5 months

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How to map a physical address using `mmap_add_dynamic_region_alloc_va`?

by 钱非凡

Hi experts, I tried to allocate a physical memory address in Linux Kernel, and pass the memory address to tf-a using smc call. As I asked in previous mails (https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…), tf-a can not access the physical memory address directly, so I try to use the `mmap_add_dynamic_region_alloc_va` function in `xlat_table_v2` Library, and map the physical memory in tf-a. After calling the function, It does return a new virtual memory address, but I still failed to access the address, is there any details I have missed? Here is the code: ``` NOTICE("phys_addr: 0x%lx, virt_addr: 0x%lx\n", phys_addr, virt_addr); int rc = mmap_add_dynamic_region_alloc_va(phys_addr, ptr_virt_addr, size, MT_NS | MT_RW_DATA); if (rc) { WARN("Failed to map memory at 0x%lx: %d\n", phys_addr, rc); return; } NOTICE("virt_addr_el3: 0x%lx\n", virt_addr_el3); NOTICE("virt_addr_el3[0] = 0x%x\n", *((uint32_t *)virt_addr_el3)); ``` Here is the output: ``` NOTICE: phys_addr: 0x40f0000, virt_addr: 0xffff0000040f0000 NOTICE: mm.base_va: 0 NOTICE: mm.base_va: 100000000 NOTICE: virt_addr_el3: 0x100000000 [ 38.540464] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks: [ 38.546584] rcu: 4-...0: (1 ticks this GP) idle=4224/1/0x4000000000000000 softirq=125/125 fqs=2625 [ 38.555651] (detected by 0, t=5252 jiffies, g=-779, q=16 ncpus=8) [ 38.561843] Task dump for CPU 4: [ 38.565075] task:main state:R running task stack:0 pid:195 ppid:181 flags:0x00000002 [ 38.575015] Call trace: [ 38.577464] __switch_to+0xe4/0x160 [ 38.580975] 0x42 ``` I would be grateful for any advice or suggestions you may have. Sincerely, Feifan

1 year, 5 months

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Canceled event with note: TF-A Tech Forum @ Thu Sep 5, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling as no topic this week. Thanks & Regards, Olivier. " TF-A Tech Forum Thursday Sep 5, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 5 months

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Can't start new thread in website

by 林觀明

Hi I have a question. But, I can't launch a new thread. Can you help me? Thanks

1 year, 5 months

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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 6 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 6 of 6 defect(s) ** CID 443168: Error handling issues (CHECKED_RETURN) /plat/st/stm32mp2/bl2_plat_setup.c: 183 in bl2_el3_plat_arch_setup() ________________________________________________________________________________________________________ *** CID 443168: Error handling issues (CHECKED_RETURN) /plat/st/stm32mp2/bl2_plat_setup.c: 183 in bl2_el3_plat_arch_setup() 177 BL_CODE_END - BL_CODE_BASE, 178 MT_CODE | MT_SECURE); 179 180 configure_mmu(); 181 182 /* Prevent corruption of preloaded Device Tree */ >>> CID 443168: Error handling issues (CHECKED_RETURN) >>> Calling "mmap_add_dynamic_region" without checking return value (as is done elsewhere 25 out of 29 times). 183 mmap_add_dynamic_region(DTB_BASE, DTB_BASE, 184 DTB_LIMIT - DTB_BASE, 185 MT_RO_DATA | MT_SECURE); 186 187 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 188 panic(); ** CID 443167: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /plat/rockchip/rk3588/drivers/scmi/rk3588_clk.c: 578 in rk3588_b0pll_get_rate() ________________________________________________________________________________________________________ *** CID 443167: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /plat/rockchip/rk3588/drivers/scmi/rk3588_clk.c: 578 in rk3588_b0pll_get_rate() 572 573 rate64 *= m; 574 rate64 = rate64 / p; 575 576 if (k != 0) { 577 /* fractional mode */ >>> CID 443167: Integer handling issues (OVERFLOW_BEFORE_WIDEN) >>> Potentially overflowing expression "24000000U * k" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). 578 uint64_t frac_rate64 = 24000000 * k; 579 580 postdiv = p * 65535; 581 frac_rate64 = frac_rate64 / postdiv; 582 rate64 += frac_rate64; 583 } ** CID 443166: Memory - corruptions (OVERRUN) ________________________________________________________________________________________________________ *** CID 443166: Memory - corruptions (OVERRUN) /plat/intel/soc/common/socfpga_vab.c: 97 in socfpga_vab_authentication() 91 if (!IS_BYTE_ALIGNED(img_sz, sizeof(uint32_t))) { 92 ERROR("Image size (%d bytes) not aliged to 4 bytes!\n", img_sz); 93 return -EIMGERR; 94 } 95 96 /* Generate HASH384 from the image */ >>> CID 443166: Memory - corruptions (OVERRUN) >>> Overrunning array "hash384" of 12 bytes by passing it to a function which accesses it at byte offset 47. 97 sha384_start((uint8_t *)img_addr, img_sz, hash384, CHUNKSZ_PER_WD_RESET); 98 cert_hash_ptr = (uint8_t *)(img_addr + img_sz + VAB_CERT_MAGIC_OFFSET + 99 VAB_CERT_FIT_SHA384_OFFSET); 100 101 /* 102 * Compare the SHA384 found in certificate against the SHA384 ** CID 443165: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /plat/rockchip/rk3588/drivers/scmi/rk3588_clk.c: 747 in rk3588_b1pll_get_rate() ________________________________________________________________________________________________________ *** CID 443165: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /plat/rockchip/rk3588/drivers/scmi/rk3588_clk.c: 747 in rk3588_b1pll_get_rate() 741 742 rate64 *= m; 743 rate64 = rate64 / p; 744 745 if (k != 0) { 746 /* fractional mode */ >>> CID 443165: Integer handling issues (OVERFLOW_BEFORE_WIDEN) >>> Potentially overflowing expression "24000000U * k" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). 747 uint64_t frac_rate64 = 24000000 * k; 748 749 postdiv = p * 65535; 750 frac_rate64 = frac_rate64 / postdiv; 751 rate64 += frac_rate64; 752 } ** CID 443164: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /plat/rockchip/rk3588/drivers/scmi/rk3588_clk.c: 408 in rk3588_lpll_get_rate() ________________________________________________________________________________________________________ *** CID 443164: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /plat/rockchip/rk3588/drivers/scmi/rk3588_clk.c: 408 in rk3588_lpll_get_rate() 402 403 rate64 *= m; 404 rate64 = rate64 / p; 405 406 if (k != 0) { 407 /* fractional mode */ >>> CID 443164: Integer handling issues (OVERFLOW_BEFORE_WIDEN) >>> Potentially overflowing expression "24000000U * k" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). 408 uint64_t frac_rate64 = 24000000 * k; 409 410 postdiv = p * 65535; 411 frac_rate64 = frac_rate64 / postdiv; 412 rate64 += frac_rate64; 413 } ** CID 254051: Memory - illegal accesses (OVERRUN) /plat/intel/soc/common/lib/sha/sha.c: 206 in sha512_base_do_finalize() ________________________________________________________________________________________________________ *** CID 254051: Memory - illegal accesses (OVERRUN) /plat/intel/soc/common/lib/sha/sha.c: 206 in sha512_base_do_finalize() 200 const int bit_offset = SHA512_BLOCK_SIZE - sizeof(uint64_t[2]); 201 uint64_t *bits = (uint64_t *)(sctx->buf + bit_offset); 202 unsigned int partial = sctx->count[0] % SHA512_BLOCK_SIZE; 203 204 sctx->buf[partial++] = 0x80; 205 if (partial > bit_offset) { >>> CID 254051: Memory - illegal accesses (OVERRUN) >>> Overrunning array of 128 bytes at byte offset 128 by dereferencing pointer "sctx->buf + partial". [Note: The source code implementation of the function has been overridden by a builtin model.] 206 memset(sctx->buf + partial, 0x0, SHA512_BLOCK_SIZE - partial); 207 partial = 0; 208 209 sha512_block_fn(sctx, sctx->buf, 1); 210 } 211 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 6 months

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Canceled event with note: TF-A Tech Forum @ Thu Aug 22, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling today as no topic. Regards, Olivier." TF-A Tech Forum Thursday Aug 22, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 6 months

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Re: TF-A Tech Forum

by Olivier Deprez

Hi, cancelling today as no topic. Regards, Olivier. ________________________________ From: Trusted Firmware Public Meetings Sent: 24 July 2024 17:36 To: Trusted Firmware Public Meetings <linaro.org_havjv2figrh5egaiurb229pd8c(a)group.calendar.google.com>; marek.bykowski(a)gmail.com <marek.bykowski(a)gmail.com>; okash.khawaja(a)gmail.com <okash.khawaja(a)gmail.com>; tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org> Subject: TF-A Tech Forum When: 22 August 2024 17:00-18:00. Where: TF-A Tech Forum We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this This event has been updated We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/<https://www.google.com/url?q=https%3A%2F%2Fwww.trustedfirmware.org%2Fmeetin…> Trusted Firmware is inviting you to a scheduled Zoom meeting. Join Zoom Meeting https://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvd…<https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fmy%2Ftruste…> One tap mobile +16465588656,,9159704974# US (New York) +16699009128,,9159704974# US (San Jose) Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-free Meeting ID: 915 970 4974 Find your local number: https://zoom.us/u/ad27hc6t7h<https://www.google.com/url?q=https%3A%2F%2Fzoom.us%2Fu%2Fad27hc6t7h&sa=D&us…> When Every 2 weeks from 8am to 9am on Thursday (Mountain Standard Time - Phoenix) Guests marek.bykowski(a)gmail.com<mailto:marek.bykowski@gmail.com> okash.khawaja(a)gmail.com<mailto:okash.khawaja@gmail.com> tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> View all guest info<https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1…> RSVP for tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> for all events in this series <https://calendar.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tM…> Yes <https://calendar.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tM…> No <https://calendar.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tM…> Maybe <https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1…> More options Invitation from Google Calendar<https://calendar.google.com/calendar/> You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more<https://support.google.com/calendar/answer/37135#forwarding>

1 year, 6 months

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Query regarding the test coverage thru tf-a-tests

by Thangaraj, Senthil Nathan

Dear TF-A team, I have a query regarding the TF-A test. Specifically, I would like to know if there is a method to find out the code coverage for a specific test or for all the tests in current run? Your direction in this regard will be really appreciated. Thank you, Senthil

1 year, 6 months

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Arm TF-A can not access linux kernel's virtual/physical address?

by 钱非凡

In my opinion, Arm TF-A (EL3) has higher privileges than Linux Kernel (EL1), and Secure World should be able to access all memory address in Normal World. To verify this feature, I added a new SMC call in Arm TF-A and wrote a kernel module to test it (on a Hikey960 Development Board). But the program does not run as expected that Arm TF-A stucked while accessing the memory address passed by Linux Kernel. Here is my kernel module, which uses `alloc_pages` to acquire a physical address, and uses `page_address` converting it to a virtual address. And the module passes the physical address and the virtual address to Arm TF-A using `smc #0`: ```cpp static int __init smc_testing_init(void) { uintptr_t phys_addr, virt_addr; pr_info("Mmodule loaded\n"); phys_addr = (uintptr_t) alloc_pages(GFP_KERNEL, 2); virt_addr = (uintptr_t) page_address((struct page *) phys_addr); memset((void *) virt_addr, 'A', PAGE_SIZE << 2); printk("phys_addr: 0x%llx, virt_addr: 0x%llx\n", (uint64_t) phys_addr, (uint64_t) virt_addr); asm volatile( "ldr x0, =0xC8000003\n" "mov x1, %0\n" "mov x2, %1\n" "smc #0\n" : : "r" (phys_addr), "r" (virt_addr) : "x0", "x1", "x2" ); __free_pages((struct page *) phys_addr, 2); return 0; } static void __exit smc_testing_exit(void) { pr_info("Module unloaded\n"); } ``` And here is the handler's code in Arm TF-A, which prints the addresses of physical address and virtual address, and access the first element of the memory address: ```cpp if (0xC8000003 == smc_fid) { uintptr_t virt_addr = x3; NOTICE("phys_addr: 0x%lx, virt_addr: 0x%lx\n", phys_addr, virt_addr); NOTICE("virt_addr[0] = 0x%x\n", *((uint32_t *)virt_addr)); NOTICE("phys_addr[0] = 0x%x\n", *((uint32_t *)phys_addr)); SMC_RET0(handle); } ``` Here is the output, Arm TF-A handles the request successfully, but failed to access the memory address passed by Linux Kernel: ```bash # insmod ./smc_testing.ko [ 75.259590] smc_testing: loading out-of-tree module taints kernel. [ 75.266682] Mmodule loaded [ 75.269404] phys_addr: 0xfffffc0002dc5e00, virt_addr: 0xffff0000b7178000 NOTICE: phys_addr: 0xfffffc0002dc5e00, virt_addr: 0xffff0000b7178000 [ 96.276605] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks: [ 96.282741] rcu: 4-...0: (1 ticks this GP) idle=72ec/1/0x4000000000000000 softirq=204/204 fqs=2592 [ 96.291835] (detected by 0, t=5253 jiffies, g=-643, q=16 ncpus=8) [ 96.298044] Task dump for CPU 4: [ 96.301287] task:insmod state:R running task stack:0 pid:201 ppid:185 flags:0x00000006 [ 96.311254] Call trace: [ 96.313713] __switch_to+0xe4/0x160 [ 96.317241] printk_rb_static+0x30/0x58 ```

1 year, 6 months

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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 441243: Memory - corruptions (OVERRUN) ________________________________________________________________________________________________________ *** CID 441243: Memory - corruptions (OVERRUN) /plat/xilinx/common/pm_service/pm_svc_main.c: 516 in eemi_api_handler() 510 module_id = (api_id & MODULE_ID_MASK) >> 8U; 511 512 PM_PACK_PAYLOAD7(payload, module_id, security_flag, api_id, 513 pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], 514 pm_arg[4], pm_arg[5]); 515 >>> CID 441243: Memory - corruptions (OVERRUN) >>> Overrunning callee's array of size 7 by passing argument "7UL" in call to "pm_ipi_send_sync". 516 ret = pm_ipi_send_sync(primary_proc, payload, (uint32_t *)buf, 517 PAYLOAD_ARG_CNT); 518 519 SMC_RET4(handle, (uint64_t)ret | ((uint64_t)buf[0] << 32U), 520 (uint64_t)buf[1] | ((uint64_t)buf[2] << 32U), 521 (uint64_t)buf[3] | ((uint64_t)buf[4] << 32U), ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 6 months

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Canceled event with note: TF-A Tech Forum @ Thu Aug 8, 2024 4pm - 5pm (BST) (tf-a@lists.trustedfirmware.org)

by Joanna Farley

This event has been canceled with a note: "No topics scheduled this week so cancelling. Also a lot of people seem to be away on vacations." TF-A Tech Forum Thursday Aug 8, 2024 ⋅ 4pm – 5pm United Kingdom Time We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 6 months

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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 440627: Control flow issues (DEADCODE) /plat/allwinner/sun50i_h616/sunxi_h616_dtb.c: 56 in sunxi_soc_fdt_fixup() ________________________________________________________________________________________________________ *** CID 440627: Control flow issues (DEADCODE) /plat/allwinner/sun50i_h616/sunxi_h616_dtb.c: 56 in sunxi_soc_fdt_fixup() 50 if (ret != 0) { 51 return; 52 } 53 54 node = fdt_node_offset_by_phandle(dtb, phandle); 55 if (ret != 0) { >>> CID 440627: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "return;". 56 return; 57 } 58 59 ccsidr = armv8_get_ccsidr(CACHE_L2U); 60 sets = ((ccsidr >> CCSIDR_SETS_SHIFT) & CCSIDR_SETS_MASK) + 1; 61 line_size = 16U << ((ccsidr >> CCSIDR_LSIZE_SHIFT) & CCSIDR_LSIZE_MASK); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 7 months

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Re: Integrate TF-A and PSA Crypto API with PUFcc

by Jothikumar Mani

HI Andy, Thank you for explaining, psa-arch-test(psa certified api compliance) testsuite currently used with TFM +MbedTLS environment as a release gate, and there is trusted service team whom were running the psa-arch-test package on arm-A class devices. Coming back to the question related to psa-arch-test, the current available package should suffice to check the compliance of crypto necessary tasks/functinoality, fyi we have already validated the latest psa-arch-test repo with the mbedtls 3.6. So I would not be more concern about the psa-arch-test being compliant to latest 1.2.1 spec. because between 1.1.0 and 1.2.1 there were minimal changes which is not showstopper for the psa certified api certification. Regards, JK From: Andy Chen <andychen(a)pufsecurity.com> Date: Thursday, 25 July 2024 at 5:30 AM To: Jothikumar Mani <Jothikumar.Mani(a)arm.com>, Manish Badarkhe <Manish.Badarkhe(a)arm.com>, tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org> Cc: Diya Soubra <Diya.Soubra(a)arm.com>, Victoria Lee <victorialee(a)pufsecurity.com>, Andrew <andrewirvin(a)pufsecurity.com> Subject: 回覆: Integrate TF-A and PSA Crypto API with PUFcc Hi Jothikumar and Manish, It's great to discuss with you and thanks. Sure, it's more clarity with usage scenarios: 1. As a Security IP provider, our PUFcc functions as a Hardware Root of Trust. However, mbedTLS currently doesn't fully support HRoT. Therefore, we are integrating directly into the PSA Crypto API, which permits customization. 1. While working on PSA L3 or L2R, we frequently face version conflicts. That why, in this project, we aim to confirm these version issues (including the dev. and test bench). 1. This also means that both TF-A and TF-M support PSA Crypto API, so we can also support both through this package. There is our PSA Software Package with PUFcc. We try to find the best way to support cryptographic tasks. Additionally, we plan to use the same development platform as ARM to ensure optimal compatibility for our customers. It means we would try to know the FPV, although I'm not sure if we can add external IPs. If I misunderstood or you have any ideas, please feel free to tell me. [cid:ed0bb76e-fb77-4502-ae5d-f8443d6b4fc4] Have a Nice Day, Andy ________________________________ 寄件者: Jothikumar Mani <Jothikumar.Mani(a)arm.com> 寄件日期: 2024年7月24日下午 11:48 收件者: Andy Chen <andychen(a)pufsecurity.com>; Manish Badarkhe <Manish.Badarkhe(a)arm.com>; tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org> 副本: Diya Soubra <Diya.Soubra(a)arm.com>; Victoria Lee <victorialee(a)pufsecurity.com>; Andrew <andrewirvin(a)pufsecurity.com> 主旨: RE: Integrate TF-A and PSA Crypto API with PUFcc Hi Andy, Please find my reply in the previous mail. Regards, JK From: Andy Chen <andychen(a)pufsecurity.com> Sent: Wednesday, July 24, 2024 8:11 PM To: Manish Badarkhe <Manish.Badarkhe(a)arm.com>; Jothikumar Mani <Jothikumar.Mani(a)arm.com>; tf-a(a)lists.trustedfirmware.org Cc: Diya Soubra <Diya.Soubra(a)arm.com>; Victoria Lee <victorialee(a)pufsecurity.com>; Andrew <andrewirvin(a)pufsecurity.com> Subject: 回覆: Integrate TF-A and PSA Crypto API with PUFcc Hi Manish, Thanks for your information. We need to integrate our hardware Crypto IP (PUFcc). And it seems that FVP cannot add custom IP, so we are planning to purchase an FPGA with the A53 - AXU9EGB<https://www.xilinx.com/products/boards-and-kits/1-1ervp7b.html> for our needs. And we need to make sure it is compatible with TF-A lts-v2.10.5. Thanks. Hi Jothikumar, We would try to integrate with PSA Crypto API, and we need a test bench for v1.2.1. Please feel free to let me know if you have any suggestions. [JK] : may I know what the intent is to requesting the crypto v1.2.1 spec compliance suites?, if you are looking for the PSA Certified APIs compliance for your product then the currently available testsuite is more than sufficient. Also, the mbedTLS version mentioned also only supports psa-crypto spec v1.1.0. I am trying to under the end goal of the psa certified api compliance suite usage with your product. Answer to this question will help me to give better suggestion. For TF-A, we plan to integrate with: TF-A lts-v2.10.5 PSA Crypto API - v1.1.0 >>> v1.2.1 PSA Certified APIs Architecture Test Suite - v1.6 Thank you very much. Have a Nice Day, Andy ________________________________ 寄件者: Manish Badarkhe <Manish.Badarkhe(a)arm.com<mailto:Manish.Badarkhe@arm.com>> 寄件日期: 2024年7月24日下午 06:12 收件者: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>>; Andy Chen <andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com>>; Jothikumar Mani <Jothikumar.Mani(a)arm.com<mailto:Jothikumar.Mani@arm.com>> 副本: Diya Soubra <Diya.Soubra(a)arm.com<mailto:Diya.Soubra@arm.com>>; Victoria Lee <victorialee(a)pufsecurity.com<mailto:victorialee@pufsecurity.com>>; Andrew <andrewirvin(a)pufsecurity.com<mailto:andrewirvin@pufsecurity.com>> 主旨: Re: Integrate TF-A and PSA Crypto API with PUFcc Hi Andy Please see my replies inline. Adding Jothikumar Mani for PSA Certified APIs Architecture Test Suite. Thanks, Manish Badarkhe ________________________________ From: Andy Chen via TF-A <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>> Sent: 23 July 2024 09:55 To: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>> Cc: Diya Soubra <Diya.Soubra(a)arm.com<mailto:Diya.Soubra@arm.com>>; Victoria Lee <victorialee(a)pufsecurity.com<mailto:victorialee@pufsecurity.com>>; Andrew <andrewirvin(a)pufsecurity.com<mailto:andrewirvin@pufsecurity.com>> Subject: [TF-A] Integrate TF-A and PSA Crypto API with PUFcc Hi TF-A teams, This is Andy from PUFsecurity, and we have a project with ARM. We try to integrate the PSA Crypto API with PUFcc (Our Crypto Engine) on TF-A. However, there are multiple versions included, and we need your assistance for specification clarification. Please ensure the versions match your recommendations. For TF-A, we plan to integrate with: TF-A lts-v2.10.5 PSA Crypto API - v1.1.0 PSA Certified APIs Architecture Test Suite - v1.6 [MB]: This looks fine. As TF-A lts-v2.10.5 using mbedTLS v3.6.0 which is compliance with PSA Crypto API - v1.1.0 but mbedTLS team can provide more detailed answer on this and also on test suite PSA Certified APIs Architecture Test Suite - v1.6. TF-A It would be beneficial to use the same hardware (FPGA) and tools as the ARM development team. If we can confirm which models are used for TF-A , scripts or details with the ARM hardware That would be grateful. [MB]: We are using FVP AEM model i.e. FVP_Base_RevC-2xAEMvA (Model version: 11.26, Build: 11). Test Run with PSA Crypto you can find here: https://ci.trustedfirmware.org/job/tf-a-builder/4029201/ (today's daily run) PSA Crypto API - The test bench is using the PSA Crypto API v1.1.0, and it is published in 2022. And Now is v1.2.1 in March 2024. I not sure it is a good choose or not. [cid:image001.png@01DADE0E.1BA75330] [MB]: It looks like arch-test is not upgraded to use v1.2.1 PSA Crypto API. Added Jothikumar Mani, he may have idea about this. Test Bench - For the "PSA Certified APIs Architecture Test Suite - v1.6," we would like to identify which test codes (test_c001 to test_c067) are relevant for TF-A. [MB]: Again, TF-A is not using this test suite, so we don't have any insights unless we review all these tests. TF-A mainly uses the following PSA_* APIs for signature verification, hash calculation, and hash comparison. psa_crypto_init mbedtls_md_psa_alg_from_type psa_set_key_algorithm psa_set_key_type psa_set_key_usage_flags psa_import_key psa_destroy_key psa_verify_message psa_hash_compute psa_hash_compare Thank you very much!!! Have a Nice Day, Andy [cid:image002.png@01DADE0E.1BA75330] 熵碼科技股份有限公司 Tel: 886-3-5601010 #2119 Email: andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com> Website: https://www.pufsecurity.com/ -------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.-------- -------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.-------- -------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.-------- -------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------

1 year, 7 months

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Re: Integrate TF-A and PSA Crypto API with PUFcc

by Jothikumar Mani

Hi Andy, Please find my reply in the previous mail. Regards, JK From: Andy Chen <andychen(a)pufsecurity.com> Sent: Wednesday, July 24, 2024 8:11 PM To: Manish Badarkhe <Manish.Badarkhe(a)arm.com>; Jothikumar Mani <Jothikumar.Mani(a)arm.com>; tf-a(a)lists.trustedfirmware.org Cc: Diya Soubra <Diya.Soubra(a)arm.com>; Victoria Lee <victorialee(a)pufsecurity.com>; Andrew <andrewirvin(a)pufsecurity.com> Subject: 回覆: Integrate TF-A and PSA Crypto API with PUFcc Hi Manish, Thanks for your information. We need to integrate our hardware Crypto IP (PUFcc). And it seems that FVP cannot add custom IP, so we are planning to purchase an FPGA with the A53 - AXU9EGB<https://www.xilinx.com/products/boards-and-kits/1-1ervp7b.html> for our needs. And we need to make sure it is compatible with TF-A lts-v2.10.5. Thanks. Hi Jothikumar, We would try to integrate with PSA Crypto API, and we need a test bench for v1.2.1. Please feel free to let me know if you have any suggestions. [JK] : may I know what the intent is to requesting the crypto v1.2.1 spec compliance suites?, if you are looking for the PSA Certified APIs compliance for your product then the currently available testsuite is more than sufficient. Also, the mbedTLS version mentioned also only supports psa-crypto spec v1.1.0. I am trying to under the end goal of the psa certified api compliance suite usage with your product. Answer to this question will help me to give better suggestion. For TF-A, we plan to integrate with: TF-A lts-v2.10.5 PSA Crypto API - v1.1.0 >>> v1.2.1 PSA Certified APIs Architecture Test Suite - v1.6 Thank you very much. Have a Nice Day, Andy ________________________________ 寄件者: Manish Badarkhe <Manish.Badarkhe(a)arm.com<mailto:Manish.Badarkhe@arm.com>> 寄件日期: 2024年7月24日下午 06:12 收件者: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>>; Andy Chen <andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com>>; Jothikumar Mani <Jothikumar.Mani(a)arm.com<mailto:Jothikumar.Mani@arm.com>> 副本: Diya Soubra <Diya.Soubra(a)arm.com<mailto:Diya.Soubra@arm.com>>; Victoria Lee <victorialee(a)pufsecurity.com<mailto:victorialee@pufsecurity.com>>; Andrew <andrewirvin(a)pufsecurity.com<mailto:andrewirvin@pufsecurity.com>> 主旨: Re: Integrate TF-A and PSA Crypto API with PUFcc Hi Andy Please see my replies inline. Adding Jothikumar Mani for PSA Certified APIs Architecture Test Suite. Thanks, Manish Badarkhe ________________________________ From: Andy Chen via TF-A <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>> Sent: 23 July 2024 09:55 To: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>> Cc: Diya Soubra <Diya.Soubra(a)arm.com<mailto:Diya.Soubra@arm.com>>; Victoria Lee <victorialee(a)pufsecurity.com<mailto:victorialee@pufsecurity.com>>; Andrew <andrewirvin(a)pufsecurity.com<mailto:andrewirvin@pufsecurity.com>> Subject: [TF-A] Integrate TF-A and PSA Crypto API with PUFcc Hi TF-A teams, This is Andy from PUFsecurity, and we have a project with ARM. We try to integrate the PSA Crypto API with PUFcc (Our Crypto Engine) on TF-A. However, there are multiple versions included, and we need your assistance for specification clarification. Please ensure the versions match your recommendations. For TF-A, we plan to integrate with: TF-A lts-v2.10.5 PSA Crypto API - v1.1.0 PSA Certified APIs Architecture Test Suite - v1.6 [MB]: This looks fine. As TF-A lts-v2.10.5 using mbedTLS v3.6.0 which is compliance with PSA Crypto API - v1.1.0 but mbedTLS team can provide more detailed answer on this and also on test suite PSA Certified APIs Architecture Test Suite - v1.6. TF-A It would be beneficial to use the same hardware (FPGA) and tools as the ARM development team. If we can confirm which models are used for TF-A , scripts or details with the ARM hardware That would be grateful. [MB]: We are using FVP AEM model i.e. FVP_Base_RevC-2xAEMvA (Model version: 11.26, Build: 11). Test Run with PSA Crypto you can find here: https://ci.trustedfirmware.org/job/tf-a-builder/4029201/ (today's daily run) PSA Crypto API - The test bench is using the PSA Crypto API v1.1.0, and it is published in 2022. And Now is v1.2.1 in March 2024. I not sure it is a good choose or not. [cid:image001.png@01DADE0E.1BA75330] [MB]: It looks like arch-test is not upgraded to use v1.2.1 PSA Crypto API. Added Jothikumar Mani, he may have idea about this. Test Bench - For the "PSA Certified APIs Architecture Test Suite - v1.6," we would like to identify which test codes (test_c001 to test_c067) are relevant for TF-A. [MB]: Again, TF-A is not using this test suite, so we don't have any insights unless we review all these tests. TF-A mainly uses the following PSA_* APIs for signature verification, hash calculation, and hash comparison. psa_crypto_init mbedtls_md_psa_alg_from_type psa_set_key_algorithm psa_set_key_type psa_set_key_usage_flags psa_import_key psa_destroy_key psa_verify_message psa_hash_compute psa_hash_compare Thank you very much!!! Have a Nice Day, Andy [cid:image002.png@01DADE0E.1BA75330] 熵碼科技股份有限公司 Tel: 886-3-5601010 #2119 Email: andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com> Website: https://www.pufsecurity.com/ -------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.-------- -------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.-------- -------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------

1 year, 7 months

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Updated invitation: TF-A Tech Forum @ Every 2 weeks from 9am to 10am on Thursday from Thu Mar 7 to Wed Jul 24 (MST) (tf-a@lists.trustedfirmware.org)

by Don Harbin

This event has been updated Changed: time TF-A Tech Forum Every 2 weeks from 9am to 10am on Thursday from Thursday Mar 7 to Wednesday Jul 24 Mountain Standard Time - Phoenix We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org View all guest info https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1… Reply for tf-a(a)lists.trustedfirmware.org and view more details https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1… Your attendance is optional. ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 7 months

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Updated invitation: TF-A Tech Forum @ Every 2 weeks from 8am to 9am on Thursday (MST) (tf-a@lists.trustedfirmware.org)

by Don Harbin

This event has been updated TF-A Tech Forum Every 2 weeks from 8am to 9am on Thursday Mountain Standard Time - Phoenix We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org View all guest info https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1… Reply for tf-a(a)lists.trustedfirmware.org and view more details https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1… Your attendance is optional. ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 7 months

1
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Integrate TF-A and PSA Crypto API with PUFcc

by Andy Chen

Hi TF-A teams, This is Andy from PUFsecurity, and we have a project with ARM. We try to integrate the PSA Crypto API with PUFcc (Our Crypto Engine) on TF-A. However, there are multiple versions included, and we need your assistance for specification clarification. Please ensure the versions match your recommendations. For TF-A, we plan to integrate with: TF-A lts-v2.10.5 PSA Crypto API - v1.1.0 PSA Certified APIs Architecture Test Suite - v1.6 TF-A It would be beneficial to use the same hardware (FPGA) and tools as the ARM development team. If we can confirm which models are used for TF-A , scripts or details with the ARM hardware That would be grateful. PSA Crypto API - The test bench is using the PSA Crypto API v1.1.0, and it is published in 2022. And Now is v1.2.1 in March 2024. I not sure it is a good choose or not. [cid:0e747007-8c2a-49a7-9447-8d5e7f9a3e9c] Test Bench - For the "PSA Certified APIs Architecture Test Suite - v1.6," we would like to identify which test codes (test_c001 to test_c067) are relevant for TF-A. Thank you very much!!! Have a Nice Day, Andy [cid:74269c28-12d4-48a9-b215-3d3eaf95f2c3] 熵碼科技股份有限公司 Tel: 886-3-5601010 #2119 Email: andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com> Website: https://www.pufsecurity.com/ -------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.-------- -------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------

1 year, 7 months

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TF-A Tech Forum - Jul 25th 2024 - Unification of Chain of Trust Descriptors

by Olivier Deprez

Hi, On Jul 25th in the TF-A Tech Forum: Unification of Chain of Trust Descriptors - presented by Xialin Liu Currently, the Chain of Trust is implemented using C data structures built into the firmware or through device tree nodes. Maintaining both formats can lead to maintenance challenges. Therefore, we are standardizing the provision of Chain of Trust descriptors exclusively via the device tree and providing a tool to convert device tree descriptors into C source files. This approach simplifies the process, ensuring consistency and reducing the potential for errors associated with managing multiple formats. Regards, Olivier. TF-A Tech Forum Thursday Jul 25, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org

1 year, 7 months

1
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Firmware Partition Filesystem query

by Ghennadi Procopciuc

Greetings everyone, I came across the following paragraph while reading the 'Firmware Partition Filesystem' chapter from EBBR v2.2.0 and I would like to clarify my understanding: Where possible, firmware images and data should be stored in a filesystem. Firmware can be stored either in a dedicated firmware partition, or in certain circumstances in the UEFI System Partition (ESP). Using a filesystem makes it simpler to manage multiple firmware files and makes it possible for a single disk image to contain firmware for multiple platforms. Dedicated firmware partitions should be formatted with a FAT filesystem as defined in UEFI § 13.3 File System Format. Dedicated firmware partitions should use the same /FIRMWARE directory hierarchy. OS tools shall ignore dedicated firmware partitions, and shall not attempt to use a dedicated firmware partition as an ESP Questions: 1. Does the above paragraph mean that, if the device allows, all firmware binaries (TF-A, U-Boot, and some others) must be stored in a dedicated firmware partition formatted with a FAT filesystem and GUID Partition Table (GPT) disk layout? 2. If so, would this also mean that, where possible, the BootROM or a (first stage) bootloader running before TF-A should have GPT and FAT support embedded support to load one of the TF-A stages (BL1/BL2)? Regards, Ghennadi

1 year, 7 months

5
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Proper message for ERRATA_NOT_APPLIES case

by Bollapalli, Maheedhar Sai

Hi, On AMD-Xilinx ZynqMP platform for ERRATA_NOT_APPLIES case; the log appearing on the console is as below: "VERBOSE: BL31: cortex_a53: CPU workaround for erratum 819472was not applied". We checked ZynqMP code and found that the ZynqMP cpu revision was higher than the cpu revision intended in the erratum and hence it was not applicable and not applied. The message seems inappropriate to us as from log message it is not clear why it wasn't applied. Our suggestion is that in the log message instead of "not applied" it should be mentioned as "not applicable" as indicated below to reflect the reason properly. "VERBOSE: BL31: cortex_a53: CPU workaround for erratum 819472 was not applicable". Regards, Maheedhar.

1 year, 7 months

2
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BL2 does find only 2 images

by Labs, Torsten

Hey all, i tried to setup a fip.bin and add 3 images (bl31, bl32 and bl33). ./fiptool --verbose create --soc-fw bl31.bin --nt-fw bl33.bin --tos-fw bl32.bin fip.bin When i check the generated fip.bin with fiptool info it shows me all my three images in the fip.bin EL3 Runtime Firmware BL31: offset=0xB0, size=0x13644, cmdline="--soc-fw" Secure Payload BL32 (Trusted OS): offset=0x136F4, size=0x18D864, cmdline="--tos-fw" Non-Trusted Firmware BL33: offset=0x1A0F58, size=0x9692E, cmdline="--nt-fw" But during bootup the BL2 finds only the image id =3 and image id=5 which is BL32 and BL33. Why he is not finding the bl32? Thanks for youre short help. Regards Torsten

1 year, 7 months

2
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TF-A Tech Forum - Jul 11th 2024 - Using the SMC Fuzzing Module in TF-A

by Olivier Deprez

Hi, This Thursday Jul 11th Kathleen Capella from Arm's TF-A team will present: **Using the SMC Fuzzing Module in TF-A** This presentation will show how you might get started with fuzz testing using the SMC fuzzing module in TF-A. I will demonstrate the basic fuzzer features, how to add SMC calls/test cases and how to make use of the module's integration with tf-a-tests and the TF-A CI. Regards, Olivier. TF-A Tech Forum Thursday Jul 11, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org

1 year, 7 months

2
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TF-A Tech Forum - Jul 18th 2024 - NUMA-Aware PER-CPU Framework

by Olivier Deprez

Hi, On Thursday Jul 18th 2024 Rohit Mathew from Arm's Infra solutions team will present: ** NUMA-Aware PER-CPU Framework: Enhancing Latency and Storage Efficiency** With the increasing prevalence of multi-chip platforms, it is crucial for software written for Trusted Firmware-A to be NUMA-aware. The PER-CPU framework addresses this need by distributing the allocation of per-CPU objects across different NUMA nodes. This approach reduces NUMA latency and balances the allocation load, leading to improved performance and efficiency. Regards, Olivier. NUMA-Aware PER-CPU Framework: Enhancing Latency and Storage Efficiency Thursday Jul 18, 2024 ⋅ 5pm – 5:50pm Central European Time - Paris Location zoom, see dial-in information below https://www.google.com/maps/search/zoom,+see+dial-in+information+below?hl=en NUMA-Aware PER-CPU Framework: Enhancing Latency and Storage EfficiencyWith the increasing prevalence of multi-chip platforms, it is crucial for software written for Trusted Firmware-A to be NUMA-aware. The PER-CPU framework addresses this need by distributing the allocation of per-CPU objects across different NUMA nodes. This approach reduces NUMA latency and balances the allocation load, leading to improved performance and efficiency.Dial In Information:Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/j/9159704974?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09Meeting ID: 915 970 4974Passcode: Mj6NdM---One tap mobile+13462487799,,9159704974# US (Houston)+16694449171,,9159704974# US---Dial by your location• +1 346 248 7799 US (Houston)• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 719 359 4580 US• +1 253 205 0468 US• +1 253 215 8782 US (Tacoma)• +1 646 931 3860 US• +1 689 278 1000 US• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://linaro-org.zoom.us/u/aZXJZYXK

1 year, 7 months

1
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Native compilation failed on dev board not able to find the gcc

by Anand Moon

Hi All, I am trying to compile the latest ATF on Raspberry Pi 5 but it fails. This is the same for all the other Arm64 architecture I have. Earlier versions of ATF were able to compile on-board with native gcc. Well with CROSS_COMPILE it works fine on x86_64 machine. alarm@raspberrypi:~/Downloads/trusted-firmware-a$ make PLAT=rpi5 DEBUG=1 make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The configured AArch64 C compiler could not be identified and may not be supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The default AArch64 C compiler is: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The following tools are supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang` make_helpers/toolchain.mk:344: - LLVM Clang (`clang`) make_helpers/toolchain.mk:344: - GNU GCC (`gcc`) make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The build system will treat this C compiler as GNU GCC (`gcc`). make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The configured AArch64 C preprocessor could not be identified and may not be supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The default AArch64 C preprocessor is: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The following tools are supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang` make_helpers/toolchain.mk:344: - LLVM Clang (`clang`) make_helpers/toolchain.mk:344: - GNU GCC (`gcc`) make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The build system will treat this C preprocessor as GNU GCC (`gcc`). make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The configured AArch64 assembler could not be identified and may not be supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The default AArch64 assembler is: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The following tools are supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang` make_helpers/toolchain.mk:344: - LLVM Clang (`clang`) make_helpers/toolchain.mk:344: - GNU GCC (`gcc`) make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The build system will treat this assembler as GNU GCC (`gcc`). make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The configured AArch64 linker could not be identified and may not be supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The default AArch64 linker is: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The following tools are supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang` make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armlink` make_helpers/toolchain.mk:344: - LLVM Clang (`clang`) make_helpers/toolchain.mk:344: - LLVM LLD (`lld`) make_helpers/toolchain.mk:344: - GNU GCC (`gcc`) make_helpers/toolchain.mk:344: - GNU LD (`ld.bfd`) make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The build system will treat this linker as GNU GCC (`gcc`). make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The configured AArch64 object copier could not be identified and may not be supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-objcopy make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The default AArch64 object copier is: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-objcopy make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The following tools are supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `fromelf` make_helpers/toolchain.mk:344: - LLVM `llvm-objcopy` make_helpers/toolchain.mk:344: - GNU `objcopy` make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The build system will treat this object copier as GNU `objcopy`. make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The configured AArch64 object dumper could not be identified and may not be supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-objdump make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The default AArch64 object dumper is: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-objdump make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The following tools are supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `fromelf` make_helpers/toolchain.mk:344: - LLVM `llvm-objdump` make_helpers/toolchain.mk:344: - GNU `objdump` make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The build system will treat this object dumper as GNU `objdump`. make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The configured AArch64 archiver could not be identified and may not be supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc-ar make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The default AArch64 archiver is: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: aarch64-none-elf-gcc-ar make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The following tools are supported: make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armar` make_helpers/toolchain.mk:344: - LLVM `llvm-ar` make_helpers/toolchain.mk:344: - GNU `ar` make_helpers/toolchain.mk:344: make_helpers/toolchain.mk:344: The build system will treat this archiver as GNU `ar`. make_helpers/toolchain.mk:344: /bin/sh: 1: aarch64-none-elf-gcc: not found /bin/sh: 1: aarch64-none-elf-gcc: not found CC bl31/bl31_context_mgmt.c make: aarch64-none-elf-gcc: No such file or directory make: *** [Makefile:1514: /home/alarm/Downloads/trusted-firmware-a/build/rpi5/debug/bl31/bl31_context_mgmt.o] Error 127 alarm@raspberrypi:~/Downloads/trusted-firmware-a$ alarm@raspberrypi:~/Downloads/trusted-firmware-a$ gcc -v Using built-in specs. COLLECT_GCC=gcc COLLECT_LTO_WRAPPER=/usr/lib/gcc/aarch64-linux-gnu/12/lto-wrapper Target: aarch64-linux-gnu Configured with: ../src/configure -v --with-pkgversion='Debian 12.2.0-14' --with-bugurl=file:///usr/share/doc/gcc-12/README.Bugs --enable-languages=c,ada,c++,go,d,fortran,objc,obj-c++,m2 --prefix=/usr --with-gcc-major-version-only --program-suffix=-12 --program-prefix=aarch64-linux-gnu- --enable-shared --enable-linker-build-id --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --libdir=/usr/lib --enable-nls --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --with-default-libstdcxx-abi=new --enable-gnu-unique-object --disable-libquadmath --disable-libquadmath-support --enable-plugin --enable-default-pie --with-system-zlib --enable-libphobos-checking=release --with-target-system-zlib=auto --enable-objc-gc=auto --enable-multiarch --enable-fix-cortex-a53-843419 --disable-werror --enable-checking=release --build=aarch64-linux-gnu --host=aarch64-linux-gnu --target=aarch64-linux-gnu Thread model: posix Supported LTO compression algorithms: zlib zstd gcc version 12.2.0 (Debian 12.2.0-14) Thanks -Anand

1 year, 8 months

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Re: Questions about the Fault Handling of GPFs

by Olivier Deprez

Hi Feifan Qian, Trapping GPF to EL3 is permitted by the architecture, however I don't believe TF-A provides such option. In general for TF-A's reference software stacks, a GPF is trapped first at EL2 (hence SCR_EL3.GPF=0). E.g. In a system implementing RME, the RMM (@ R-EL2) traps a GPF occurring in an R-EL1/0 Realm (or R-EL2 itself). Similarly, in the secure world, the SPM (@ S-EL2) traps a GPF occurring in a S-EL1/0 secure partition (or S-EL2 itself). Regards, Olivier. ________________________________ From: 钱非凡 <qianfeifan(a)iie.ac.cn> Sent: 01 July 2024 08:52 To: tf-a-owner(a)lists.trustedfirmware.org <tf-a-owner(a)lists.trustedfirmware.org> Subject: Questions about the Fault Handling of GPFs Dear experts, I have been learning the Fault Handling of the Granule Protection Fault in Arm CCA. Upon studying the Arm Document, I discovered that the GPF bit in the SCR_EL3 register controls whether the fault handling of GPFs occurs in EL3 or not. In addition, I noted that `include/arch/aarch64/arch.h` defines a macro `#define SCR_GPF_BIT (UL(1) << 48)`, yet I could not find any reference to this macro in the source code. I want to know that whether ATF has implemented the fault handling of GPFs or if this is a feature to be expected in the future. If its not, how can I implement this. Any guidance or advice you could provide would be greatly appreciated. Sincerely, Feifan Qian

1 year, 8 months

1
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Trusted Firmware-A LTS v2.8.20 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.20 is now available. This release contains the following patches: 4da2210db chore: add encrypt_fw to gitignore [1] e0124e1ba feat(build): allow additional CFLAGS for library build [2] d7f618143 refactor(mbedtls): avoid including MBEDTLS_CONFIG_FILE [3] fd566c3cd feat(mbedtls): add support for mbedtls-3.3 [4] bf740eba7 feat(fvp): increase BL1_RW and BL2 size [5] ef7aac710 refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT [6] c82afd25b feat(stm32mp1): add mbedtls-3.3 support config [7] 488514a66 docs(prerequisites): update software and libraries prerequisites [8] a353e39e8 feat(mbedtls): update to 3.4.1 [9] 07126ffb4 build(mbedtls): add deprecation notice [10] 87f4a6305 refactor(mbedtls): remove mbedtls 2.x support [11] e8ae4fa2b feat(mbedtls): update config for 3.6.0 [12] b437905e2 docs(prerequisites): update mbedtls version used [13] [1] https://review.trustedfirmware.org/q/I2f4ddbe1c11848513fe20f7c8b448a041988c… [2] https://review.trustedfirmware.org/q/Ic99af22b229f8089c82110d6545f762c14a62… [3] https://review.trustedfirmware.org/q/I029992311be2a38b588ebbb350875b03ea29a… [4] https://review.trustedfirmware.org/q/Ib034036c09fbdc573d9427b1eda6f2387bda2… [5] https://review.trustedfirmware.org/q/I8a423711ac50b3d615c1d9650086cdbca5051… [6] https://review.trustedfirmware.org/q/I800524d54ea56dc27b6c6da26c75a07f5f6de… [7] https://review.trustedfirmware.org/q/I4581cb0ea7b2c7022e71aefd7ff05ee3a72f5… [8] https://review.trustedfirmware.org/q/I384aab4dfee9cae9453eebf4091abe82ef9cc… [9] https://review.trustedfirmware.org/q/Ifc31c2fc825a2fc9ca318ea8baadd51b670e7… [10] https://review.trustedfirmware.org/q/I669b423ee9af9f5c5255fce370413fffaf38e… [11] https://review.trustedfirmware.org/q/Id3eb98b55692df98aabe6a7c5a5ec910222c8… [12] https://review.trustedfirmware.org/q/Ib345b0bd4f2994f366629ed162d18814fd05a… [13] https://review.trustedfirmware.org/q/I6bd8fcca795373a05bc6beb2e085d24fdd149… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.20/change-log.html Thanks, TF-A LTS team

1 year, 8 months

1
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Trusted Firmware-A LTS v2.10.5 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.5 is now available. This release contains the following patches: 1d3bb2fe6 refactor(mbedtls): remove mbedtls 2.x support [1] 05ec367ba feat(mbedtls): update config for 3.6.0 [2] aa84a9dad docs(prerequisites): update mbedtls version used [3] ee945f1d2 fix(mbedtls): sign verification issue with invalid Key/Signature [4] [1] https://review.trustedfirmware.org/q/Id3eb98b55692df98aabe6a7c5a5ec910222c8… [2] https://review.trustedfirmware.org/q/Ib345b0bd4f2994f366629ed162d18814fd05a… [3] https://review.trustedfirmware.org/q/I6bd8fcca795373a05bc6beb2e085d24fdd149… [4] https://review.trustedfirmware.org/q/Ib484d97a04b7a82dd72592c8b5b153d577d01… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.5/change-log.html Thanks, TF-A LTS team

1 year, 8 months

1
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Canceled event with note: TF-A Tech Forum @ Thu Jun 27, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling as no topic planned. Regards, Olivier. " TF-A Tech Forum Thursday Jun 27, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 8 months

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Canceled event with note: TF-A Tech Forum @ Thu Jun 13, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling this instance as no topic proposed. Thanks, Olivier. " TF-A Tech Forum Thursday Jun 13, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 8 months

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Canceled event with note: TF-A Tech Forum @ Thu May 30, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling for this week as no topic proposed. Thanks, Olivier. " TF-A Tech Forum Thursday May 30, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 9 months

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Trusted Firmware v2.10 Release Announcement

by Olivier Deprez

Hi All, We are pleased to announce the formal release of Trusted Firmware-A version 2.10 bundle of project deliverables. This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium, RMM and TF-A OpenCI Scripts/Jobs 2.10 releases involving the tagging of multiple repositories. These went live on 22nd November 2023. Please find references to tags and change logs at the end of this email. Many thanks to the community for the active engagement in delivering this release! Notable Features of the Version 2.10 Release are as follows: TF-A/EL3 Root World * New Features: * Firmware handoff library support * Improvements to BL31 runtime exception handling * Context management refactoring for RME/4 worlds * Gelas, Nevis & Travis CPUs support * V8.9 features enabled (FEAT_ HAFT, RPRFM, LRCPC3, MTE_PERM) TF-A Boot BL1/BL2 * New Features * Trusted Boot support for ECDSA (Elliptic Curve Digital Signature Algorithm) * Migrated to PSA crypto API’s * Improved the GUID Partition Table (GPT) parser. * Various security Improvements and threat Model updates for ARM CCA * Signer id extraction Implementation Hafnium/SEL2 SPM * New Features: * FF-A v1.2: FFA_YIELD with time-out; EL3 SPMDs LSPs communication; memory sharing updates. * Memory region relative base address field support in SP manifests. * Interrupt re-configuration hypervisor calls. * Memory management: S2 PT NS/S IPA split * SMCCCv1.2+ compliance fixes. * Feature parity test improvements, EL3 SPMC and Hafnium (S-EL2 SPMC) TF-RMM/REL2 * New Feature/Support * Fenimore v1.0 EAC5 aligned implementation. * TFTF Enhancements for RME testing * Initial CBMC support * NS SME support in RMM * BTI support for RMM Errata * Errata implemented (1xCortex-X2/ Matterhorn-ELP, 1xCortex-A710/Matterhorn, 1xNeoverse N2/Perseus, 2xNeoverse V2/Demeter, Makalu ELP/Cortex X3, Klein/Cortex-A510) * Fix some minor defects with version in a few errata that applies for some follow up revisions of the CPUs. (Neoverse V1, Cortex-X2, Cortex-A710) TF-A Tests * Core * Added errata management firmware interface tests. * Added firmware handoff tests. * Introduced RAS KFH support test. * SPM/FF-A * Support SMCCCv1.2 extended GP registers set. * Test SMCCC compliance at the non-secure physical instance. * Test secure eSPI interrupt handling. * Test FF-A v1.2 FFA_PARTITION_INFO_GET_REGS interface. * RMM * Added FPU/SVE/SME tests * Added multiple REC single CPU tests. * Added PAuth support in Realms tests. * Added PMU tests. Platform Support * New platforms added: * Aspeed AST2700, NXP IMX93, Intel Agilex5, Nuvoton NPCM845x, QTI MDM9607, MSM8909, MSM8939, ST STM32MP2 Release tags across repositories: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tag/?h=v2.10 https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tag/?h=v2.10 https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tag/?h=v2.10 https://git.trustedfirmware.org/ci/tf-a-job-configs.git/tag/?h=v2.10 https://git.trustedfirmware.org/hafnium/hafnium.git/tag/?h=v2.10 https://git.trustedfirmware.org/ci/hafnium-ci-scripts.git/tag/?h=v2.10 https://git.trustedfirmware.org/ci/hafnium-job-configs.git/tag/?h=v2.10 https://git.trustedfirmware.org/TF-RMM/tf-rmm.git/tag/?h=tf-rmm-v0.4.0 Change logs: https://trustedfirmware-a.readthedocs.io/en/v2.10/change-log.html#id1 https://trustedfirmware-a-tests.readthedocs.io/en/v2.10/change-log.html#ver… https://hafnium.readthedocs.io/en/latest/change-log.html#v2-10 https://tf-rmm.readthedocs.io/en/tf-rmm-v0.4.0/about/change-log.html#v0-4-0 Regards, Olivier.

1 year, 9 months

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regarding AS and AR values with clang compiler

by Nagal, Amit

Hi , We are trying to build the TF-A code using clang compiler . Instructions are followed as per the conf page https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/initial-… 1. export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- 2. make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all in our side , make CC=/tools/installs/arm/safety/armcc/6.6.2/bin/armclang PLAT=zynqmp distclean 3. with steps 1) and 2) , we observe the value of AS and AR getting set as below: AS = /tools/installs/arm/safety/armcc/6.6.2/bin/armclang -c -x assembler-with-cpp -target aarch64-arm-none-eabi -march=armv8-a AR = <path-to-aarch64-gcc>/bin/aarch64-linux-gnu-ar 4. However in /tools/installs/arm/safety/armcc/6.6.2/bin , clang tool specific AS points to armasm and AR points to armar utility. 5. From above output in point 4 , we can see that AS and AR does not refer to clang toolchain utilities armasm and armar. From point 3) , AS still points to armclang utility only instead of armasm , while AR still points to aarch64-linux-gnu-ar instead of armar . 6. Can we be guided if the above outputs are correct to use wrt TF-A code build using clang compiler ? And whether any modifications can be done to point AS and AR to clang toolchain specific utilities as mentioned in step 4. Regards Amit

1 year, 9 months

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Maintainer for Marvell platforms

by Manish Pandey2

Hi, We do not have active maintainer for Marvell platform. As per docs/about/maintainers.rst the current maintainer is "Konstantin Porotchkin <kostap(a)marvell.com>". Is anybody willing to take ownership of the platform, preferably people who have contributed to this platform in past. Thanks Manish

1 year, 9 months

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Make TF-A (bl31) (El3 firmware) preemtible

by Kamlesh Gurudasani

Clock and power management in ATF, preemption issue. I have seen that multiple Vendors are using arm scmi protocol to do clock management in bl31[0][1]. The problem with such implementations is any long running SCMI operations (like PLL locking for example) will hold the core in EL3 for extended period of time, adding to latency of NS EL1 interrupt handling as ATF is not preemptible. This problem can be solved by making ATF preemptible, similar to how OP-TEE does it by by implementing a remote procedural call after it receives a interrupt. [2]How Linux does SMC call with YIELD flag enabled. [3]How OP-TEE handles the timer interrupt [4]How Linux receives an interrupt which came in EL3->SEL1 As quoted in exception Handling document in ATF docs[5] "Receive exceptions, but handle part of the exception in EL3, and delegate processing of the error to dedicated software stack running at lower secure ELs (as above); additionally, the Normal world may also be required to participate in the handling, or be notified of such events (for example, as an event). In this scheme, exception handling potentially and maximally spans all ELs in both Secure and Normal worlds." From this we can understand that we can delegate the exception to EL1 if we are already in EL3. (way to preempt) We are aware that ARM v8.4-A onwards arch are having a SEL2 level with which we can run a vendor specific firmware parallel to TEE at SEL1 in a secure partition. But how we do handle clock and power management for version which doesn't support SEL2? We don't want to put it in TEE as it will constraint our devices to that specific TEE. I am starting to work on a proposal to make ATF preemptible similar to how OP-TEE is doing it. a)Will the similar approach from OP-TEE if implemented and working be accepted by ATF upstream? The SMC call with YIELD option will only be preemtible so will not affect the normal flow. b)As quoted in Trusted Firmware-A Document[6] Page 94, "Yielding calls are reserved exclusively for Trusted OS providers" "Yielding 0- 1 Reserved for existing Armv7-A calls Yielding 2-63 Trusted OS Standard Calls" Can this range be consumed within ATF/bl31 firmware or is it necessary to forward all yielding calls to Trusted OS? [0]https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/st/… [1]https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/21840 [2]https://elixir.bootlin.com/linux/v6.9-rc3/source/drivers/tee/optee/smc_ab… [3]https://github.com/OP-TEE/optee_os/blob/fc57019cb35c8c1bad66fc6d814ace5de… [4]https://elixir.bootlin.com/linux/v6.9-rc3/source/drivers/tee/optee/smc_ab… [5]https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/com… [6]https://trustedfirmware-a.readthedocs.io/_/downloads/en/latest/pdf/ Regards, Kamlesh

1 year, 9 months

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Changelog for v2.11 Release

by Juan Pablo Conde

Hello everyone, Please take a look at the changelog for your respective platforms ahead of the TF-A v2.11 release. The changelog is autogenerated from the commit messages of the patches that have been merged since the v2.10 release. Here's your chance to give us guidance on any small manual adjustments you would like to see. Patch: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/28891 Rendered Version: https://ci-builds.trustedfirmware.org/static-files/M6zhCYgGrsu6KLmMu2AdTlI2… Thanks, Juan Pablo

1 year, 9 months

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documentation - secure interrupt handling in EL3 for arm gic v2

by Nagal, Amit

Hi , There is a contradiction present in TF-A documentation whether secure interrupts can be handled in EL3 for arm gic v2 case . 1. Referring https://trustedfirmware-a.readthedocs.io/en/latest/design/interrupt-framewo… It says secure interrupts can't be handled in EL3 . Refer statement : "In Arm GICv2, all secure interrupts are assumed to be handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they cannot be handled in EL3." 2. Referring https://trustedfirmware-a.readthedocs.io/en/latest/components/platform-inte… It says secure interrupts can be handled in EL3 , When GICV2_G0_FOR_EL3 is 1 . Refer below statements : For interrupt type INTR_TYPE_EL3: When GICV2_G0_FOR_EL3 is 0, it returns false, indicating no support for EL3 interrupts. When GICV2_G0_FOR_EL3 is 1, it returns true, indicating support for EL3 interrupts. can this be clarified ? Regards Amit

1 year, 9 months

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Trusted Firmware-A LTS v2.8.19 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.19 is now available. This release contains the following patches. 1e785ab6a feat(spmd): initialize SCR_EL3.EEL2 bit at RESET [1] 9d40eff24 fix(spmd): avoid restoring ctx during first entry into spmc [2] 02633263a fix(cpus): workaround for Cortex-A715 erratum 2728106 [3] 9b5d75b17 fix(cpus): workaround for Cortex-X4 erratum 2740089 [4] d0a74e38c fix(cpus): workaround for Cortex-X4 erratum 2763018 [5] 6c9135fb0 docs: decrease the minimum supported OpenSSL [6] [1] https://review.trustedfirmware.org/q/Ia246235aa8d8004dcaf845f21c8aeeabbbbbe… [2] https://review.trustedfirmware.org/q/I368088ece60826fd7a6aa423ba584a89d32fc… [3] https://review.trustedfirmware.org/q/Ic825f9942e7eb13893fdbb44a2090b897758c… [4] https://review.trustedfirmware.org/q/I1d0fa4dd383437044a4467591f65a4a8514ca… [5] https://review.trustedfirmware.org/q/Ia188e08c2eb2952923ec72e2a56efdeea836f… [6] https://review.trustedfirmware.org/q/I5c60907337f10b05d5c43b0384247c5d4135d… Thanks, TF-A LTS team

1 year, 9 months

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Canceled event with note: TF-A Tech Forum @ Thu May 16, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling as no topic proposed this week. Thanks & Regards, Olivier. " TF-A Tech Forum Thursday May 16, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 9 months

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Firmware-A v2.10 release code freeze notification

by Olivier Deprez

Hi All, The next release of the Firmware-A bundle of projects tagged v2.10 has an expected code freeze date of Nov, 7th 2023. Refer to the Release Cadence section from TF-A documentation (https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/docs/about…). Closing out the release takes around 6-10 working days after the code freeze. Preparations tasks for v2.10 release should start in coming month. We want to ensure that planned feature patches for the release are submitted in good time for the review process to conclude. As a kind recommendation and a matter of sharing CI resources, please launch CI jobs with care e.g.: -For simple platform, docs changes, or one liners, use Allow-CI+1 label (no need for a full Allow-CI+2 run). -For large patch stacks use Allow-CI+2 at top of the patch stack (and if required few individual Allow+CI+1 in the middle of the patch stack). -Carefully analyze results and fix the change if required, before launching new jobs on the same change. -If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not added as a gerrit comment on the patch right away please be patient as under heavy load CI jobs can be queued and in extreme conditions it can be over an hour before the Build start notice is issued. Issuing another Allow-CI+1 or Allow-CI+2 label will just result in an additional job being queued. Thanks & Regards, Olivier.

1 year, 9 months

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FAULT_INJECTION_SUPPORT - FIEN bit

by Nagal, Amit

Hi, Referring https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/getti… it says : ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault injection from lower Els. Referring https://github.com/ARM-software/arm-trusted-firmware/blob/master/lib/el3_ru… FAULT_INJECTION_SUPPORT enables FIEN bit. #if FAULT_INJECTION_SUPPORT /* Enable fault injection from lower ELs */ scr_el3 |= SCR_FIEN_BIT; #endif Question : 1. Do we have any relevant documentation from arm which specifies FIEN bit can be enabled from armv8.4 ? 2. In cortex a-53 technical reference manual, SCR_EL3 does not have FIEN bit , bit 21 is marked reserved . In cortex a-78 technical reference manual , manual does not have details for SCR_EL3 . I want to know whether on Armv8.2-a based cores like cortex a-78 , is the FIEN bit field marked reserved in SCR_EL3 register or is available functionality wise as in armv8.4 ? Please help with above query. Regards Amit

1 year, 9 months

2
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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 14 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 425813: Memory - corruptions (OVERRUN) /drivers/arm/css/dsu/dsu.c: 133 in cluster_on_dsu_pmu_context_restore() ________________________________________________________________________________________________________ *** CID 425813: Memory - corruptions (OVERRUN) /drivers/arm/css/dsu/dsu.c: 133 in cluster_on_dsu_pmu_context_restore() 127 void cluster_on_dsu_pmu_context_restore(void) 128 { 129 unsigned int cluster_pos; 130 131 cluster_pos = (unsigned int) plat_cluster_id_by_mpidr(read_mpidr_el1()); 132 >>> CID 425813: Memory - corruptions (OVERRUN) >>> "&cluster_pmu_context[cluster_pos]" evaluates to an address that is at byte offset 138720 of an array of 544 bytes. 133 restore_dsu_pmu_state(&cluster_pmu_context[cluster_pos]); ** CID 425812: Memory - corruptions (OVERRUN) /drivers/arm/css/dsu/dsu.c: 81 in cluster_off_dsu_pmu_context_save() ________________________________________________________________________________________________________ *** CID 425812: Memory - corruptions (OVERRUN) /drivers/arm/css/dsu/dsu.c: 81 in cluster_off_dsu_pmu_context_save() 75 void cluster_off_dsu_pmu_context_save(void) 76 { 77 unsigned int cluster_pos; 78 79 cluster_pos = (unsigned int) plat_cluster_id_by_mpidr(read_mpidr_el1()); 80 >>> CID 425812: Memory - corruptions (OVERRUN) >>> "&cluster_pmu_context[cluster_pos]" evaluates to an address that is at byte offset 138720 of an array of 544 bytes. 81 save_dsu_pmu_state(&cluster_pmu_context[cluster_pos]); 82 } 83 84 /***************************************************************************** 85 * This function, restore_dsu_pmu_state, restores the state of the 86 * Performance Monitoring Unit (PMU) from a previously saved state. ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 9 months

1
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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 8 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 425810: High impact quality (WRITE_CONST_FIELD) /plat/nxp/s32/s32g274ardb2/plat_console.c: 17 in console_s32g2_register() ________________________________________________________________________________________________________ *** CID 425810: High impact quality (WRITE_CONST_FIELD) /plat/nxp/s32/s32g274ardb2/plat_console.c: 17 in console_s32g2_register() 11 12 void console_s32g2_register(void) 13 { 14 static console_t s32g2_console; 15 int ret; 16 >>> CID 425810: High impact quality (WRITE_CONST_FIELD) >>> A write to an aggregate overwrites a const-qualified field within the aggregate. 17 (void)memset(&s32g2_console, 0, sizeof(s32g2_console)); 18 19 ret = console_linflex_register(UART_BASE, UART_CLOCK_HZ, 20 UART_BAUDRATE, &s32g2_console); 21 if (ret == 0) { 22 panic(); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 9 months

1
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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 7 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 14 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 7 of 7 defect(s) ** CID 425803: Control flow issues (DEADCODE) /mbedtls/library/psa_crypto_aead.c: 314 in mbedtls_psa_aead_decrypt() ________________________________________________________________________________________________________ *** CID 425803: Control flow issues (DEADCODE) /mbedtls/library/psa_crypto_aead.c: 314 in mbedtls_psa_aead_decrypt() 308 } 309 310 exit: 311 mbedtls_psa_aead_abort(&operation); 312 313 if (status == PSA_SUCCESS) { >>> CID 425803: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "*plaintext_length = ciphert...". 314 *plaintext_length = ciphertext_length - operation.tag_length; 315 } 316 return status; 317 } 318 319 /* Set the key and algorithm for a multipart authenticated encryption ** CID 425802: Control flow issues (DEADCODE) /mbedtls/library/x509_crt.c: 2750 in x509_inet_pton_ipv6() ________________________________________________________________________________________________________ *** CID 425802: Control flow issues (DEADCODE) /mbedtls/library/x509_crt.c: 2750 in x509_inet_pton_ipv6() 2744 MBEDTLS_PUT_UINT16_BE(group, addr, nonzero_groups); 2745 nonzero_groups++; 2746 if (*p == '\0') { 2747 break; 2748 } else if (*p == '.') { 2749 /* Don't accept IPv4 too early or late */ >>> CID 425802: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "zero_group_start == -1" inside this statement: "if ((nonzero_groups == 0 &&...". 2750 if ((nonzero_groups == 0 && zero_group_start == -1) || 2751 nonzero_groups >= 7) { 2752 break; 2753 } 2754 2755 /* Walk back to prior ':', then parse as IPv4-mapped */ ** CID 425801: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 306 in mbedtls_psa_aead_decrypt() ________________________________________________________________________________________________________ *** CID 425801: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 306 in mbedtls_psa_aead_decrypt() 300 (void) additional_data; 301 (void) additional_data_length; 302 (void) plaintext; 303 return PSA_ERROR_NOT_SUPPORTED; 304 } 305 >>> CID 425801: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "if (status == 0) { *plain...". 306 if (status == PSA_SUCCESS) { 307 *plaintext_length = ciphertext_length - operation.tag_length; 308 } 309 310 exit: 311 mbedtls_psa_aead_abort(&operation); ** CID 425800: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 612 in mbedtls_psa_aead_finish() ________________________________________________________________________________________________________ *** CID 425800: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 612 in mbedtls_psa_aead_finish() 606 (void) tag_size; 607 (void) tag_length; 608 609 return PSA_ERROR_NOT_SUPPORTED; 610 } 611 >>> CID 425800: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "if (status == 0) { *ciphe...". 612 if (status == PSA_SUCCESS) { 613 /* This will be zero for all supported algorithms currently, but left 614 * here for future support. */ 615 *ciphertext_length = finish_output_size; 616 *tag_length = operation->tag_length; 617 } ** CID 425799: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 110 in psa_aead_setup() ________________________________________________________________________________________________________ *** CID 425799: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 110 in psa_aead_setup() 104 default: 105 (void) status; 106 (void) key_buffer; 107 return PSA_ERROR_NOT_SUPPORTED; 108 } 109 >>> CID 425799: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "operation->key_type = psa_g...". 110 operation->key_type = psa_get_key_type(attributes); 111 112 operation->tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(alg); 113 114 return PSA_SUCCESS; 115 } ** CID 425798: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 541 in mbedtls_psa_aead_update() ________________________________________________________________________________________________________ *** CID 425798: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 541 in mbedtls_psa_aead_update() 535 (void) output; 536 (void) output_size; 537 538 return PSA_ERROR_NOT_SUPPORTED; 539 } 540 >>> CID 425798: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "if (status == 0) { *outpu...". 541 if (status == PSA_SUCCESS) { 542 *output_length = update_output_length; 543 } 544 545 return status; 546 } ** CID 425797: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 196 in mbedtls_psa_aead_encrypt() ________________________________________________________________________________________________________ *** CID 425797: Control flow issues (UNREACHABLE) /mbedtls/library/psa_crypto_aead.c: 196 in mbedtls_psa_aead_encrypt() 190 (void) additional_data; 191 (void) additional_data_length; 192 (void) plaintext; 193 return PSA_ERROR_NOT_SUPPORTED; 194 } 195 >>> CID 425797: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "if (status == 0) { *ciphe...". 196 if (status == PSA_SUCCESS) { 197 *ciphertext_length = plaintext_length + operation.tag_length; 198 } 199 200 exit: 201 mbedtls_psa_aead_abort(&operation); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 9 months

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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 425708: Null pointer dereferences (NULL_RETURNS) ________________________________________________________________________________________________________ *** CID 425708: Null pointer dereferences (NULL_RETURNS) /plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c: 279 in pm_self_suspend() 273 const struct pm_proc *proc = pm_get_proc(cpuid); 274 275 /* 276 * Do client specific suspend operations 277 * (e.g. set powerdown request bit) 278 */ >>> CID 425708: Null pointer dereferences (NULL_RETURNS) >>> Dereferencing a pointer that might be "NULL" "proc" when calling "pm_client_suspend". 279 pm_client_suspend(proc, state); 280 /* Send request to the PMU */ 281 PM_PACK_PAYLOAD6(payload, PM_SELF_SUSPEND, proc->node_id, latency, 282 state, address, (address >> 32)); 283 return pm_ipi_send_sync(proc, payload, NULL, 0); 284 } ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 10 months

1
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TF-A Tech Forum : TF-RMM CPPCheck integration and TF-A-Tests testing

by Soby Mathew

Hi Everyone, This Thursday , Shruti from TF-RMM team will discuss the following topics in TF-A Tech Forum : 1. Integration of CPPCheck in TF-RMM * CPPCheck is an open-source static analyzer with addon MISRA checker. In this talk, we will discuss the CPPCheck integration in TF-RMM build system and demonstrate the same. 2. TF-A-Tests enhancements and testing for TF-RMM * Discuss new enhancements in TF-A-Tests for Realm Payload tests including Creating, Loading & Running Realm Payload, testing multiple Rec’s and PSCI support for Realms. We will also cover some Test framework conventions and aspects of Stage2 Memory Management, Realm Memory Exception Model testing. Best Regards Soby Mathew -----Original Appointment----- From: Trusted Firmware Public Meetings <linaro.org_havjv2figrh5egaiurb229pd8c(a)group.calendar.google.com> Sent: Thursday, February 22, 2024 10:13 PM To: Trusted Firmware Public Meetings; tf-a(a)lists.trustedfirmware.org; marek.bykowski(a)gmail.com; okash.khawaja(a)gmail.com Subject: TF-A Tech Forum When: 02 May 2024 16:00-17:00 Europe/London. Where: TF-A Tech Forum We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this This event has been updated with a note: "Updating invite link" Changed: description Description CHANGED We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/<https://www.google.com/url?q=https%3A%2F%2Fwww.trustedfirmware.org%2Fmeetin…> Trusted Firmware is inviting you to a scheduled Zoom meeting. Join Zoom Meeting https://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvd…<https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fmy%2Ftruste…> One tap mobile +16465588656,,9159704974# US (New York) +16699009128,,9159704974# US (San Jose) Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-free Meeting ID: 915 970 4974 Find your local number: https://zoom.us/u/ad27hc6t7h<https://www.google.com/url?q=https%3A%2F%2Fzoom.us%2Fu%2Fad27hc6t7h&sa=D&us…> When Every 2 weeks from 9am to 10am on Thursday (Mountain Standard Time - Phoenix) Guests tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> marek.bykowski(a)gmail.com<mailto:marek.bykowski@gmail.com> okash.khawaja(a)gmail.com<mailto:okash.khawaja@gmail.com> View all guest info<https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1…> RSVP for tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> for all events in this series Yes<https://calendar.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tM…> No<https://calendar.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tM…> Maybe<https://calendar.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tM…> More options<https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1…> Invitation from Google Calendar<https://calendar.google.com/calendar/> You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more<https://support.google.com/calendar/answer/37135#forwarding>

1 year, 10 months

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Trusted Firmware-A LTS v2.10.4 Release Announcement

by ci_notify＠trustedfirmware.org

The content of this message was lost. It was probably cross-posted to multiple lists and previously handled on another list.

1 year, 10 months

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Trusted Firmware-A LTS v2.8.18 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.18 is now available. This release contains the following patches. a1cb5f656 feat(mbedtls): upgrade to version v2.28.8 [1] [1] https://review.trustedfirmware.org/q/Ic1e6debbfc0f5667a8872482ccfb104c1a92e… Thanks, TF-A LTS team

1 year, 10 months

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Need a mechanism to easily define platform-independent SMC FIDs

by Julius Werner

Hi, I would like to restart a discussion that we already had a few years ago on a thread called "SMC to intentionally trigger a panic in TF-A" (https://lists.trustedfirmware.org/archives/search?mlist=tf-a%40lists.truste…) but that petered out without any real resolution (and resulted in me ultimately not implementing the feature I was hoping to add). Basically, we are repeatedly stumbling over the problem that we have a use case for some platform-independent SMC API that we want to implement in TF-A, but don't have an appropriate SMC FID range to put it. My request from a few years ago was about implementing a call to intentionally trigger a panic in TF-A for test-automation purposes. Today we came up with a use case where a Trusted OS wants to query BL31 about the location of a shared log buffer: https://review.trustedfirmware.org/20478 . Currently, the available SMC ranges are Arm, CPU, SiP, OEM, Standard, Hypervisor, TA and TOS. The SiP, OEM and TOS ranges are all specific to a single silicon vendor, OEM or trusted OS implementation, so they are not good targets to implement APIs that would make sense to be shared among multiple of these. In theory, the Standard range would probably be the right target to implement calls that are independently useful for multiple platforms / OSes... but as far as I understand, adding a new call to that range requires petitioning Arm to update the SMC calling convention itself, which is a ridiculously high bar to implement a small utility API. In practice, the only choice we have for implementing these kinds of calls is to let every OEM, SiP or TOS assign its own (different) FID for it and then write separate SMC handlers for each in TF-A that all end up calling the same underlying function... which creates a lot of unnecessary code duplication and identifier soup (especially in the case of SMCs for the non-secure OS which would then be implemented by a platform-independent Linux driver that needs a big mapping table to decide which FID to use on which platform for the same API). I think it would be very useful if there was another range of easily allocatable FIDs that developers could just add to with a simple TF-A CL without having to go through a huge specification update process. There are still 41 OENs unused in the Arm SMCCC, and I don't think any new ones were added in the 10 years that the specification existed... so we are really not going to run out of them any time soon. If we could get even one of those OENs for this purpose, we would have 64K FIDs to use up for our small, simple platform-independent API needs, which should last us a long while. We could maybe call it the "Secure Monitor range" and say the FIDs are specific to a certain implementation of Secure Monitor (e.g. TF-A). Then there could just be a header file in the TF-A sources that serves as the authoritative FID assignment table for TF-A, and anyone with a sufficiently useful idea (subject to TF-A maintainer review) for a platform-independent API like this could add it there by just uploading a patch. I recently argued for a similar "simple tag allocation" concept on https://github.com/FirmwareHandoff/firmware_handoff and it found support there, so I hope I'll be able to convince you that it would be useful for SMC FIDs as well?

1 year, 10 months

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