Hi All,
I'm new to TF-A. While working on enabling Linux on A-520 FVP, I ran into
an issue that I wanted to ask about.
My stack looks like this:TF-A->U-boot->kernel. Initially I was able to boot
on Base FVP(FVP_Base_RevC-2xAEMvA) and get to the linux console. Now we
need to enable the same for A-520 FVP as our soc will be A-520. I saw the
crash happening very early in "cpu_helpers.S.
I made the change in plat/arm/board/fvp/platform.mk by adding
lib/cpus/aarch64/cortex_a520.S in one of the FVP_CPU_LIBS and enabling the
ERRATA_A520_2938996, ERRATA_A520_2858100 and ERRATA_A520_2630792. These
changes helped me get past the TF-A and now i ' m seeing a crash inside
kernel in pci.
16.720973] pci-host-generic 40000000.pci: host bridge /pci@40000000
ranges:
[ 16.721375] pci-host-generic 40000000.pci: MEM
0x0050000000..0x005fffffff -> 0x0050000000
[ 16.722013] pci-host-generic 40000000.pci: ECAM at [mem
0x40000000-0x4fffffff] for [bus 00-ff]
[ 16.723128] pci-host-generic 40000000.pci: PCI host bridge to bus 0000:00
[ 16.723461] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 16.723761] pci_bus 0000:00: root bus resource [mem
0x50000000-0x5fffffff]
[ 16.724101] Internal error: synchronous external abort: 0000000096000010
[#1] SMP
[ 16.724216] Modules linked in:
[ 16.724302] CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted
6.15.0-rc7-dirty #12 PREEMPT
[ 16.724449] Hardware name: FVP Base RevC (DT)
[ 16.724531] pstate: 214000c9 (nzCv daIF +PAN -UAO -TCO +DIT -SSBS
BTYPE=--)
[ 16.724666] pc : pci_generic_config_read+0x38/0xb8
[ 16.724802] lr : pci_generic_config_read+0x24/0xb8
[ 16.724939] sp : ffff80008272b940
[ 16.725012] x29: ffff80008272b940 x28: 0000000000000000 x27:
ffff800081dc00b0
[ 16.725205] x26: ffff800081ec9060 x25: ffff800081ec9078 x24:
ffff80008266a9a0
[ 16.725401] x23: 0000000000000000 x22: ffff80008272b9f4 x21:
ffff000800fa8000
[ 16.725594] x20: ffff80008272b964 x19: 0000000000000004 x18:
0000000000000006
[ 16.725781] x17: 6666666666663478 x16: 302d303030303030 x15:
ffff800082edbbbf
[ 16.725980] x14: 0000000000000000 x13: 0000000000000000 x12:
0000000000000000
[ 16.726166] x11: 0000000000000001 x10: 3ea1f6d484b7e318 x9 :
69631046f78aed23
[ 16.726355] x8 : ffff000800169108 x7 : ffff800082250960 x6 :
00000000000000ff
[ 16.726547] x5 : 0000000000000000 x4 : 0000000000000000 x3 :
ffff800090000000
[ 16.726738] x2 : 0000000000000000 x1 : 0000000000000000 x0 :
ffff800090000000
Do i need to do enable somethign else in TF-A?
I tried adding :
pci: pci@40000000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
bus-range = <0x0 0xff>;
reg = <0x0 0x40000000 0x0 0x10000000>;
ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0
0x10000000>;
};
in plat/arm/board/fvp/fdts/fvp_soc_fw_config.dts but it does not help.
Also I see the kernel is not able to bring all the cpu's online:
[ 0.040364] smp: Bringing up secondary CPUs ...
[ 5.116993] CPU1: failed to come online
[ 5.117063] CPU1: failed in unknown state : 0x0
[ 10.266076] CPU2: failed to come online
[ 10.266152] CPU2: failed in unknown state : 0x0
[ 15.415178] CPU3: failed to come online
[ 15.415247] CPU3: failed in unknown state : 0x0
[ 15.421021] psci: failed to boot CPU4 (-22)
[ 15.421099] CPU4: failed to boot: -22
[ 15.425045] psci: failed to boot CPU5 (-22)
[ 15.425123] CPU5: failed to boot: -22
[ 15.429079] psci: failed to boot CPU6 (-22)
[ 15.429157] CPU6: failed to boot: -22
[ 15.433153] psci: failed to boot CPU7 (-22)
[ 15.433227] CPU7: failed to boot: -22
[ 15.433587] smp: Brought up 1 node, 1 CPU
[ 15.433672] SMP: Total of 1 processors activated.
[ 15.433746] CPU: All CPU(s) started at EL2
I’m still getting familiar with the codebase and community, so apologies if
this has already been addressed. I’d really appreciate any guidance or
pointers, and if this is a known issue or good for a first-time
contributor, I’d be happy to help.
Regards,
Shaunak
Hi folks,
We are planning on going live with the migration of the TF.org Open CI tomorrow, Friday 30th May, which will migrate Jenkins (ci.trustedfirmware.org) from on-premises to cloud-managed infrastructure. We expect a downtime of 2-4 hours beginning at 14:30 GMT+1, during which anything which interacts with Jenkins will be unavailable.
Please note that the Jenkins build history is not being transferred - if you have Gerrit changes in review with the Allow-CI+1/+2 label, you will need to retrigger the CI once migration is complete by reapplying the label.
We will send out a follow-up email once we have restored service availability.
Regards,
Chris
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Hi All,
We are pleased to announce the formal release of Trusted Firmware-A version 2.13 bundle of project deliverables.
This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium, TF-RMM, Trusted Services, and TF-A OpenCI scripts/jobs components.
These went live on May, 22nd 2025.
Please find references to tags and change logs at the end of this email.
Many thanks to the trustedfirmware.org community for the active engagement in delivering this release!
Notable features of the release version 2.13 are as follows:
TF-A/EL3
* Alto CPU support
*
Architecture feature support for PMUv3p9. PAUTH_LR and SPE_FDS.
* Refactor PSCI to let each CPU core initialise its own context, allowing TF-A to natively handle asymmetric configurations
*
PSCI Powerdown abandon feature support
*
SMCCC_FEATURE_AVAILABILITY support based on SMCCC v1.5 specification
* Firmware Handoff
* Library enhancements to add more TE types in library
* All BL interfaces for FVP are now migrated to use Transfer List along in different boot scenarios (RESET_TO_BL1/BL2/BL31)
*
TC platform is now using Transfer List for booting
* HOB creation Library (from edk2) is now hosted in TF-A
* New Platforms: mt8189, mt8196, qcs615, RK3576, AM62L
Boot flow
* Feature Additions
* Added discrete TPM support in BL1/BL2 for the RPi3 platform.
*
Support for MbedTLS PSA Crypto with ROMLIB on FVP.
*
Redesigned PSA Crypto Key ID management to avoid repeated key creation/destruction.
*
Test Additions
*
Support for MbedTLS PSA Crypto with ROMLIB on FVP.
*
Added basic boot test for TF-RMM with TF-A and TFTF (Realm Payload) in Jenkins CI.
*
Integrated DRTM ACS test suite into TF-A Jenkins CI.
*
Added missing test configuration for ROTPK in register on FVP platform.
*
Build System
*
Refactored ROTPK key/hash generation to auto-generate required files during build.
*
mbedTLS Improvements
*
Migrated to mbedTLS version 3.6.3.
Errata/Security mitigations (CPU/GIC)
*
CVE-2024-5660, CVE-2024-7881
* Cortex-A510, Cortex-A715, Cortex-X4, Cortex-X925, Neoverse V3
Hafnium/SPM (S-EL2)
* FF-A v1.2 completed: indirect messaging with service UUIDs.
* FF-A v1.3 early adoption: Update to FFA_MEM_PERM_GET ABIs.
* StMM integration: provide HOB structure as boot information.
* Power management update:
* Bootstrapped secondary vCPUs on secondary cores power on flows.
* SP's subscription to the power off event.
* SP loading: SP artefacts can be bundled in a TL format. I.e SP binary and SP manifest (DTB).
* Resuming ECs for interrupt handling assisted by NWd Scheduler when the SP is in waiting state, with sri-interrupts-policy field in the SP manifest.
TF-RMM (R-EL2)
* Deprivileging RMM code via EL0 App support
*
Added some support for some RMMv1.1 APIs - "RMI_DEV_MEM_(UN)MAP", support for device granules in "RMI_GRANULE_DELEGATE" and "RMI_GRANULE_UNDELEGATE".
*
Additional hardening of RMM via compiler flags `-fstack-protector-strong`, '-Wextra', '-Wstrict-overflow', '-D_FORTIFY_SOURCE=2' and '-Wnull-dereference'.
*
New platform support for RD-V3-R1 and RD-V3-R1-Cfg1 FVPs.
*
Dynamic discovery of PCIE Root complex topology and device memory from the Boot manifest.
Trusted Services (v1.2.0)
* Introduced the fTPM SP. The implementation is experimental.
*
Introduce the new Arm Reference Design-1 AE platform targeting the Automotive segment. It features
high-performance Arm Neoverse V3AE Application Processor compute system, Arm Cortex-R82AE based Safety Island, and
a Runtime Security Engine (RSE) for enhanced security.
*
Updated the se-proxy deployment and added support for the Firmware Update Proxy service. The FWU Proxy implements a Platform Security Firmware Update for the A-profile Arm Architecture<https://developer.arm.com/documentation/den0118/latest/> compliant FWU Agent which runs a PSA Certified Firmware Update API 1.0<https://arm-software.github.io/psa-api/fwu/1.0/> compliant client as its backend.
TF-A Tests
* Enhancements to fuzzing tests (EL3 vendor specific SMC, SDEI, FF-A interface, capability for randomized fuzzing inputs)
* Functionality test
* Firmware Handoff : AArch32 tests and event log testing
* SMCCC_ARCH_FEATURE_AVAILABILITY
* RAS system registers, FPMR, SCTLR2, THE and D128
* validate psci_is_last_cpu_to_idle_at_pwrlvl
* SPM/FF-A : HOB generation, PPI timer interrupts, v1.2 RXTX headers
* RMM: Tests introduced for majority of features developed in RMM
* Platform Support
* Versal NET
* Versal
* Neoverse-RD
Release tags across repositories:
https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r…https://git.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags…https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-ci-scripts/+/refs/t…https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-job-configs/+/refs/…https://git.trustedfirmware.org/plugins/gitiles/hafnium/hafnium.git/+/refs/…https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-ci-scripts/+/ref…https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-job-configs/+/re…https://git.trustedfirmware.org/plugins/gitiles/TF-RMM/tf-rmm/+/refs/tags/t…https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/…
Change logs:
https://trustedfirmware-a.readthedocs.io/en/v2.13.0/change-log.html#id1https://trustedfirmware-a-tests.readthedocs.io/en/v2.13.0/change-log.html#v…https://hafnium.readthedocs.io/en/v2.13.0/change-log.html#v2-13https://tf-rmm.readthedocs.io/en/latest/about/change-log.html#v0-7-0https://trusted-services.readthedocs.io/en/stable/project/change-log.html#v…
Regards,
Olivier.
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The email was moderated, re-sending on behalf of Andrei.
________________________________
From: Andrei Stefanescu <andrei.stefanescu(a)nxp.com>
Sent: 13 May 2025 12:35
To: tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org>
Cc: Ghennadi Procopciuc <ghennadi.procopciuc(a)nxp.com>; Ciprian Marian Costea <ciprianmarian.costea(a)nxp.com>; Alexandru-Catalin Ionita <alexandru-catalin.ionita(a)nxp.com>
Subject: Question about memory mapping attributes for MT_DEVICE
Hi,
I noticed that the memory mapping attributes for MT_DEVICE memory are defined to: nGnRE [1]. Why was nGnRE selected instead of nGnRnE?
Platforms which have USE_COHERENT_MEM set to 1 will map the coherent memory area as MT_DEVICE. This area is helpful for cases where a backery lock is shared between cores which have MMU enabled and cores which don’t (whose access is equivalent to nGnRnE). This would generate an access attributes mismatch for the coherent memory area.
Would it be ok to send a patch which changes the ATTR_DEVICE to nGnRnE?
Best regards,
Andrei Stefanescu
[1] - https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a.git…
Hi All,
The next release of the Firmware-A bundle of projects tagged v2.13 has an expected code freeze date of May, 2nd 2025.
In order to accommodate the Linaro connect event occurring during the week of May 12th we may extend the release completion date up until the week of May 26th.
v2.13 release preparation tasks start from now.
We want to ensure that planned feature patches for the release are submitted in good time for the review process to conclude.
As a kind recommendation and a matter of sharing CI resources, please launch CI jobs with care e.g.:
-For simple platform, docs changes, or one liners, use Allow-CI+1 label (no need for a full Allow-CI+2 run).
-For large patch stacks use Allow-CI+2 at top of the patch stack (and if required few individual Allow+CI+1 labels in the middle of the patch stack).
-Carefully analyze results and fix the change if required, before launching new jobs on the same change.
-If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not added as a gerrit comment on the patch right away please be patient as under heavy load CI jobs can be queued and in extreme conditions it can be over an hour before the Build start notice is issued. Issuing another Allow-CI+1 or Allow-CI+2 label will just result in an additional job being queued.
Regards,
Olivier.
TF-A Tech Forum
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Hi,
For some reason the invite disappeared from the shared trustedfirmware.org calendar but this message is to state there is no TF-A tech forum planned tomorrow May 1st due to lack of topics.
Thanks & Regards,
Olivier.
Hi All,
We currently have TF-A/OP-TEE support for a platform (ADSP-SC598,
arm cortex A55) in our forked repositories and would like to upstream
our past efforts to align better with newer developments within the projects.
As per the contributor's guide for TF-A, it mentions that it might be a good
idea to start a discussion regarding the same prior to submission of a patch
series.
Currently, the plan is for the initial patch series to support BL31 followed by
another patch series adding support for PSCI. The overarching idea being that
BOOTROM passes control to u-boot SPL, which configures required peripherals
and loads us into TF-A, then proceeding to load OP-TEE, followed by full
uboot/linux.
Please let me know your thoughts/concerns and if I should be proceeding
with the patch series submission.
Regards,
Utsav Agarwal
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)
** CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW)
/services/std_svc/sdei/sdei_event.c: 79 in get_event_entry_target_pe()
________________________________________________________________________________________________________
*** CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW)
/services/std_svc/sdei/sdei_event.c: 79 in get_event_entry_target_pe()
73 */
74 idx = mapsub;
75
76 /* Base of private mappings for this CPU */
77 base_idx = (unsigned int) plat_core_pos_by_mpidr(target_pe);
78 base_idx *= nm;
>>> CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW)
>>> "base_idx", which might have underflowed, is passed to "sdei_private_event_table[base_idx]".
79 cpu_priv_base = &sdei_private_event_table[base_idx];
80 /*
81 * Return the address of the entry at the same index in the
82 * per-CPU event entry.
83 */
84 return &cpu_priv_base[idx];
** CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS)
/services/std_svc/sdei/sdei_intr_mgmt.c: 64 in sdei_is_target_pe_masked()
________________________________________________________________________________________________________
*** CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS)
/services/std_svc/sdei/sdei_intr_mgmt.c: 64 in sdei_is_target_pe_masked()
58
59 /* SDEI states for all cores in the system */
60 static sdei_cpu_state_t cpu_state[PLATFORM_CORE_COUNT];
61
62 bool sdei_is_target_pe_masked(uint64_t target_pe)
63 {
>>> CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS)
>>> Using variable "plat_core_pos_by_mpidr(target_pe)" as an index to array "cpu_state".
64 const sdei_cpu_state_t *state = sdei_get_target_pe_state(target_pe);
65
66 return state->pe_masked;
67 }
68
69 int64_t sdei_pe_mask(void)
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…
I need Gerrit admin's help to delete my old Gerrit account. Who should I
contact?
--
Yu-Ping Wu | Software Engineer | yupingso(a)google.com | +886 937 057 080
Hi,
You must have noticed slowness or breakages with review.trustedfirmware.org or git.trustedfirmware.org during the week.
There are high and lows of network bandwidth usage affecting server availability.
The issue is being investigated but not yet 100% root caused.
Apologies for the frustration and inconvenience that this is causing.
Rest assured the team is on board to resolve this unfortunate situation.
Regards,
Olivier.
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Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 461861: Code maintainability issues (UNUSED_VALUE)
/plat/ti/k3low/common/am62l_psci.c: 35 in am62l_pwr_domain_on()
________________________________________________________________________________________________________
*** CID 461861: Code maintainability issues (UNUSED_VALUE)
/plat/ti/k3low/common/am62l_psci.c: 35 in am62l_pwr_domain_on()
29 int32_t core, ret;
30 uint8_t proc_id;
31
32 core = plat_core_pos_by_mpidr(mpidr);
33 if (core < 0) {
34 ERROR("Could not get target core id: %d\n", core);
>>> CID 461861: Code maintainability issues (UNUSED_VALUE)
>>> Assigning value "-6" to "ret" here, but that stored value is overwritten before it can be used.
35 ret = PSCI_E_INTERN_FAIL;
36 }
37
38 proc_id = (uint8_t)(PLAT_PROC_START_ID + (uint32_t)core);
39
40 ret = ti_sci_proc_request(proc_id);
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…
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Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)
** CID 458349: Integer handling issues (INCOMPATIBLE_CAST)
________________________________________________________________________________________________________
*** CID 458349: Integer handling issues (INCOMPATIBLE_CAST)
/plat/intel/soc/common/socfpga_sip_svc.c: 2190 in sip_smc_handler_v1()
2184 SMC_RET1(handle, status);
2185 } else {
2186 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
2187 }
2188
2189 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR:
>>> CID 458349: Integer handling issues (INCOMPATIBLE_CAST)
>>> Pointer "&x1" points to an object whose effective type is "unsigned long" (64 bits, unsigned) but is dereferenced as a narrower "unsigned int" (32 bits, unsigned). This may lead to unexpected results depending on machine endianness.
2190 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2);
2191 SMC_RET1(handle, status);
2192
2193 case INTEL_SIP_SMC_ATF_BUILD_VER:
2194 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR,
2195 VERSION_MINOR, VERSION_PATCH);
** CID 458348: Integer handling issues (INCOMPATIBLE_CAST)
________________________________________________________________________________________________________
*** CID 458348: Integer handling issues (INCOMPATIBLE_CAST)
/plat/intel/soc/common/socfpga_sip_svc.c: 1250 in sip_smc_handler_v3()
1244 0);
1245 SMC_RET1(handle, status);
1246 }
1247
1248 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT:
1249 {
>>> CID 458348: Integer handling issues (INCOMPATIBLE_CAST)
>>> Pointer "&x4" points to an object whose effective type is "unsigned long" (64 bits, unsigned) but is dereferenced as a narrower "unsigned int" (32 bits, unsigned). This may lead to unexpected results depending on machine endianness.
1250 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3,
1251 (uint32_t *) &x4, &mbox_error);
1252 SMC_RET1(handle, status);
1253 }
1254
1255 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD:
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…
Hi All,
If you're downstream platform maintainer or maintainer for mtk or qti platforms for TF-A,
I want to bring to your attention about this patch in review - https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/36700
This patch removes erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock” this should not be handled within TF-A. The static setting of PF_MODE in TF-A does not correctly address the erratum and may introduce unnecessary performance degradation on platforms that adopt it without fully understanding its implications.
--
Thanks,
Govindraj R
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[AMD Official Use Only - AMD Internal Distribution Only]
Hi TF-A Team,
With our internal Coverity infrastructure we are seeing multiple MISRA C issues reported (enforced) for transfer-list, while TF-A upstream CI pipeline reports only subset of those violation issues. Could you please share Coverity configuration used in TF-A upstream CI pipeline ?
Regards,
Maheedhar.
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Hi,
I have a question regarding the TBBR implementation for non-volatile counters in TF-A.
While looking through the code and documentation for Trusted Boot authentication options, it was not clear why there are only two non-volatile counters for the Trusted and Non-Trusted worlds (`TRUSTED_FW_NVCOUNTER` and `NON_TRUSTED_FW_NVCOUNTER`). This is true for the Arm DEN0006D specification, but it was retired and ARM DEN0072 is the current specification. Is there any specific reason why there isn't a counter for each authenticated image declared and created by `cert_create` or is the retired specification the only reason? This limits the non-volatile counter extensions for all certificates, meaning that the Trusted OS content certificate for example cannot be authenticated with another extension, unless I add a custom certificate with another non-volatile counter extension and a new command line option.
To quote the ARM DEN0072 TBBR specification [source: https://developer.arm.com/documentation/den0072/latest]: "It is recommended to implement as many version counters as there are images, where each image can use a separate counter without affecting other images. However, the number of rollback counters that can practically be supported is implementation dependent.".
Thank you!
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Hi
I tried to turn on encryption in BL31.
And, I met some trouble.
Here is my code.
```
static struct plat_io_policy policies[] = {
...
[BL31_IMAGE_ID] = {&enc_dev_handle, &bl31_uuid_spec, check_enc_fip},
....
[ENC_IMAGE_ID] = {&fip_dev_handle, NULL, check_fip}
}
int plat_get_image_source(...) {
...
policy = &policies[image_id];
ret = policy->check[policy->image_spec];
...
}
static int check_fip(const uintptr_t spec)
{
int ret;
ret = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle);
if (ret) {
ERROR("io_dev_open failed for FIP (%d)\n", ret);
return ret;
}
ret = io_dev_init(fip_dev_handle, fip_image_id);
if (ret) {
ERROR("io_dev_init failed for FIP image id %lu (%d)\n",
fip_image_id, ret);
io_dev_close(fip_dev_handle);
}
return ret;
}
static int check_enc_fip(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
/* See if a Firmware Image Package is available */
result = io_dev_open(enc_dev_con, (uintptr_t)NULL, &enc_dev_handle);
if (result) {
ERROR("io_dev_open failed for FIP (%d)\n", result);
return result;
}
result = io_dev_init(enc_dev_handle, (uintptr_t)ENC_IMAGE_ID);
if (result != 0)
return result;
return result;
}
```
But, I can't boot successfully.
Below is log.
```
INFO: Image id=3 loaded: 0x40800000 - 0x4080e299
INFO: BL2: Loading image id 5
WARNING: ===== allocate_dev_info 1 =====
WARNING: ==== -12 ====
ERROR: io_dev_open failed for FIP (-12)
ERROR: Image id 11 open failed with -12
WARNING: Failed to obtain reference to image id=11 (-12)
ERROR: BL2: Failed to load image id 5 (-12)
```
And, I found root cause in `allocate_dev_info` and `free_dev_info` in
`drivers/io/io_fip.c`
In `allocate_dev_info`, there is a count, `fip_dev_count`, increasing by 1
after calling `fip_dev_open`
There is a check. The value of MAX_FIP_DEVICES is 1.
```
if (fip_dev_count < (unsigned int)MAX_FIP_DEVICES) {
unsigned int index = 0;
result = find_first_fip_state(0, &index);
assert(result == 0);
/* initialize dev_info */
dev_info_pool[index].funcs = &fip_dev_funcs;
dev_info_pool[index].info =
(uintptr_t)&state_pool[index];
*dev_info = &dev_info_pool[index];
++fip_dev_count;
}
```
And, in `fip_dev_close`, The `fip_dev_count` will be decreased by 1.
However, The root casue is it call fip_dev_open but not calling
fip_dev_close.
It cause the `fip_dev_count` not be decreased by 1.
Now, I have two solution.
1. Increasing the MAX_FIP_DEVICES, it will be working.
2. Add the io_dev_close in `enc_dev_close` in `driver/io_/io_encrypted.c`.
And, it will call the fip_dev_close. It will be working.
Do you have any idea in this solution ?
Which solution is more general ?
Thanks !
Hi, On Jan 23rd 2025, in the TF-A Tech forum, Mate Toth-Pal and Soby Mathew
will present the RMM design of EL0 applications support. The TF-A Tech
forum is a regular open forum for anyone from the open source community to
participate. Feel free to reach if you have a topic you'd want to present.
It can be a design review with slides, walking through RFC patches, or more
generic discussion around open source projects. Regards, Olivier.
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Hi,
On AMD-Xilinx ZynqMP platform there is a erratum (1530924) which is mentioned as applied as shown in the log below:
" INFO: BL31: cortex_a53: CPU workaround for erratum 1530924 was applied "
Refer to the code comments mentioned below, there is no "erratum has no workaround in the CPU. Generic code must take care "
https://gitenterprise.xilinx.com/Linux/arm-trusted-firmware/blob/master/lib…
However, we found no handling in the generic code either.
Can we be guided further regarding the handling of erratum 1530924 ?
Regards,
Maheedhar.