This event has been canceled with a note:
"Hi, Cancelling today as no topic. Regards, Olivier."
TF-A Tech Forum
Thursday Aug 22, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
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Dear TF-A team,
I have a query regarding the TF-A test. Specifically, I would like to know if there is a method to find out the code coverage for a specific test or for all the tests in current run?
Your direction in this regard will be really appreciated.
Thank you,
Senthil
In my opinion, Arm TF-A (EL3) has higher privileges than Linux Kernel
(EL1), and Secure World should be able to access all memory address in
Normal World. To verify this feature, I added a new SMC call in Arm TF-A
and wrote a kernel module to test it (on a Hikey960 Development Board).
But the program does not run as expected that Arm TF-A stucked while
accessing the memory address passed by Linux Kernel.
Here is my kernel module, which uses `alloc_pages` to acquire a physical
address, and uses `page_address` converting it to a virtual address. And
the module passes the physical address and the virtual address to Arm
TF-A using `smc #0`:
```cpp
static int __init smc_testing_init(void) {
uintptr_t phys_addr, virt_addr;
pr_info("Mmodule loaded\n");
phys_addr = (uintptr_t) alloc_pages(GFP_KERNEL, 2);
virt_addr = (uintptr_t) page_address((struct page *) phys_addr);
memset((void *) virt_addr, 'A', PAGE_SIZE << 2);
printk("phys_addr: 0x%llx, virt_addr: 0x%llx\n", (uint64_t)
phys_addr, (uint64_t) virt_addr);
asm volatile(
"ldr x0, =0xC8000003\n"
"mov x1, %0\n"
"mov x2, %1\n"
"smc #0\n"
:
: "r" (phys_addr), "r" (virt_addr)
: "x0", "x1", "x2"
);
__free_pages((struct page *) phys_addr, 2);
return 0;
}
static void __exit smc_testing_exit(void) {
pr_info("Module unloaded\n");
}
```
And here is the handler's code in Arm TF-A, which prints the addresses
of physical address and virtual address, and access the first element of
the memory address:
```cpp
if (0xC8000003 == smc_fid) {
uintptr_t virt_addr = x3;
NOTICE("phys_addr: 0x%lx, virt_addr: 0x%lx\n", phys_addr, virt_addr);
NOTICE("virt_addr[0] = 0x%x\n", *((uint32_t *)virt_addr));
NOTICE("phys_addr[0] = 0x%x\n", *((uint32_t *)phys_addr));
SMC_RET0(handle);
}
```
Here is the output, Arm TF-A handles the request successfully, but
failed to access the memory address passed by Linux Kernel:
```bash
# insmod ./smc_testing.ko
[ 75.259590] smc_testing: loading out-of-tree module taints kernel.
[ 75.266682] Mmodule loaded
[ 75.269404] phys_addr: 0xfffffc0002dc5e00, virt_addr: 0xffff0000b7178000
NOTICE: phys_addr: 0xfffffc0002dc5e00, virt_addr: 0xffff0000b7178000
[ 96.276605] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
[ 96.282741] rcu: 4-...0: (1 ticks this GP)
idle=72ec/1/0x4000000000000000 softirq=204/204 fqs=2592
[ 96.291835] (detected by 0, t=5253 jiffies, g=-643, q=16 ncpus=8)
[ 96.298044] Task dump for CPU 4:
[ 96.301287] task:insmod state:R running task stack:0
pid:201 ppid:185 flags:0x00000006
[ 96.311254] Call trace:
[ 96.313713] __switch_to+0xe4/0x160
[ 96.317241] printk_rb_static+0x30/0x58
```
This event has been canceled with a note:
"No topics scheduled this week so cancelling. Also a lot of people seem to
be away on vacations."
TF-A Tech Forum
Thursday Aug 8, 2024 ⋅ 4pm – 5pm
United Kingdom Time
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
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Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
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HI Andy,
Thank you for explaining,
psa-arch-test(psa certified api compliance) testsuite currently used with TFM +MbedTLS environment as a release gate, and there is trusted service team whom were running the psa-arch-test package on arm-A class devices.
Coming back to the question related to psa-arch-test, the current available package should suffice to check the compliance of crypto necessary tasks/functinoality, fyi we have already validated the latest psa-arch-test repo with the mbedtls 3.6.
So I would not be more concern about the psa-arch-test being compliant to latest 1.2.1 spec. because between 1.1.0 and 1.2.1 there were minimal changes which is not showstopper for the psa certified api certification.
Regards,
JK
From: Andy Chen <andychen(a)pufsecurity.com>
Date: Thursday, 25 July 2024 at 5:30 AM
To: Jothikumar Mani <Jothikumar.Mani(a)arm.com>, Manish Badarkhe <Manish.Badarkhe(a)arm.com>, tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org>
Cc: Diya Soubra <Diya.Soubra(a)arm.com>, Victoria Lee <victorialee(a)pufsecurity.com>, Andrew <andrewirvin(a)pufsecurity.com>
Subject: 回覆: Integrate TF-A and PSA Crypto API with PUFcc
Hi Jothikumar and Manish,
It's great to discuss with you and thanks.
Sure, it's more clarity with usage scenarios:
1. As a Security IP provider, our PUFcc functions as a Hardware Root of Trust.
However, mbedTLS currently doesn't fully support HRoT. Therefore, we are integrating directly into the PSA Crypto API, which permits customization.
1. While working on PSA L3 or L2R, we frequently face version conflicts. That why, in this project, we aim to confirm these version issues (including the dev. and test bench).
1. This also means that both TF-A and TF-M support PSA Crypto API, so we can also support both through this package.
There is our PSA Software Package with PUFcc. We try to find the best way to support cryptographic tasks.
Additionally, we plan to use the same development platform as ARM to ensure optimal compatibility for our customers.
It means we would try to know the FPV, although I'm not sure if we can add external IPs.
If I misunderstood or you have any ideas, please feel free to tell me.
[cid:ed0bb76e-fb77-4502-ae5d-f8443d6b4fc4]
Have a Nice Day,
Andy
________________________________
寄件者: Jothikumar Mani <Jothikumar.Mani(a)arm.com>
寄件日期: 2024年7月24日 下午 11:48
收件者: Andy Chen <andychen(a)pufsecurity.com>; Manish Badarkhe <Manish.Badarkhe(a)arm.com>; tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org>
副本: Diya Soubra <Diya.Soubra(a)arm.com>; Victoria Lee <victorialee(a)pufsecurity.com>; Andrew <andrewirvin(a)pufsecurity.com>
主旨: RE: Integrate TF-A and PSA Crypto API with PUFcc
Hi Andy,
Please find my reply in the previous mail.
Regards,
JK
From: Andy Chen <andychen(a)pufsecurity.com>
Sent: Wednesday, July 24, 2024 8:11 PM
To: Manish Badarkhe <Manish.Badarkhe(a)arm.com>; Jothikumar Mani <Jothikumar.Mani(a)arm.com>; tf-a(a)lists.trustedfirmware.org
Cc: Diya Soubra <Diya.Soubra(a)arm.com>; Victoria Lee <victorialee(a)pufsecurity.com>; Andrew <andrewirvin(a)pufsecurity.com>
Subject: 回覆: Integrate TF-A and PSA Crypto API with PUFcc
Hi Manish,
Thanks for your information.
We need to integrate our hardware Crypto IP (PUFcc). And it seems that FVP cannot add custom IP, so we are planning to purchase an FPGA with the A53 - AXU9EGB<https://www.xilinx.com/products/boards-and-kits/1-1ervp7b.html> for our needs. And we need to make sure it is compatible with TF-A lts-v2.10.5.
Thanks.
Hi Jothikumar,
We would try to integrate with PSA Crypto API, and we need a test bench for v1.2.1.
Please feel free to let me know if you have any suggestions.
[JK] : may I know what the intent is to requesting the crypto v1.2.1 spec compliance suites?, if you are looking for the PSA Certified APIs compliance for your product then the currently available testsuite is more than sufficient. Also, the mbedTLS version mentioned also only supports psa-crypto spec v1.1.0. I am trying to under the end goal of the psa certified api compliance suite usage with your product. Answer to this question will help me to give better suggestion.
For TF-A, we plan to integrate with:
TF-A lts-v2.10.5
PSA Crypto API - v1.1.0 >>> v1.2.1
PSA Certified APIs Architecture Test Suite - v1.6
Thank you very much.
Have a Nice Day,
Andy
________________________________
寄件者: Manish Badarkhe <Manish.Badarkhe(a)arm.com<mailto:Manish.Badarkhe@arm.com>>
寄件日期: 2024年7月24日 下午 06:12
收件者: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>>; Andy Chen <andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com>>; Jothikumar Mani <Jothikumar.Mani(a)arm.com<mailto:Jothikumar.Mani@arm.com>>
副本: Diya Soubra <Diya.Soubra(a)arm.com<mailto:Diya.Soubra@arm.com>>; Victoria Lee <victorialee(a)pufsecurity.com<mailto:victorialee@pufsecurity.com>>; Andrew <andrewirvin(a)pufsecurity.com<mailto:andrewirvin@pufsecurity.com>>
主旨: Re: Integrate TF-A and PSA Crypto API with PUFcc
Hi Andy
Please see my replies inline. Adding Jothikumar Mani for PSA Certified APIs Architecture Test Suite.
Thanks,
Manish Badarkhe
________________________________
From: Andy Chen via TF-A <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>>
Sent: 23 July 2024 09:55
To: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>>
Cc: Diya Soubra <Diya.Soubra(a)arm.com<mailto:Diya.Soubra@arm.com>>; Victoria Lee <victorialee(a)pufsecurity.com<mailto:victorialee@pufsecurity.com>>; Andrew <andrewirvin(a)pufsecurity.com<mailto:andrewirvin@pufsecurity.com>>
Subject: [TF-A] Integrate TF-A and PSA Crypto API with PUFcc
Hi TF-A teams,
This is Andy from PUFsecurity, and we have a project with ARM.
We try to integrate the PSA Crypto API with PUFcc (Our Crypto Engine) on TF-A.
However, there are multiple versions included, and we need your assistance for specification clarification.
Please ensure the versions match your recommendations.
For TF-A, we plan to integrate with:
TF-A lts-v2.10.5
PSA Crypto API - v1.1.0
PSA Certified APIs Architecture Test Suite - v1.6
[MB]: This looks fine. As TF-A lts-v2.10.5 using mbedTLS v3.6.0 which is compliance with PSA Crypto API - v1.1.0 but mbedTLS team can provide more detailed answer on this and also on test suite PSA Certified APIs Architecture Test Suite - v1.6.
TF-A
It would be beneficial to use the same hardware (FPGA) and tools as the ARM development team.
If we can confirm which models are used for TF-A , scripts or details with the ARM hardware That would be grateful.
[MB]: We are using FVP AEM model i.e. FVP_Base_RevC-2xAEMvA (Model version: 11.26, Build: 11). Test Run with PSA Crypto
you can find here: https://ci.trustedfirmware.org/job/tf-a-builder/4029201/ (today's daily run)
PSA Crypto API -
The test bench is using the PSA Crypto API v1.1.0, and it is published in 2022.
And Now is v1.2.1 in March 2024. I not sure it is a good choose or not.
[cid:image001.png@01DADE0E.1BA75330]
[MB]: It looks like arch-test is not upgraded to use v1.2.1 PSA Crypto API. Added Jothikumar Mani, he may have idea about this.
Test Bench -
For the "PSA Certified APIs Architecture Test Suite - v1.6," we would like to identify which test codes (test_c001 to test_c067) are relevant for TF-A.
[MB]: Again, TF-A is not using this test suite, so we don't have any insights unless we review all these tests. TF-A mainly uses the following PSA_* APIs for signature verification, hash calculation, and hash comparison.
psa_crypto_init
mbedtls_md_psa_alg_from_type
psa_set_key_algorithm
psa_set_key_type
psa_set_key_usage_flags
psa_import_key
psa_destroy_key
psa_verify_message
psa_hash_compute
psa_hash_compare
Thank you very much!!!
Have a Nice Day,
Andy
[cid:image002.png@01DADE0E.1BA75330]
熵碼科技股份有限公司
Tel: 886-3-5601010 #2119
Email: andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com>
Website: https://www.pufsecurity.com/
-------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------
-------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------
-------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------
-------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------
Hi Andy,
Please find my reply in the previous mail.
Regards,
JK
From: Andy Chen <andychen(a)pufsecurity.com>
Sent: Wednesday, July 24, 2024 8:11 PM
To: Manish Badarkhe <Manish.Badarkhe(a)arm.com>; Jothikumar Mani <Jothikumar.Mani(a)arm.com>; tf-a(a)lists.trustedfirmware.org
Cc: Diya Soubra <Diya.Soubra(a)arm.com>; Victoria Lee <victorialee(a)pufsecurity.com>; Andrew <andrewirvin(a)pufsecurity.com>
Subject: 回覆: Integrate TF-A and PSA Crypto API with PUFcc
Hi Manish,
Thanks for your information.
We need to integrate our hardware Crypto IP (PUFcc). And it seems that FVP cannot add custom IP, so we are planning to purchase an FPGA with the A53 - AXU9EGB<https://www.xilinx.com/products/boards-and-kits/1-1ervp7b.html> for our needs. And we need to make sure it is compatible with TF-A lts-v2.10.5.
Thanks.
Hi Jothikumar,
We would try to integrate with PSA Crypto API, and we need a test bench for v1.2.1.
Please feel free to let me know if you have any suggestions.
[JK] : may I know what the intent is to requesting the crypto v1.2.1 spec compliance suites?, if you are looking for the PSA Certified APIs compliance for your product then the currently available testsuite is more than sufficient. Also, the mbedTLS version mentioned also only supports psa-crypto spec v1.1.0. I am trying to under the end goal of the psa certified api compliance suite usage with your product. Answer to this question will help me to give better suggestion.
For TF-A, we plan to integrate with:
TF-A lts-v2.10.5
PSA Crypto API - v1.1.0 >>> v1.2.1
PSA Certified APIs Architecture Test Suite - v1.6
Thank you very much.
Have a Nice Day,
Andy
________________________________
寄件者: Manish Badarkhe <Manish.Badarkhe(a)arm.com<mailto:Manish.Badarkhe@arm.com>>
寄件日期: 2024年7月24日 下午 06:12
收件者: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>>; Andy Chen <andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com>>; Jothikumar Mani <Jothikumar.Mani(a)arm.com<mailto:Jothikumar.Mani@arm.com>>
副本: Diya Soubra <Diya.Soubra(a)arm.com<mailto:Diya.Soubra@arm.com>>; Victoria Lee <victorialee(a)pufsecurity.com<mailto:victorialee@pufsecurity.com>>; Andrew <andrewirvin(a)pufsecurity.com<mailto:andrewirvin@pufsecurity.com>>
主旨: Re: Integrate TF-A and PSA Crypto API with PUFcc
Hi Andy
Please see my replies inline. Adding Jothikumar Mani for PSA Certified APIs Architecture Test Suite.
Thanks,
Manish Badarkhe
________________________________
From: Andy Chen via TF-A <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>>
Sent: 23 July 2024 09:55
To: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>>
Cc: Diya Soubra <Diya.Soubra(a)arm.com<mailto:Diya.Soubra@arm.com>>; Victoria Lee <victorialee(a)pufsecurity.com<mailto:victorialee@pufsecurity.com>>; Andrew <andrewirvin(a)pufsecurity.com<mailto:andrewirvin@pufsecurity.com>>
Subject: [TF-A] Integrate TF-A and PSA Crypto API with PUFcc
Hi TF-A teams,
This is Andy from PUFsecurity, and we have a project with ARM.
We try to integrate the PSA Crypto API with PUFcc (Our Crypto Engine) on TF-A.
However, there are multiple versions included, and we need your assistance for specification clarification.
Please ensure the versions match your recommendations.
For TF-A, we plan to integrate with:
TF-A lts-v2.10.5
PSA Crypto API - v1.1.0
PSA Certified APIs Architecture Test Suite - v1.6
[MB]: This looks fine. As TF-A lts-v2.10.5 using mbedTLS v3.6.0 which is compliance with PSA Crypto API - v1.1.0 but mbedTLS team can provide more detailed answer on this and also on test suite PSA Certified APIs Architecture Test Suite - v1.6.
TF-A
It would be beneficial to use the same hardware (FPGA) and tools as the ARM development team.
If we can confirm which models are used for TF-A , scripts or details with the ARM hardware That would be grateful.
[MB]: We are using FVP AEM model i.e. FVP_Base_RevC-2xAEMvA (Model version: 11.26, Build: 11). Test Run with PSA Crypto
you can find here: https://ci.trustedfirmware.org/job/tf-a-builder/4029201/ (today's daily run)
PSA Crypto API -
The test bench is using the PSA Crypto API v1.1.0, and it is published in 2022.
And Now is v1.2.1 in March 2024. I not sure it is a good choose or not.
[cid:image001.png@01DADE0E.1BA75330]
[MB]: It looks like arch-test is not upgraded to use v1.2.1 PSA Crypto API. Added Jothikumar Mani, he may have idea about this.
Test Bench -
For the "PSA Certified APIs Architecture Test Suite - v1.6," we would like to identify which test codes (test_c001 to test_c067) are relevant for TF-A.
[MB]: Again, TF-A is not using this test suite, so we don't have any insights unless we review all these tests. TF-A mainly uses the following PSA_* APIs for signature verification, hash calculation, and hash comparison.
psa_crypto_init
mbedtls_md_psa_alg_from_type
psa_set_key_algorithm
psa_set_key_type
psa_set_key_usage_flags
psa_import_key
psa_destroy_key
psa_verify_message
psa_hash_compute
psa_hash_compare
Thank you very much!!!
Have a Nice Day,
Andy
[cid:image002.png@01DADE0E.1BA75330]
熵碼科技股份有限公司
Tel: 886-3-5601010 #2119
Email: andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com>
Website: https://www.pufsecurity.com/
-------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------
-------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------
-------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------
This event has been updated
Changed: time
TF-A Tech Forum
Every 2 weeks from 9am to 10am on Thursday from Thursday Mar 7 to Wednesday
Jul 24
Mountain Standard Time - Phoenix
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
York)+16699009128,,9159704974# US (San Jose)Dial by your location +1
646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877
853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970
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This event has been updated
TF-A Tech Forum
Every 2 weeks from 8am to 9am on Thursday
Mountain Standard Time - Phoenix
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
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Hi TF-A teams,
This is Andy from PUFsecurity, and we have a project with ARM.
We try to integrate the PSA Crypto API with PUFcc (Our Crypto Engine) on TF-A.
However, there are multiple versions included, and we need your assistance for specification clarification.
Please ensure the versions match your recommendations.
For TF-A, we plan to integrate with:
TF-A lts-v2.10.5
PSA Crypto API - v1.1.0
PSA Certified APIs Architecture Test Suite - v1.6
TF-A
It would be beneficial to use the same hardware (FPGA) and tools as the ARM development team.
If we can confirm which models are used for TF-A , scripts or details with the ARM hardware That would be grateful.
PSA Crypto API -
The test bench is using the PSA Crypto API v1.1.0, and it is published in 2022.
And Now is v1.2.1 in March 2024. I not sure it is a good choose or not.
[cid:0e747007-8c2a-49a7-9447-8d5e7f9a3e9c]
Test Bench -
For the "PSA Certified APIs Architecture Test Suite - v1.6," we would like to identify which test codes (test_c001 to test_c067) are relevant for TF-A.
Thank you very much!!!
Have a Nice Day,
Andy
[cid:74269c28-12d4-48a9-b215-3d3eaf95f2c3]
熵碼科技股份有限公司
Tel: 886-3-5601010 #2119
Email: andychen(a)pufsecurity.com<mailto:andychen@pufsecurity.com>
Website: https://www.pufsecurity.com/
-------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------
-------- Disclaimer: This e-mail is from PUFsecurity Corporation. This e-mail may contain privileged and confidential information. It is intended for the named recipient(s) only. Disclosure, copying, distribution, or use of the contents of this e-mail by persons other than the intended recipient may violate applicable laws. If you are not an intended recipient, please notify us immediately (by reply e-mail) and delete this e-mail from your system. Our postal address is 8F-1, No. 5, Tai-Yuan 1st St., Jhubei City, Hsinchu County 302082, Taiwan.--------
Hi, On Jul 25th in the TF-A Tech Forum: Unification of Chain of Trust
Descriptors - presented by Xialin Liu Currently, the Chain of Trust is
implemented using C data structures built into the firmware or through
device tree nodes. Maintaining both formats can lead to maintenance
challenges. Therefore, we are standardizing the provision of Chain of Trust
descriptors exclusively via the device tree and providing a tool to convert
device tree descriptors into C source files. This approach simplifies the
process, ensuring consistency and reducing the potential for errors
associated with managing multiple formats. Regards, Olivier.
TF-A Tech Forum
Thursday Jul 25, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
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Greetings everyone,
I came across the following paragraph while reading the 'Firmware Partition Filesystem' chapter from EBBR v2.2.0
and I would like to clarify my understanding:
Where possible, firmware images and data should be stored in a filesystem. Firmware can be stored either in a
dedicated firmware partition, or in certain circumstances in the UEFI System Partition (ESP). Using a filesystem
makes it simpler to manage multiple firmware files and makes it possible for a single disk image to contain firmware
for multiple platforms.
Dedicated firmware partitions should be formatted with a FAT filesystem as defined in UEFI § 13.3 File System
Format. Dedicated firmware partitions should use the same /FIRMWARE directory hierarchy. OS tools shall ignore
dedicated firmware partitions, and shall not attempt to use a dedicated firmware partition as an ESP
Questions:
1. Does the above paragraph mean that, if the device allows, all firmware binaries (TF-A, U-Boot, and some others)
must be stored in a dedicated firmware partition formatted with a FAT filesystem and GUID Partition Table (GPT)
disk layout?
2. If so, would this also mean that, where possible, the BootROM or a (first stage) bootloader running before TF-A
should have GPT and FAT support embedded support to load one of the TF-A stages (BL1/BL2)?
Regards,
Ghennadi
Hi,
On AMD-Xilinx ZynqMP platform for ERRATA_NOT_APPLIES case; the log appearing on the console is as below:
"VERBOSE: BL31: cortex_a53: CPU workaround for erratum 819472was not applied".
We checked ZynqMP code and found that the ZynqMP cpu revision was higher than the cpu revision intended in the erratum and hence it was not applicable and not applied.
The message seems inappropriate to us as from log message it is not clear why it wasn't applied.
Our suggestion is that in the log message instead of "not applied" it should be mentioned as "not applicable" as indicated below to reflect the reason properly.
"VERBOSE: BL31: cortex_a53: CPU workaround for erratum 819472 was not applicable".
Regards,
Maheedhar.
Hey all,
i tried to setup a fip.bin and add 3 images (bl31, bl32 and bl33).
./fiptool --verbose create --soc-fw bl31.bin --nt-fw bl33.bin --tos-fw bl32.bin fip.bin
When i check the generated fip.bin with fiptool info it shows me all my three images in the fip.bin
EL3 Runtime Firmware BL31: offset=0xB0, size=0x13644, cmdline="--soc-fw"
Secure Payload BL32 (Trusted OS): offset=0x136F4, size=0x18D864, cmdline="--tos-fw"
Non-Trusted Firmware BL33: offset=0x1A0F58, size=0x9692E, cmdline="--nt-fw"
But during bootup the BL2 finds only the image id =3 and image id=5 which is BL32 and BL33. Why he is not finding the bl32?
Thanks for youre short help.
Regards
Torsten
Hi, This Thursday Jul 11th Kathleen Capella from Arm's TF-A team will
present: **Using the SMC Fuzzing Module in TF-A** This presentation will
show how you might get started with fuzz testing using the SMC fuzzing
module in TF-A. I will demonstrate the basic fuzzer features, how to add
SMC calls/test cases and how to make use of the module's integration with
tf-a-tests and the TF-A CI. Regards, Olivier.
TF-A Tech Forum
Thursday Jul 11, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
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853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970
4974Find your local number: https://zoom.us/u/ad27hc6t7h
Guests
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Hi, On Thursday Jul 18th 2024 Rohit Mathew from Arm's Infra solutions team
will present: ** NUMA-Aware PER-CPU Framework: Enhancing Latency and
Storage Efficiency** With the increasing prevalence of multi-chip
platforms, it is crucial for software written for Trusted Firmware-A to be
NUMA-aware. The PER-CPU framework addresses this need by distributing the
allocation of per-CPU objects across different NUMA nodes. This approach
reduces NUMA latency and balances the allocation load, leading to improved
performance and efficiency. Regards, Olivier.
NUMA-Aware PER-CPU Framework: Enhancing Latency and Storage Efficiency
Thursday Jul 18, 2024 ⋅ 5pm – 5:50pm
Central European Time - Paris
Location
zoom, see dial-in information below
https://www.google.com/maps/search/zoom,+see+dial-in+information+below?hl=en
NUMA-Aware PER-CPU Framework: Enhancing Latency and Storage EfficiencyWith
the increasing prevalence of multi-chip platforms, it is crucial for
software written for Trusted Firmware-A to be NUMA-aware. The PER-CPU
framework addresses this need by distributing the allocation of per-CPU
objects across different NUMA nodes. This approach reduces NUMA latency and
balances the allocation load, leading to improved performance and
efficiency.Dial In Information:Trusted Firmware is inviting you to a
scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/j/9159704974?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09Meeting
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Hi All,
I am trying to compile the latest ATF on Raspberry Pi 5 but it fails.
This is the same for all the other Arm64 architecture I have.
Earlier versions of ATF were able to compile on-board with native gcc.
Well with CROSS_COMPILE it works fine on x86_64 machine.
alarm@raspberrypi:~/Downloads/trusted-firmware-a$ make PLAT=rpi5 DEBUG=1
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 C compiler could
not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 C compiler is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang`
make_helpers/toolchain.mk:344: - LLVM Clang (`clang`)
make_helpers/toolchain.mk:344: - GNU GCC (`gcc`)
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this C
compiler as GNU GCC (`gcc`).
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 C preprocessor
could not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 C preprocessor is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang`
make_helpers/toolchain.mk:344: - LLVM Clang (`clang`)
make_helpers/toolchain.mk:344: - GNU GCC (`gcc`)
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this C
preprocessor as GNU GCC (`gcc`).
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 assembler could
not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 assembler is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang`
make_helpers/toolchain.mk:344: - LLVM Clang (`clang`)
make_helpers/toolchain.mk:344: - GNU GCC (`gcc`)
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this
assembler as GNU GCC (`gcc`).
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 linker could not
be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 linker is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang`
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armlink`
make_helpers/toolchain.mk:344: - LLVM Clang (`clang`)
make_helpers/toolchain.mk:344: - LLVM LLD (`lld`)
make_helpers/toolchain.mk:344: - GNU GCC (`gcc`)
make_helpers/toolchain.mk:344: - GNU LD (`ld.bfd`)
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this linker
as GNU GCC (`gcc`).
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 object copier
could not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-objcopy
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 object copier is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-objcopy
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `fromelf`
make_helpers/toolchain.mk:344: - LLVM `llvm-objcopy`
make_helpers/toolchain.mk:344: - GNU `objcopy`
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this object
copier as GNU `objcopy`.
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 object dumper
could not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-objdump
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 object dumper is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-objdump
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `fromelf`
make_helpers/toolchain.mk:344: - LLVM `llvm-objdump`
make_helpers/toolchain.mk:344: - GNU `objdump`
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this object
dumper as GNU `objdump`.
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 archiver could
not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc-ar
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 archiver is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc-ar
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armar`
make_helpers/toolchain.mk:344: - LLVM `llvm-ar`
make_helpers/toolchain.mk:344: - GNU `ar`
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this
archiver as GNU `ar`.
make_helpers/toolchain.mk:344:
/bin/sh: 1: aarch64-none-elf-gcc: not found
/bin/sh: 1: aarch64-none-elf-gcc: not found
CC bl31/bl31_context_mgmt.c
make: aarch64-none-elf-gcc: No such file or directory
make: *** [Makefile:1514:
/home/alarm/Downloads/trusted-firmware-a/build/rpi5/debug/bl31/bl31_context_mgmt.o]
Error 127
alarm@raspberrypi:~/Downloads/trusted-firmware-a$
alarm@raspberrypi:~/Downloads/trusted-firmware-a$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/aarch64-linux-gnu/12/lto-wrapper
Target: aarch64-linux-gnu
Configured with: ../src/configure -v --with-pkgversion='Debian
12.2.0-14' --with-bugurl=file:///usr/share/doc/gcc-12/README.Bugs
--enable-languages=c,ada,c++,go,d,fortran,objc,obj-c++,m2
--prefix=/usr --with-gcc-major-version-only --program-suffix=-12
--program-prefix=aarch64-linux-gnu- --enable-shared
--enable-linker-build-id --libexecdir=/usr/lib
--without-included-gettext --enable-threads=posix --libdir=/usr/lib
--enable-nls --enable-clocale=gnu --enable-libstdcxx-debug
--enable-libstdcxx-time=yes --with-default-libstdcxx-abi=new
--enable-gnu-unique-object --disable-libquadmath
--disable-libquadmath-support --enable-plugin --enable-default-pie
--with-system-zlib --enable-libphobos-checking=release
--with-target-system-zlib=auto --enable-objc-gc=auto
--enable-multiarch --enable-fix-cortex-a53-843419 --disable-werror
--enable-checking=release --build=aarch64-linux-gnu
--host=aarch64-linux-gnu --target=aarch64-linux-gnu
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 12.2.0 (Debian 12.2.0-14)
Thanks
-Anand
Hi Feifan Qian,
Trapping GPF to EL3 is permitted by the architecture, however I don't believe TF-A provides such option.
In general for TF-A's reference software stacks, a GPF is trapped first at EL2 (hence SCR_EL3.GPF=0).
E.g.
In a system implementing RME, the RMM (@ R-EL2) traps a GPF occurring in an R-EL1/0 Realm (or R-EL2 itself).
Similarly, in the secure world, the SPM (@ S-EL2) traps a GPF occurring in a S-EL1/0 secure partition (or S-EL2 itself).
Regards,
Olivier.
________________________________
From: 钱非凡 <qianfeifan(a)iie.ac.cn>
Sent: 01 July 2024 08:52
To: tf-a-owner(a)lists.trustedfirmware.org <tf-a-owner(a)lists.trustedfirmware.org>
Subject: Questions about the Fault Handling of GPFs
Dear experts,
I have been learning the Fault Handling of the Granule Protection
Fault in Arm CCA. Upon studying the Arm Document, I discovered that the
GPF bit in the SCR_EL3 register controls whether the fault handling of
GPFs occurs in EL3 or not. In addition, I noted that
`include/arch/aarch64/arch.h` defines a macro `#define SCR_GPF_BIT
(UL(1) << 48)`, yet I could not find any reference to this macro in the
source code.
I want to know that whether ATF has implemented the fault handling
of GPFs or if this is a feature to be expected in the future. If its
not, how can I implement this. Any guidance or advice you could provide
would be greatly appreciated.
Sincerely,
Feifan Qian
This event has been canceled with a note:
"Hi, Cancelling as no topic planned. Regards, Olivier. "
TF-A Tech Forum
Thursday Jun 27, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
York)+16699009128,,9159704974# US (San Jose)Dial by your location +1
646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877
853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970
4974Find your local number: https://zoom.us/u/ad27hc6t7h
Guests
marek.bykowski(a)gmail.com
okash.khawaja(a)gmail.com
tf-a(a)lists.trustedfirmware.org
~~//~~
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This event has been canceled with a note:
"Hi, Cancelling this instance as no topic proposed. Thanks, Olivier. "
TF-A Tech Forum
Thursday Jun 13, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
York)+16699009128,,9159704974# US (San Jose)Dial by your location +1
646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877
853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970
4974Find your local number: https://zoom.us/u/ad27hc6t7h
Guests
marek.bykowski(a)gmail.com
okash.khawaja(a)gmail.com
tf-a(a)lists.trustedfirmware.org
~~//~~
Invitation from Google Calendar: https://calendar.google.com/calendar/
You are receiving this email because you are an attendee on the event. To
stop receiving future updates for this event, decline this event.
Forwarding this invitation could allow any recipient to send a response to
the organizer, be added to the guest list, invite others regardless of
their own invitation status, or modify your RSVP.
Learn more https://support.google.com/calendar/answer/37135#forwarding
This event has been canceled with a note:
"Hi, Cancelling for this week as no topic proposed. Thanks, Olivier. "
TF-A Tech Forum
Thursday May 30, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
York)+16699009128,,9159704974# US (San Jose)Dial by your location +1
646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877
853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970
4974Find your local number: https://zoom.us/u/ad27hc6t7h
Guests
marek.bykowski(a)gmail.com
okash.khawaja(a)gmail.com
tf-a(a)lists.trustedfirmware.org
~~//~~
Invitation from Google Calendar: https://calendar.google.com/calendar/
You are receiving this email because you are an attendee on the event. To
stop receiving future updates for this event, decline this event.
Forwarding this invitation could allow any recipient to send a response to
the organizer, be added to the guest list, invite others regardless of
their own invitation status, or modify your RSVP.
Learn more https://support.google.com/calendar/answer/37135#forwarding