Hi, This Thursday Jul 11th Kathleen Capella from Arm's TF-A team will
present: **Using the SMC Fuzzing Module in TF-A** This presentation will
show how you might get started with fuzz testing using the SMC fuzzing
module in TF-A. I will demonstrate the basic fuzzer features, how to add
SMC calls/test cases and how to make use of the module's integration with
tf-a-tests and the TF-A CI. Regards, Olivier.
TF-A Tech Forum
Thursday Jul 11, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
York)+16699009128,,9159704974# US (San Jose)Dial by your location +1
646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877
853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970
4974Find your local number: https://zoom.us/u/ad27hc6t7h
Guests
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okash.khawaja(a)gmail.com
tf-a(a)lists.trustedfirmware.org
Hi, On Thursday Jul 18th 2024 Rohit Mathew from Arm's Infra solutions team
will present: ** NUMA-Aware PER-CPU Framework: Enhancing Latency and
Storage Efficiency** With the increasing prevalence of multi-chip
platforms, it is crucial for software written for Trusted Firmware-A to be
NUMA-aware. The PER-CPU framework addresses this need by distributing the
allocation of per-CPU objects across different NUMA nodes. This approach
reduces NUMA latency and balances the allocation load, leading to improved
performance and efficiency. Regards, Olivier.
NUMA-Aware PER-CPU Framework: Enhancing Latency and Storage Efficiency
Thursday Jul 18, 2024 ⋅ 5pm – 5:50pm
Central European Time - Paris
Location
zoom, see dial-in information below
https://www.google.com/maps/search/zoom,+see+dial-in+information+below?hl=en
NUMA-Aware PER-CPU Framework: Enhancing Latency and Storage EfficiencyWith
the increasing prevalence of multi-chip platforms, it is crucial for
software written for Trusted Firmware-A to be NUMA-aware. The PER-CPU
framework addresses this need by distributing the allocation of per-CPU
objects across different NUMA nodes. This approach reduces NUMA latency and
balances the allocation load, leading to improved performance and
efficiency.Dial In Information:Trusted Firmware is inviting you to a
scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/j/9159704974?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09Meeting
ID: 915 970 4974Passcode: Mj6NdM---One tap mobile+13462487799,,9159704974#
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Toll-freeMeeting ID: 915 970 4974Find your local number:
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Hi All,
I am trying to compile the latest ATF on Raspberry Pi 5 but it fails.
This is the same for all the other Arm64 architecture I have.
Earlier versions of ATF were able to compile on-board with native gcc.
Well with CROSS_COMPILE it works fine on x86_64 machine.
alarm@raspberrypi:~/Downloads/trusted-firmware-a$ make PLAT=rpi5 DEBUG=1
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 C compiler could
not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 C compiler is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang`
make_helpers/toolchain.mk:344: - LLVM Clang (`clang`)
make_helpers/toolchain.mk:344: - GNU GCC (`gcc`)
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this C
compiler as GNU GCC (`gcc`).
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 C preprocessor
could not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 C preprocessor is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang`
make_helpers/toolchain.mk:344: - LLVM Clang (`clang`)
make_helpers/toolchain.mk:344: - GNU GCC (`gcc`)
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this C
preprocessor as GNU GCC (`gcc`).
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 assembler could
not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 assembler is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang`
make_helpers/toolchain.mk:344: - LLVM Clang (`clang`)
make_helpers/toolchain.mk:344: - GNU GCC (`gcc`)
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this
assembler as GNU GCC (`gcc`).
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 linker could not
be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 linker is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armclang`
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armlink`
make_helpers/toolchain.mk:344: - LLVM Clang (`clang`)
make_helpers/toolchain.mk:344: - LLVM LLD (`lld`)
make_helpers/toolchain.mk:344: - GNU GCC (`gcc`)
make_helpers/toolchain.mk:344: - GNU LD (`ld.bfd`)
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this linker
as GNU GCC (`gcc`).
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 object copier
could not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-objcopy
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 object copier is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-objcopy
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `fromelf`
make_helpers/toolchain.mk:344: - LLVM `llvm-objcopy`
make_helpers/toolchain.mk:344: - GNU `objcopy`
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this object
copier as GNU `objcopy`.
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 object dumper
could not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-objdump
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 object dumper is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-objdump
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `fromelf`
make_helpers/toolchain.mk:344: - LLVM `llvm-objdump`
make_helpers/toolchain.mk:344: - GNU `objdump`
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this object
dumper as GNU `objdump`.
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The configured AArch64 archiver could
not be identified and may not be supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc-ar
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The default AArch64 archiver is:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: aarch64-none-elf-gcc-ar
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The following tools are supported:
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: - Arm® Compiler for Embedded `armar`
make_helpers/toolchain.mk:344: - LLVM `llvm-ar`
make_helpers/toolchain.mk:344: - GNU `ar`
make_helpers/toolchain.mk:344:
make_helpers/toolchain.mk:344: The build system will treat this
archiver as GNU `ar`.
make_helpers/toolchain.mk:344:
/bin/sh: 1: aarch64-none-elf-gcc: not found
/bin/sh: 1: aarch64-none-elf-gcc: not found
CC bl31/bl31_context_mgmt.c
make: aarch64-none-elf-gcc: No such file or directory
make: *** [Makefile:1514:
/home/alarm/Downloads/trusted-firmware-a/build/rpi5/debug/bl31/bl31_context_mgmt.o]
Error 127
alarm@raspberrypi:~/Downloads/trusted-firmware-a$
alarm@raspberrypi:~/Downloads/trusted-firmware-a$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/aarch64-linux-gnu/12/lto-wrapper
Target: aarch64-linux-gnu
Configured with: ../src/configure -v --with-pkgversion='Debian
12.2.0-14' --with-bugurl=file:///usr/share/doc/gcc-12/README.Bugs
--enable-languages=c,ada,c++,go,d,fortran,objc,obj-c++,m2
--prefix=/usr --with-gcc-major-version-only --program-suffix=-12
--program-prefix=aarch64-linux-gnu- --enable-shared
--enable-linker-build-id --libexecdir=/usr/lib
--without-included-gettext --enable-threads=posix --libdir=/usr/lib
--enable-nls --enable-clocale=gnu --enable-libstdcxx-debug
--enable-libstdcxx-time=yes --with-default-libstdcxx-abi=new
--enable-gnu-unique-object --disable-libquadmath
--disable-libquadmath-support --enable-plugin --enable-default-pie
--with-system-zlib --enable-libphobos-checking=release
--with-target-system-zlib=auto --enable-objc-gc=auto
--enable-multiarch --enable-fix-cortex-a53-843419 --disable-werror
--enable-checking=release --build=aarch64-linux-gnu
--host=aarch64-linux-gnu --target=aarch64-linux-gnu
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 12.2.0 (Debian 12.2.0-14)
Thanks
-Anand
Hi Feifan Qian,
Trapping GPF to EL3 is permitted by the architecture, however I don't believe TF-A provides such option.
In general for TF-A's reference software stacks, a GPF is trapped first at EL2 (hence SCR_EL3.GPF=0).
E.g.
In a system implementing RME, the RMM (@ R-EL2) traps a GPF occurring in an R-EL1/0 Realm (or R-EL2 itself).
Similarly, in the secure world, the SPM (@ S-EL2) traps a GPF occurring in a S-EL1/0 secure partition (or S-EL2 itself).
Regards,
Olivier.
________________________________
From: 钱非凡 <qianfeifan(a)iie.ac.cn>
Sent: 01 July 2024 08:52
To: tf-a-owner(a)lists.trustedfirmware.org <tf-a-owner(a)lists.trustedfirmware.org>
Subject: Questions about the Fault Handling of GPFs
Dear experts,
I have been learning the Fault Handling of the Granule Protection
Fault in Arm CCA. Upon studying the Arm Document, I discovered that the
GPF bit in the SCR_EL3 register controls whether the fault handling of
GPFs occurs in EL3 or not. In addition, I noted that
`include/arch/aarch64/arch.h` defines a macro `#define SCR_GPF_BIT
(UL(1) << 48)`, yet I could not find any reference to this macro in the
source code.
I want to know that whether ATF has implemented the fault handling
of GPFs or if this is a feature to be expected in the future. If its
not, how can I implement this. Any guidance or advice you could provide
would be greatly appreciated.
Sincerely,
Feifan Qian
This event has been canceled with a note:
"Hi, Cancelling as no topic planned. Regards, Olivier. "
TF-A Tech Forum
Thursday Jun 27, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
York)+16699009128,,9159704974# US (San Jose)Dial by your location +1
646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877
853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970
4974Find your local number: https://zoom.us/u/ad27hc6t7h
Guests
marek.bykowski(a)gmail.com
okash.khawaja(a)gmail.com
tf-a(a)lists.trustedfirmware.org
~~//~~
Invitation from Google Calendar: https://calendar.google.com/calendar/
You are receiving this email because you are an attendee on the event. To
stop receiving future updates for this event, decline this event.
Forwarding this invitation could allow any recipient to send a response to
the organizer, be added to the guest list, invite others regardless of
their own invitation status, or modify your RSVP.
Learn more https://support.google.com/calendar/answer/37135#forwarding
This event has been canceled with a note:
"Hi, Cancelling this instance as no topic proposed. Thanks, Olivier. "
TF-A Tech Forum
Thursday Jun 13, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
York)+16699009128,,9159704974# US (San Jose)Dial by your location +1
646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877
853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970
4974Find your local number: https://zoom.us/u/ad27hc6t7h
Guests
marek.bykowski(a)gmail.com
okash.khawaja(a)gmail.com
tf-a(a)lists.trustedfirmware.org
~~//~~
Invitation from Google Calendar: https://calendar.google.com/calendar/
You are receiving this email because you are an attendee on the event. To
stop receiving future updates for this event, decline this event.
Forwarding this invitation could allow any recipient to send a response to
the organizer, be added to the guest list, invite others regardless of
their own invitation status, or modify your RSVP.
Learn more https://support.google.com/calendar/answer/37135#forwarding
This event has been canceled with a note:
"Hi, Cancelling for this week as no topic proposed. Thanks, Olivier. "
TF-A Tech Forum
Thursday May 30, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
Invites are via the TF-A mailing list and also published on the Trusted
Firmware website. Details are here:
https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09
One tap mobile+16465588656,,9159704974# US (New
York)+16699009128,,9159704974# US (San Jose)Dial by your location +1
646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877
853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970
4974Find your local number: https://zoom.us/u/ad27hc6t7h
Guests
marek.bykowski(a)gmail.com
okash.khawaja(a)gmail.com
tf-a(a)lists.trustedfirmware.org
~~//~~
Invitation from Google Calendar: https://calendar.google.com/calendar/
You are receiving this email because you are an attendee on the event. To
stop receiving future updates for this event, decline this event.
Forwarding this invitation could allow any recipient to send a response to
the organizer, be added to the guest list, invite others regardless of
their own invitation status, or modify your RSVP.
Learn more https://support.google.com/calendar/answer/37135#forwarding
Hi All,
We are pleased to announce the formal release of Trusted Firmware-A version 2.10 bundle of project deliverables.
This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium, RMM and TF-A OpenCI Scripts/Jobs 2.10 releases involving the tagging of multiple repositories.
These went live on 22nd November 2023.
Please find references to tags and change logs at the end of this email.
Many thanks to the community for the active engagement in delivering this release!
Notable Features of the Version 2.10 Release are as follows:
TF-A/EL3 Root World
* New Features:
* Firmware handoff library support
* Improvements to BL31 runtime exception handling
* Context management refactoring for RME/4 worlds
* Gelas, Nevis & Travis CPUs support
* V8.9 features enabled (FEAT_ HAFT, RPRFM, LRCPC3, MTE_PERM)
TF-A Boot BL1/BL2
* New Features
* Trusted Boot support for ECDSA (Elliptic Curve Digital Signature Algorithm)
* Migrated to PSA crypto API’s
* Improved the GUID Partition Table (GPT) parser.
* Various security Improvements and threat Model updates for ARM CCA
* Signer id extraction Implementation
Hafnium/SEL2 SPM
* New Features:
* FF-A v1.2: FFA_YIELD with time-out; EL3 SPMDs LSPs communication; memory sharing updates.
* Memory region relative base address field support in SP manifests.
* Interrupt re-configuration hypervisor calls.
* Memory management: S2 PT NS/S IPA split
* SMCCCv1.2+ compliance fixes.
* Feature parity test improvements, EL3 SPMC and Hafnium (S-EL2 SPMC)
TF-RMM/REL2
* New Feature/Support
* Fenimore v1.0 EAC5 aligned implementation.
* TFTF Enhancements for RME testing
* Initial CBMC support
* NS SME support in RMM
* BTI support for RMM
Errata
* Errata implemented (1xCortex-X2/ Matterhorn-ELP, 1xCortex-A710/Matterhorn, 1xNeoverse N2/Perseus, 2xNeoverse V2/Demeter, Makalu ELP/Cortex X3, Klein/Cortex-A510)
* Fix some minor defects with version in a few errata that applies for some follow up revisions of the CPUs. (Neoverse V1, Cortex-X2, Cortex-A710)
TF-A Tests
* Core
* Added errata management firmware interface tests.
* Added firmware handoff tests.
* Introduced RAS KFH support test.
* SPM/FF-A
* Support SMCCCv1.2 extended GP registers set.
* Test SMCCC compliance at the non-secure physical instance.
* Test secure eSPI interrupt handling.
* Test FF-A v1.2 FFA_PARTITION_INFO_GET_REGS interface.
* RMM
* Added FPU/SVE/SME tests
* Added multiple REC single CPU tests.
* Added PAuth support in Realms tests.
* Added PMU tests.
Platform Support
* New platforms added:
* Aspeed AST2700, NXP IMX93, Intel Agilex5, Nuvoton NPCM845x, QTI MDM9607, MSM8909, MSM8939, ST STM32MP2
Release tags across repositories:
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tag/?h=v2.10https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tag/?h=v2.10https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tag/?h=v2.10https://git.trustedfirmware.org/ci/tf-a-job-configs.git/tag/?h=v2.10https://git.trustedfirmware.org/hafnium/hafnium.git/tag/?h=v2.10https://git.trustedfirmware.org/ci/hafnium-ci-scripts.git/tag/?h=v2.10https://git.trustedfirmware.org/ci/hafnium-job-configs.git/tag/?h=v2.10https://git.trustedfirmware.org/TF-RMM/tf-rmm.git/tag/?h=tf-rmm-v0.4.0
Change logs:
https://trustedfirmware-a.readthedocs.io/en/v2.10/change-log.html#id1https://trustedfirmware-a-tests.readthedocs.io/en/v2.10/change-log.html#ver…https://hafnium.readthedocs.io/en/latest/change-log.html#v2-10https://tf-rmm.readthedocs.io/en/tf-rmm-v0.4.0/about/change-log.html#v0-4-0
Regards,
Olivier.
Hi ,
We are trying to build the TF-A code using clang compiler .
Instructions are followed as per the conf page https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/initial-…
1. export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
2. make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
in our side , make CC=/tools/installs/arm/safety/armcc/6.6.2/bin/armclang PLAT=zynqmp distclean
3.
with steps 1) and 2) , we observe the value of AS and AR getting set as below:
AS = /tools/installs/arm/safety/armcc/6.6.2/bin/armclang -c -x assembler-with-cpp -target aarch64-arm-none-eabi -march=armv8-a
AR = <path-to-aarch64-gcc>/bin/aarch64-linux-gnu-ar
4.
However in /tools/installs/arm/safety/armcc/6.6.2/bin , clang tool specific AS points to armasm and AR points to armar utility.
5.
From above output in point 4 , we can see that AS and AR does not refer to clang toolchain utilities armasm and armar.
From point 3) , AS still points to armclang utility only instead of armasm , while AR still points to aarch64-linux-gnu-ar instead of armar .
6.
Can we be guided if the above outputs are correct to use wrt TF-A code build using clang compiler ?
And whether any modifications can be done to point AS and AR to clang toolchain specific utilities as mentioned in step 4.
Regards
Amit
Hi,
We do not have active maintainer for Marvell platform.
As per docs/about/maintainers.rst the current maintainer is "Konstantin Porotchkin <kostap(a)marvell.com>".
Is anybody willing to take ownership of the platform, preferably people who have contributed to this platform in past.
Thanks
Manish
Clock and power management in ATF, preemption issue.
I have seen that multiple Vendors are using arm scmi protocol to do clock management in bl31[0][1].
The problem with such implementations is any long running SCMI operations (like PLL locking for example)
will hold the core in EL3 for extended period of time, adding to latency of NS EL1 interrupt handling
as ATF is not preemptible.
This problem can be solved by making ATF preemptible, similar to how OP-TEE does it by
by implementing a remote procedural call after it receives a interrupt.
[2]How Linux does SMC call with YIELD flag enabled.
[3]How OP-TEE handles the timer interrupt
[4]How Linux receives an interrupt which came in EL3->SEL1
As quoted in exception Handling document in ATF docs[5]
"Receive exceptions, but handle part of the exception in EL3, and delegate processing of
the error to dedicated software stack running at lower secure ELs (as above); additionally,
the Normal world may also be required to participate in the handling,
or be notified of such events (for example, as an event).
In this scheme, exception handling potentially and maximally spans all
ELs in both Secure and Normal worlds."
From this we can understand that we can delegate the exception to EL1 if we are already in EL3.
(way to preempt)
We are aware that ARM v8.4-A onwards arch are having a SEL2 level with which we can run a vendor specific firmware
parallel to TEE at SEL1 in a secure partition. But how we do handle clock and power management
for version which doesn't support SEL2?
We don't want to put it in TEE as it will constraint our devices to that
specific TEE.
I am starting to work on a proposal to make ATF preemptible similar to how OP-TEE is doing it.
a)Will the similar approach from OP-TEE if implemented and working be
accepted by ATF upstream?
The SMC call with YIELD option will only be preemtible so will not
affect the normal flow.
b)As quoted in Trusted Firmware-A Document[6] Page 94,
"Yielding calls are reserved exclusively for Trusted OS providers"
"Yielding 0- 1 Reserved for existing Armv7-A calls
Yielding 2-63 Trusted OS Standard Calls"
Can this range be consumed within ATF/bl31 firmware or is it necessary to forward all yielding calls to Trusted OS?
[0]https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/st/…
[1]https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/21840
[2]https://elixir.bootlin.com/linux/v6.9-rc3/source/drivers/tee/optee/smc_ab…
[3]https://github.com/OP-TEE/optee_os/blob/fc57019cb35c8c1bad66fc6d814ace5de…
[4]https://elixir.bootlin.com/linux/v6.9-rc3/source/drivers/tee/optee/smc_ab…
[5]https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/com…
[6]https://trustedfirmware-a.readthedocs.io/_/downloads/en/latest/pdf/
Regards,
Kamlesh
Hi ,
There is a contradiction present in TF-A documentation whether secure interrupts can be handled in EL3 for arm gic v2 case .
1.
Referring https://trustedfirmware-a.readthedocs.io/en/latest/design/interrupt-framewo…
It says secure interrupts can't be handled in EL3 .
Refer statement : "In Arm GICv2, all secure interrupts are assumed to be handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they cannot be handled in EL3."
2.
Referring https://trustedfirmware-a.readthedocs.io/en/latest/components/platform-inte…
It says secure interrupts can be handled in EL3 , When GICV2_G0_FOR_EL3 is 1 .
Refer below statements :
For interrupt type INTR_TYPE_EL3:
When GICV2_G0_FOR_EL3 is 0, it returns false, indicating no support for EL3 interrupts.
When GICV2_G0_FOR_EL3 is 1, it returns true, indicating support for EL3 interrupts.
can this be clarified ?
Regards
Amit
This event has been canceled with a note:
"Hi, Cancelling as no topic proposed this week. Thanks & Regards, Olivier. "
TF-A Tech Forum
Thursday May 16, 2024 ⋅ 5pm – 6pm
Central European Time - Paris
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to colleagues.
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Hi All,
The next release of the Firmware-A bundle of projects tagged v2.10 has an expected code freeze date of Nov, 7th 2023.
Refer to the Release Cadence section from TF-A documentation (https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/docs/about…).
Closing out the release takes around 6-10 working days after the code freeze.
Preparations tasks for v2.10 release should start in coming month.
We want to ensure that planned feature patches for the release are submitted in good time for the review process to conclude. As a kind recommendation and a matter of sharing CI resources, please launch CI jobs with care e.g.:
-For simple platform, docs changes, or one liners, use Allow-CI+1 label (no need for a full Allow-CI+2 run).
-For large patch stacks use Allow-CI+2 at top of the patch stack (and if required few individual Allow+CI+1 in the middle of the patch stack).
-Carefully analyze results and fix the change if required, before launching new jobs on the same change.
-If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not added as a gerrit comment on the patch right away please be patient as under heavy load CI jobs can be queued and in extreme conditions it can be over an hour before the Build start notice is issued. Issuing another Allow-CI+1 or Allow-CI+2 label will just result in an additional job being queued.
Thanks & Regards,
Olivier.
Hi,
Referring https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/getti…
it says : ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault injection from lower Els.
Referring https://github.com/ARM-software/arm-trusted-firmware/blob/master/lib/el3_ru…
FAULT_INJECTION_SUPPORT enables FIEN bit.
#if FAULT_INJECTION_SUPPORT
/* Enable fault injection from lower ELs */
scr_el3 |= SCR_FIEN_BIT;
#endif
Question :
1.
Do we have any relevant documentation from arm which specifies FIEN bit can be enabled from armv8.4 ?
2.
In cortex a-53 technical reference manual, SCR_EL3 does not have FIEN bit , bit 21 is marked reserved .
In cortex a-78 technical reference manual , manual does not have details for SCR_EL3 .
I want to know whether on Armv8.2-a based cores like cortex a-78 , is the FIEN bit field marked reserved in SCR_EL3 register or is available functionality wise as in armv8.4 ?
Please help with above query.
Regards
Amit
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
14 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)
** CID 425813: Memory - corruptions (OVERRUN)
/drivers/arm/css/dsu/dsu.c: 133 in cluster_on_dsu_pmu_context_restore()
________________________________________________________________________________________________________
*** CID 425813: Memory - corruptions (OVERRUN)
/drivers/arm/css/dsu/dsu.c: 133 in cluster_on_dsu_pmu_context_restore()
127 void cluster_on_dsu_pmu_context_restore(void)
128 {
129 unsigned int cluster_pos;
130
131 cluster_pos = (unsigned int) plat_cluster_id_by_mpidr(read_mpidr_el1());
132
>>> CID 425813: Memory - corruptions (OVERRUN)
>>> "&cluster_pmu_context[cluster_pos]" evaluates to an address that is at byte offset 138720 of an array of 544 bytes.
133 restore_dsu_pmu_state(&cluster_pmu_context[cluster_pos]);
** CID 425812: Memory - corruptions (OVERRUN)
/drivers/arm/css/dsu/dsu.c: 81 in cluster_off_dsu_pmu_context_save()
________________________________________________________________________________________________________
*** CID 425812: Memory - corruptions (OVERRUN)
/drivers/arm/css/dsu/dsu.c: 81 in cluster_off_dsu_pmu_context_save()
75 void cluster_off_dsu_pmu_context_save(void)
76 {
77 unsigned int cluster_pos;
78
79 cluster_pos = (unsigned int) plat_cluster_id_by_mpidr(read_mpidr_el1());
80
>>> CID 425812: Memory - corruptions (OVERRUN)
>>> "&cluster_pmu_context[cluster_pos]" evaluates to an address that is at byte offset 138720 of an array of 544 bytes.
81 save_dsu_pmu_state(&cluster_pmu_context[cluster_pos]);
82 }
83
84 /*****************************************************************************
85 * This function, restore_dsu_pmu_state, restores the state of the
86 * Performance Monitoring Unit (PMU) from a previously saved state.
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
8 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 425810: High impact quality (WRITE_CONST_FIELD)
/plat/nxp/s32/s32g274ardb2/plat_console.c: 17 in console_s32g2_register()
________________________________________________________________________________________________________
*** CID 425810: High impact quality (WRITE_CONST_FIELD)
/plat/nxp/s32/s32g274ardb2/plat_console.c: 17 in console_s32g2_register()
11
12 void console_s32g2_register(void)
13 {
14 static console_t s32g2_console;
15 int ret;
16
>>> CID 425810: High impact quality (WRITE_CONST_FIELD)
>>> A write to an aggregate overwrites a const-qualified field within the aggregate.
17 (void)memset(&s32g2_console, 0, sizeof(s32g2_console));
18
19 ret = console_linflex_register(UART_BASE, UART_CLOCK_HZ,
20 UART_BAUDRATE, &s32g2_console);
21 if (ret == 0) {
22 panic();
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…
Hi Everyone,
This Thursday , Shruti from TF-RMM team will discuss the following topics in TF-A Tech Forum :
1. Integration of CPPCheck in TF-RMM
* CPPCheck is an open-source static analyzer with addon MISRA checker. In this talk, we will discuss the CPPCheck integration in TF-RMM build system and demonstrate the same.
2. TF-A-Tests enhancements and testing for TF-RMM
* Discuss new enhancements in TF-A-Tests for Realm Payload tests including Creating, Loading & Running Realm Payload, testing multiple Rec’s and PSCI support for Realms. We will also cover some Test framework conventions and aspects of Stage2 Memory Management, Realm Memory Exception Model testing.
Best Regards
Soby Mathew
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