- TF-A - lists.trustedfirmware.org

On supporting unmaintained platforms and downstream projects

by Julius Werner

Hi Soby et. al., I wanna kick off a little discussion about how TF-A intends to deal with in-tree platform ports as they get older and the interest in maintaining them drops off. Concretely, I noticed that the plat/nvidia/tegra platforms no longer build since the removal of the deprecated console API in https://review.trustedfirmware.org/842 last month. There has been a patch suggestion to fix it uploaded at https://review.trustedfirmware.org/1192 for two months, but it hasn't moved forward because it seems that Arm thinks it's on the platform maintainer (Nvidia) to finish up and test the patch, and they don't seem to be responding. This creates a problem for downstream projects like coreboot and Chrome OS that use Trusted Firmware on Tegra chips and build-test them in their CI systems. My assumption when setting up the Trusted Firmware integration for them was that the Trusted Firmware CI would build test all in-tree platforms for every commit anyway, so we could always assume that all platforms build on the current master... but clearly, that assumption broke in this case. (I guess because you manually overrode the CI in https://review.trustedfirmware.org/842? Or does it not test all platforms anyway?) So now, coreboot is stuck on an old TF-A version and cannot move forward for any platform until we either kick out the Tegra SoCs or get the problem fixed in TF-A (which is a problem with the testing because I don't have a Tegra board on hand either). How do you think we should solve issues like this? Is keeping platforms that don't build in the tree an intended state? Is there some deadline after which you intend to remove the platform completely? Or would it be better to just merge "best effort" commits like https://review.trustedfirmware.org/1192 that we think should do the right thing for the platform (and at least makes it build again), even if nobody is around to test it on real hardware? To give some experience from the coreboot project, I think it's an unfortunate truth that SoC vendors just tend to lose interest in maintaining hardware once it's more than 2-3 years old. At that point the open-source community has to jump in to continue maintenance, and they can only do it on a best effort basis. It's not possible to always find someone with the right hardware and time to test it for all these old platforms whenever you're trying to do some large, project wide API change, so eventually you'll just have to accept patches that haven't been tested for them. Most of the times (if reviewers pay attention) it works well, sometimes they break. If they do, eventually someone will notice and then they'll have to bisect and fix it. I believe Linux is essentially doing the same thing for lesser-used hardware. It's either that, or you have to constantly kick out old platforms after a few years. (From the coreboot point of view, kicking the Tegra platforms out of TF-A would mean we're forced to remove them from coreboot as well, which would be unfortunate.) Let me know what you think! Julius

5 years, 11 months

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Re: [TF-A] On supporting unmaintained platforms and downstream projects

by Joanna Farley

Hi Julius, It’s a valid issue you have raised. In general we rely on the platform maintainer to work with us to keep their platform port fresh and in this case we proposed some changes and was looking for feedback from the maintainer. We try in our internal standups at least once a week to look for patch reviews that have had no work on them for 21 days and if we do identify any we start chasing to progress these. Eventually if after several attempts we cannot get the patch to progress we would generally look to abandon if it’s the patch originator we cannot contact. In this case it was the platform maintainer who we needed a review from and you managed to get Varun to notice the patches. If we had not managed to contact them then we would have had to make a call on if to submit the changes or not to at least get the build working even though we would not be able to test them. I would like to think in the case of a broken build we would take that option rather than abandon. I think this issue is made a little worse in that the CI results are not yet open so not obvious to everybody although hopefully that will be eventually addressed with the proposed Open CI system on trustedfirmware.org where build results will be available. On top of that if partners want to engage in providing a board available that could be integrated into the LAVA farm that’s part of the CI system and would also be tested. Joanna On 03/08/2019, 01:10, "TF-A on behalf of Julius Werner via TF-A" <tf-a-bounces(a)lists.trustedfirmware.org on behalf of tf-a(a)lists.trustedfirmware.org> wrote: > Thanks for the email, Julius. To be clear, we very well intend to be part of the TF-A project. Having said that, I was not aware of the two commits you mentioned in the email and di not know that Tegra builds are broken in the master branch. Thanks. You were CCed on the patch so I assumed you would've seen it. If not, maybe your email address isn't set correctly in your Gerrit account or something? I've already pushed an update to https://review.trustedfirmware.org/1192 which I think should fix the issue for Tegra, but I need someone to test it. Nevertheless, I think it's a good idea to answer these questions in a general case (e.g. whether we can make sure that we won't break the build on master even if there are temporary issues with certain platforms), because it's probably going to become relevant again sooner or later even if the Tegra issue gets fixed now. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

5 years, 11 months

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Advisory TFV 5 to CVE-2017-15031 only saves/stores the PMCR_EL0 across world switching

by Marek Bykowski

Hi David/ATF Support, An excerpt from the commit message to CVE-2017-15031 is "Additionally, PMCR_EL0 is added to the list of registers that are saved and restored during a world switch." My question is why it is only being saved/restored across the world switch and not during a "normal" SMC call? When I do modify the PMCR_EL0 in EL2 or NonSecure-EL1 and run the smc call the PMCCNTR counter counts during the smc call and does expose secure world timing information to NonSecure in that matter. Thanks, Marek

5 years, 11 months

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Raspberry Pi 4 ATF port

by Andre Przywara

Hi, (BCC:ing Antonio as well) not sure if someone gets notified, but I pushed a patch set to add Raspberry Pi 4 support to Trusted Firmware: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1629 This port is quite a departure from the existing RPi3 port, that's why I wanted to start a discussion about it here. I originally started by copying files. But for the sake of simplicity, also to get away without a BL33 loader, it turned into just a BL31-only port (for now?). This ties more into the existing RPi Foundation boot style, as the resulting bl31.bin is a drop-in replacement for the existing armstub8.bin. So you put your AArch64 kernel into kernel8.img and copy bl31.bin to armstub8.bin (or use the respective config.txt options to point to any other filename), and it should work (TM). The code will pick up the actual kernel and DTB load address from the GPU firmware, patch the DT to use PSCI instead of spin tables, then will drop into EL2 at the kernel load address. There could (should?) be U-Boot or EDK-II there as well, or any other kernel, for that matter. The only thing Linux specific we do is to put the DTB address into x0. I guess this doesn't hurt, even if the BL33 payload does not use this information. I would be grateful to hear some opinions about this approach. Does that sound sensible? Is the split of the platform directory (plat/rpi3 -> plat/rpi/rpi[34]) reasonable? Shall we add this design as a build option to RPi3 as well? Shall we add the "full featured" RPi3 design to RPi4 also? Looking forward to any feedback! Cheers, Andre.

5 years, 11 months

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Re: [TF-A] Defects detected by Coverity Scan Online

by Sandrine Bailleux

Hi, On 7/3/19 11:15 AM, Sandrine Bailleux via TF-A wrote: > We would need help from the TF-A community for analyzing and fixing > them, especially those in platform ports and drivers. Note that there > might be false positives, in which case we would just triage them as > such in the tool's database. > > Hopefully everyone should be able to view the defects, according to the > tool's settings. You might need to create an account on > https://scan.coverity.com for that. We've received a couple of requests from users to get access to the TF-A defects database in the Coverity Scan Online service. I think it's worth clarifying the different levels of access the tool offers and how we envisage the defects triaging. In Coverity Scan Online, users can have any of the following 4 roles (in ascending order of permissions): - Observer/User: Only sees defects summary. - Defect Viewer. - Contributor/Member: Can also triage defects. - Maintainer/Owner: Also has some admin powers, like managing users and submitting builds to be analyzed. Right now, all users should be able to see the project summary and view the defects in read-only mode so this is equivalent to the "Defect viewer" role. I suspect people still need to create an account in Coverity Scan Online and be logged in to see the data. We would expect subsystems and platforms maintainers (i.e. people listed in docs/maintainers.rst [1]) to manage the defects in the part of the codebase they own, as they know best how to assess the severity of these defects and how to fix or triage them. As such, they need to have the "contributor/member" role in the tool. If you are such a maintainer, please feel free to create an account and request this role. If you would like to delegate part/all of the triaging process to a peer, that is also possible. In this case, could you please send me an email to indicate who you have chosen for this task? This is just to make sure that whoever requests the "contributor/member" role has done so with the relevant maintainer's approval. Please be aware that those with "contributor/member" role will be able to triage any defects in any part of the codebase, and not just in the subsystem/platform they maintain. "Maintainer/Owner" role will be reserved to the main maintainers (i.e. people listed at the top of docs/maintainers.rst) for now. Best regards, Sandrine [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/docs/maint…

5 years, 12 months

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Re: [TF-A] How can I check detail error of CI failure?

by Sandrine Bailleux

Hi Jun, On 7/16/19 11:30 AM, John Tsichritzis via TF-A wrote: > Thank you for your email. Unfortunately detailed information is not available in Gerrit since CI is hosted internally. The maintainers post detailed information of the errors in case there is something that needs fixing. In this case I will post the error details in the Gerrit review itself. > > When a patch stack is submitted, usually we launch the tests on the topmost patch on the stack. In this case the entire branch gets tested, not a single commit. In other words, the testing doesn't do any "cherry-picking" on the patches, so even if there are dependencies between the patches this doesn't affect the test. That's why we usually launch the tests on the topmost patch. To add on top of what John said, I would like to mention that we are working with Linaro to have the CI loop opened up to all contributors in the future. When this day comes, you will be able to check the error log by yourself. In the meantime, I'm afraid you'll have to rely on Arm maintainers to give you the details, as John said. If they forget, please feel free to ping them in Gerrit (like you've already done for this patch). Best regards, Sandrine

5 years, 12 months

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Re: [TF-A] How can I check detail error of CI failure?

by John Tsichritzis

Dear Jun, Thank you for your email. Unfortunately detailed information is not available in Gerrit since CI is hosted internally. The maintainers post detailed information of the errors in case there is something that needs fixing. In this case I will post the error details in the Gerrit review itself. When a patch stack is submitted, usually we launch the tests on the topmost patch on the stack. In this case the entire branch gets tested, not a single commit. In other words, the testing doesn't do any "cherry-picking" on the patches, so even if there are dependencies between the patches this doesn't affect the test. That's why we usually launch the tests on the topmost patch. Kind regards, John -- John Tsichritzis | Graduate Software Engineer Email: john.tsichritzis(a)arm.com<mailto:john.tsichritzis@arm.com> 110 Fulbourn Road, Cambridge, CB1 9NJ, United Kingdom https://www.arm.com/ On 16/07/2019 09.24, Jun Nie via TF-A wrote: Hi, I see below failure in this link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1367 How can I check the error log? I am not sure it is due to lack of earlier patch in patch set or something. Because local build is OK. Patch Set 4: Verified-1 Build Failed https://jenkins.oss.arm.com/job/tf-gerrit-tforg-l1/221/ : FAILURE Jun

5 years, 12 months

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How can I check detail error of CI failure?

by Jun Nie

Hi, I see below failure in this link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1367 How can I check the error log? I am not sure it is due to lack of earlier patch in patch set or something. Because local build is OK. Patch Set 4: Verified-1 Build Failed https://jenkins.oss.arm.com/job/tf-gerrit-tforg-l1/221/ : FAILURE Jun

5 years, 12 months

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Header file re-org

by Soby Mathew

Hi Everyone, This is regarding the header file re-organization patch that was submitted by Julius https://review.trustedfirmware.org/#/c/TF-A/trusted-firmware-a/+/1207/. It is necessary for the headers which form the ABI/handover interface for BL31 to be able to copied separately and included in other projects. The current approach taken in the patch is to define a "raw" version of such headers and have the original header include them. This certainly is the easiest way to solve the problem. But if it possible to have a more refined solution, that would be preferable. For that I have the following questions : 1. Should the project recognize these special headers and have them organized together in a folder ? It is important to recognize that the ABI can be extended by the platform. I would expect even if these "common" headers are organized into a folder, the platform specific ones need not go together with them. 2. Should the header be restricted from including standard C library headers ? 3. Should these ABI headers be allowed to include each other ? Forward declaration might be able to solve some of the issues, but good to have a policy on this. The current patch as such can be treated as step towards the ideal solution, if that solution needs more work/churn in the code base. Comments welcome. Best Regards Soby Mathew

6 years

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Re: [TF-A] [RFC] isolate the memory into different pagetable for TF-A

by feng chen

Hi Soby Mathew, Thanks for your reply. IMHO, the isolate pagetable is much more heavy. It looks like a big idea. And if we have a dynamic mapping function, which map the service's needed memory in the service's call can also mitigate this. But this can be more slower. For accessing limited resource, what's your idea? -Feng On 2019/7/9 4:27 下午, Soby Mathew wrote: > Hi Feng, > Thanks for your email. This is an interesting topic and this is an active area of work for us but in a slightly different manner. Could you please send this message to the mailing list tf-a(a)lists.trustedfirmware.org , so we can continue conversation on the list ? > > The mailing list info can be found here : > https://lists.trustedfirmware.org/mailman/listinfo/tf-a > > Thanks & Regards > Soby Mathew > >> -----Original Message----- >> From: feng chen <puck.chen(a)foxmail.com> >> Sent: 08 July 2019 16:24 >> To: Dan Handley <Dan.Handley(a)arm.com>; Soby Mathew >> <Soby.Mathew(a)arm.com>; Sandrine Bailleux <Sandrine.Bailleux(a)arm.com>; >> Alexei Fedorov <Alexei.Fedorov(a)arm.com>; Paul Beesley >> <Paul.Beesley(a)arm.com>; John Tsichritzis <John.Tsichritzis(a)arm.com> >> Subject: [RFC] isolate the memory into different pagetable for TF-A >> >> Hello maintainers, >> >> Is it possible for mapping the memory into different page-tables for TF-A? >> >> Since the ATF is running in EL3 mode, which is the highest level of ARM SoCs. >> >> And for security reason, once one service provided in TF has some >> vulnerabilities, It can access all the memory TF mapped. And it could be more >> acceptable. >> >> Thinking about the userland goto kernelland, the process use isolated page >> tables. >> >> So I want to implement this for TF-A, different memory-mapping for different >> service, and it can also use a shared mem-mapping space which all the service >> need to use. >> >> >> I want to know how do you think about this? Does this make sense to you? >> >> >> Cherrs, >> >> Feng >> > > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. >

6 years

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Re: [TF-A] [RFC] isolate the memory into different pagetable for TF-A

by Chen Feng

Move this folk to list > 在 2019年7月9日，下午4:27，Soby Mathew <Soby.Mathew(a)arm.com> 写道： > > Hi Feng, > Thanks for your email. This is an interesting topic and this is an active area of work for us but in a slightly different manner. Could you please send this message to the mailing list tf-a(a)lists.trustedfirmware.org , so we can continue conversation on the list ? > > The mailing list info can be found here : > https://lists.trustedfirmware.org/mailman/listinfo/tf-a > > Thanks & Regards > Soby Mathew > >> -----Original Message----- >> From: feng chen <puck.chen(a)foxmail.com> >> Sent: 08 July 2019 16:24 >> To: Dan Handley <Dan.Handley(a)arm.com>; Soby Mathew >> <Soby.Mathew(a)arm.com>; Sandrine Bailleux <Sandrine.Bailleux(a)arm.com>; >> Alexei Fedorov <Alexei.Fedorov(a)arm.com>; Paul Beesley >> <Paul.Beesley(a)arm.com>; John Tsichritzis <John.Tsichritzis(a)arm.com> >> Subject: [RFC] isolate the memory into different pagetable for TF-A >> >> Hello maintainers, >> >> Is it possible for mapping the memory into different page-tables for TF-A? >> >> Since the ATF is running in EL3 mode, which is the highest level of ARM SoCs. >> >> And for security reason, once one service provided in TF has some >> vulnerabilities, It can access all the memory TF mapped. And it could be more >> acceptable. >> >> Thinking about the userland goto kernelland, the process use isolated page >> tables. >> >> So I want to implement this for TF-A, different memory-mapping for different >> service, and it can also use a shared mem-mapping space which all the service >> need to use. >> >> >> I want to know how do you think about this? Does this make sense to you? >> >> >> Cherrs, >> >> Feng >> > > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 years

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Defects detected by Coverity Scan Online

by Sandrine Bailleux

Hello, As you may be aware, Trusted Firmware-A source code regularly gets analyzed by Coverity Scan Online [1]. This is a free service offered by Synopsys for open source projects, that TF-A has used since 2015. The analysis currently gets driven by Arm's internal CI system. We've recently made some improvements to this setup, which led to the tool analyzing more files. The latest analysis report from this morning shows 65 newly-found defects, scattered across the code base. We would need help from the TF-A community for analyzing and fixing them, especially those in platform ports and drivers. Note that there might be false positives, in which case we would just triage them as such in the tool's database. Hopefully everyone should be able to view the defects, according to the tool's settings. You might need to create an account on https://scan.coverity.com for that. Best regards, Sandrine [1] https://scan.coverity.com/projects/arm-software-arm-trusted-firmware

6 years

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Why is assembly macro used for registering multi-console driver?

by Masahiro Yamada

Hi, Probably, I should have asked this before pushing my code. I have a question about finalize_console_register. Platforms call console_*_register() from C code. I do not know why we need to fill the callbacks in the assembler macro, finalize_console_register. We could call console_register() directly from C code, like this: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1426/3/plat/… Maybe, we may want to register the console so early in order to enable plat/common/aarch64/crash_console_helpers.S in the boot-up code?

6 years

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Re: [TF-A] Armv8A Suspend/Resume reference code

by Soby Mathew

> -----Original Message----- > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Gutierrez, > Hernan Ildefonso (Boise R&D, FW) via TF-A > Sent: 24 June 2019 22:35 > To: tf-a(a)lists.trustedfirmware.org > Subject: [TF-A] Armv8A Suspend/Resume reference code > > Hi, > > I am looking for reference code for ArmV8A core suspend/resume. > Are there code references that are suggested to look for? > Application notes to read? > Hi Hernan, The PSCI Spec[1] specifies power management on ARM CPUs and this includes suspend and resume. The TF-A provides an implementation of PSCI with appropriate hooks to plug-in in platform specifics. There are documents in the `docs` folder which cover different aspects of PSCI implementation like PSCI topology [2], CPU specifics [3], and platform porting guide [4]. In terms of adding support for a new platform, it is most likely that all the architectural (as in ARMv8A reference manual) and the CPU specific power management as specified in the TRM are covered already (see lib/cpus/ folder for CPUs already supported). So it’s a matter of implementing the platform hooks as mentioned in the porting guide [4]. With respect to implementing platform hooks, the ARM reference platforms like FVP provide an example of how the hooks can be implemented (see fvp_pm.c/fvp_topology.c ). So if you platform is a GICv3 system and the power controller already uses SCMI as the protocol for communication, then most of the code in FVP can be reused for your platform. Hope that provides a starting point for you to begin. [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coord… [2] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/about/docs/desi… [3] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/about/docs/desi… (see CPU specific operations framework) [4] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/about/docs/gett… (see Power State Coordination Interface) > Any pointers will be appreciated, thanks. > > Hernan > > -- > TF-A mailing list > TF-A(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-a

6 years

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Armv8A Suspend/Resume reference code

by Gutierrez, Hernan Ildefonso (Boise R&D, FW)

Hi, I am looking for reference code for ArmV8A core suspend/resume. Are there code references that are suggested to look for? Application notes to read? Any pointers will be appreciated, thanks. Hernan

6 years

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Re: [TF-A] New console interface porting examples

by Soby Mathew

Hi, We are planning merge the patch removing support for legacy console support this week. This is a gentle reminder for platforms not yet migrated to the MULTI_CONSOLE_API. Best Regards Soby Mathew > -----Original Message----- > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Ambroise > Vincent via TF-A > Sent: 31 May 2019 10:40 > To: jens.wiklander(a)linaro.org; yamada.masahiro(a)socionext.com; > siva.durga.paladugu(a)xilinx.com; vwadekar(a)nvidia.com; > bryan.odonoghue(a)linaro.org; jun.nie(a)linaro.org > Cc: tf-a(a)lists.trustedfirmware.org; nd <nd(a)arm.com> > Subject: [TF-A] New console interface porting examples > > Hi, > > An update on the new console API > (https://github.com/ARM-software/tf-issues/issues/692): > > You will find patches below for the platforms that haven't done the migration > to the new interface yet, in order to give them something to test and > potentially adapt if it doesn't work as intended. The commits are independent > from each other and can be easily cherry-picked. > > Tegra: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1192/ > > Zynqmp: https://review.trustedfirmware.org/c/TF-A/trusted-firmware- > a/+/1193/ > > Uniphier: > https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1194/ > > Qemu: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1195/ > > Warp7: a very small patch to look at, removing a soon to be deleted legacy file > from the platform makefile: > https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1191/ > > > As you know, the old interface is going to be removed at the end of June > by https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/842/ > > > Regards > > -- > TF-A mailing list > TF-A(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-a

6 years

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Re: [TF-A] Can 1 Core in EL3 elevate other 3 cores to EL3?

by Soby Mathew

> -----Original Message----- > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Thor > Thayer via TF-A > Sent: 20 June 2019 09:05 > To: tf-a(a)lists.trustedfirmware.org > Subject: [TF-A] Can 1 Core in EL3 elevate other 3 cores to EL3? > > Hi, > > I have a quad-core ARM64 Cortex-A53 where 1 core is executing in EL3 while > the other 3 cores are in EL1. The 3 cores in EL1 are spinning in a WFI loop. The > EL3 CPU transitioned to EL3 as a result of the PSCI RESET2 call from Linux. > > Is there a way for the EL3 core to switch the other cores into EL3 easily? Hi Thor, One way to do this to configure an IPI (SGI in GICv3 terminology) to be an EL3 interrupt (Group 0). Trigger this IPI from the first core to all the other 3 cores. This will cause the 3 cores to transition to EL3 to handle the EL3 interrupt and you will have to configure a suitable interrupt handler. Implication of this new EL3 IPI is that it can also cause the core to transition to EL3 if triggered when executing in Secure world. Also be aware that configuration of any EL3 interrupt will affect the routing model and change the behaviour of normal world interrupts when executing in Secure world. The secure world executing a "yielding" SMC request will get pre-empted on occurrence of normal world interrupt and the secure world may not get a chance to do a "controlled exit". Usually the PSCI_RESET2 can work without all the cores being in EL3. Could you elaborate why the other cores need to be in EL3 for this reset? > > As far as I know, the communication between cores takes place through the IPI. > Unfortunately, in my case, an SError has occurred that is masking the IPI. > If I understand correctly, the PSCI_RESET2 is being issued after the SError has happened on other cores. The EL3 IPI should cause these cores to transition to EL3 regardless of the interrupt mask state at lower Els. > Thanks, > > Thor > -- > TF-A mailing list > TF-A(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-a

6 years

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Can 1 Core in EL3 elevate other 3 cores to EL3?

by Thor Thayer

Hi, I have a quad-core ARM64 Cortex-A53 where 1 core is executing in EL3 while the other 3 cores are in EL1. The 3 cores in EL1 are spinning in a WFI loop. The EL3 CPU transitioned to EL3 as a result of the PSCI RESET2 call from Linux. Is there a way for the EL3 core to switch the other cores into EL3 easily? As far as I know, the communication between cores takes place through the IPI. Unfortunately, in my case, an SError has occurred that is masking the IPI. Thanks, Thor

6 years

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Re: [TF-A] Arm trusted firmware reads wrong fip file from flash on hikey960v2

by Soby Mathew

> -----Original Message----- > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of David > Cerdeira via TF-A > Sent: 04 June 2019 10:04 > To: tf-a(a)lists.trustedfirmware.org > Subject: [TF-A] Arm trusted firmware reads wrong fip file from flash on > hikey960v2 > > Greetings, > i’m having trouble getting arm trusted firmware to work on hikey960v2 I > followed all the steps in this guide https://github.com/ARM-software/arm- > trusted-firmware/blob/master/docs/plat/hikey960.rst, > and the steps in https://optee.readthedocs.io/building/devices/hikey960.html > The problem seems to be in reading the fip.bin, or rather the problem is > writing the fip file as it seems it is not properly flashed. > ATF bl2 fails to find the UUID of the BL2_SCP image in the fip.bin output by the > build process, the fip file it reads from flash only has the BL31 and BL33 UUIDs. > > I tried checking older versions of ATF, as I figured it might be a problem in > current versions, but the same problems occurred. Hi David, I don’t have much insight into platform specifics. One suggestion is to try with pre-built binaries and once they are working, replace with your custom ones. This page may help : http://releases.linaro.org/96boards/hikey/linaro/debian/15.11/ The Hikey Platform maintainers may be able to help more in this regard. Best Regards Soby Mathew > > At this moment I feel the problem is in the flashing step. > I tried moving the partitions in the partition tables, as well as the value of the > macro HIKEY960_FIP_BASE present in hikey960_def.h to match what I thought > would be the writing position of the file in the partition, but without success. > > If anyone could give me any idea as to what the problem might be, that’d be > great Best regards, David Cerdeira > -- > TF-A mailing list > TF-A(a)lists.trustedfirmware.org > https://lists.trustedfirmware.org/mailman/listinfo/tf-a

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Re: [TF-A] [PATCH 2/2] plat: imx7: Add PicoPi iMX7D basic support

by Sandrine Bailleux

Hi Jun, Thank you for your patches. We do not use this mailing list for patch submission/code review, instead we use Gerrit. Could you please upload these patches on review.trustedfirmware.org? The following wiki page might be helpful: https://developer.trustedfirmware.org/w/tf_a/gerrit-getting-started/ Many thanks, Sandrine Bailleux

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[PATCH 1/2] plat: imx7: refactor code for reuse

by Jun Nie

for the i.MX7 SOCs, part of the code for platform setup implementation can be reused and make it common for all these SoCs. this patch extracts the common part for reuse. Signed-off-by: Jun Nie <jun.nie(a)linaro.org> --- .../imx/imx7/{warp7/platform.mk => common/imx7.mk} | 51 ++---- plat/imx/imx7/common/imx7_bl2_el3_common.c | 203 +++++++++++++++++++++ .../imx7_bl2_mem_params_desc.c} | 12 +- .../warp7_helpers.S => common/imx7_helpers.S} | 8 +- .../imx7_image_load.c} | 0 .../imx7_io_storage.c} | 22 +-- .../{warp7/warp7_rotpk.S => common/imx7_rotpk.S} | 10 +- .../imx7_trusted_boot.c} | 6 +- plat/imx/imx7/include/imx7_def.h | 20 ++ plat/imx/imx7/warp7/include/platform_def.h | 59 +++--- plat/imx/imx7/warp7/platform.mk | 119 +----------- plat/imx/imx7/warp7/warp7_bl2_el3_setup.c | 184 +------------------ plat/imx/imx7/warp7/warp7_private.h | 15 -- 13 files changed, 303 insertions(+), 406 deletions(-) copy plat/imx/imx7/{warp7/platform.mk => common/imx7.mk} (73%) create mode 100644 plat/imx/imx7/common/imx7_bl2_el3_common.c rename plat/imx/imx7/{warp7/warp7_bl2_mem_params_desc.c => common/imx7_bl2_mem_params_desc.c} (87%) rename plat/imx/imx7/{warp7/aarch32/warp7_helpers.S => common/imx7_helpers.S} (88%) rename plat/imx/imx7/{warp7/warp7_image_load.c => common/imx7_image_load.c} (100%) rename plat/imx/imx7/{warp7/warp7_io_storage.c => common/imx7_io_storage.c} (95%) rename plat/imx/imx7/{warp7/warp7_rotpk.S => common/imx7_rotpk.S} (57%) rename plat/imx/imx7/{warp7/warp7_trusted_boot.c => common/imx7_trusted_boot.c} (80%) create mode 100644 plat/imx/imx7/include/imx7_def.h delete mode 100644 plat/imx/imx7/warp7/warp7_private.h diff --git a/plat/imx/imx7/warp7/platform.mk b/plat/imx/imx7/common/imx7.mk similarity index 73% copy from plat/imx/imx7/warp7/platform.mk copy to plat/imx/imx7/common/imx7.mk index 6cd7566..cc6a3e4 100644 --- a/plat/imx/imx7/warp7/platform.mk +++ b/plat/imx/imx7/common/imx7.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -22,10 +22,9 @@ endif # Platform PLAT_INCLUDES := -Idrivers/imx/uart \ -Iplat/imx/common/include/ \ - -Iplat/imx/imx7/warp7/include \ + -Iplat/imx/imx7/include \ -Idrivers/imx/timer \ -Idrivers/imx/usdhc \ - -Iplat/imx/imx7/include # Translation tables library include lib/xlat_tables_v2/xlat_tables.mk @@ -41,7 +40,6 @@ BL2_SOURCES += common/desc_image_load.c \ drivers/imx/timer/imx_gpt.c \ drivers/imx/uart/imx_uart.c \ drivers/imx/uart/imx_crash_uart.S \ - drivers/imx/usdhc/imx_usdhc.c \ lib/aarch32/arm32_aeabi_divmod.c \ lib/aarch32/arm32_aeabi_divmod_a32.S \ lib/cpus/aarch32/cortex_a7.S \ @@ -53,12 +51,12 @@ BL2_SOURCES += common/desc_image_load.c \ plat/imx/common/imx_io_mux.c \ plat/imx/common/imx_snvs.c \ plat/imx/common/imx_wdog.c \ - plat/imx/common/imx7_clock.c \ - plat/imx/imx7/warp7/aarch32/warp7_helpers.S \ - plat/imx/imx7/warp7/warp7_bl2_el3_setup.c \ - plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c \ - plat/imx/imx7/warp7/warp7_io_storage.c \ - plat/imx/imx7/warp7/warp7_image_load.c \ + plat/imx/common/imx7_clock.c \ + plat/imx/imx7/common/imx7_bl2_mem_params_desc.c \ + plat/imx/imx7/common/imx7_bl2_el3_common.c \ + plat/imx/imx7/common/imx7_helpers.S \ + plat/imx/imx7/common/imx7_image_load.c \ + plat/imx/imx7/common/imx7_io_storage.c \ plat/imx/common/aarch32/imx_uart_console.S \ ${XLAT_TABLES_LIB_SRCS} @@ -74,8 +72,8 @@ AUTH_SOURCES := drivers/auth/auth_mod.c \ BL2_SOURCES += ${AUTH_SOURCES} \ plat/common/tbbr/plat_tbbr.c \ - plat/imx/imx7/warp7/warp7_trusted_boot.c \ - plat/imx/imx7/warp7/warp7_rotpk.S + plat/imx/imx7/common/imx7_trusted_boot.c \ + plat/imx/imx7/common/imx7_rotpk.S ROT_KEY = $(BUILD_PLAT)/rot_key.pem ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin @@ -83,7 +81,7 @@ ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin $(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) $(eval $(call MAKE_LIB_DIRS)) -$(BUILD_PLAT)/bl2/warp7_rotpk.o: $(ROTPK_HASH) +$(BUILD_PLAT)/bl2/imx7_rotpk.o: $(ROTPK_HASH) certificates: $(ROT_KEY) @@ -99,33 +97,6 @@ $(ROTPK_HASH): $(ROT_KEY) openssl dgst -sha256 -binary > $@ 2>/dev/null endif -# Build config flags -# ------------------ - -WORKAROUND_CVE_2017_5715 := 0 - -# Enable reset to BL31 by default -RESET_TO_BL31 := 0 - -# Non-TF Boot ROM -BL2_AT_EL3 := 1 - -# Indicate single-core -COLD_BOOT_SINGLE_CPU := 1 - -# Have different sections for code and rodata -SEPARATE_CODE_AND_RODATA := 1 - -# Use Coherent memory -USE_COHERENT_MEM := 1 - -# Use multi console API -MULTI_CONSOLE_API := 1 - -# PLAT_WARP7_UART -PLAT_WARP7_UART :=1 -$(eval $(call add_define,PLAT_WARP7_UART)) - # Add the build options to pack BLx images and kernel device tree # in the FIP if the platform requires. ifneq ($(BL2),) diff --git a/plat/imx/imx7/common/imx7_bl2_el3_common.c b/plat/imx/imx7/common/imx7_bl2_el3_common.c new file mode 100644 index 0000000..d381895 --- /dev/null +++ b/plat/imx/imx7/common/imx7_bl2_el3_common.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <platform_def.h> + +#include <arch_helpers.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <common/desc_image_load.h> +#include <drivers/mmc.h> +#include <lib/xlat_tables/xlat_mmu_helpers.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <lib/mmio.h> +#include <lib/optee_utils.h> +#include <lib/utils.h> + +#include <imx_aips.h> +#include <imx_caam.h> +#include <imx_clock.h> +#include <imx_csu.h> +#include <imx_gpt.h> +#include <imx_io_mux.h> +#include <imx_uart.h> +#include <imx_snvs.h> +#include <imx_usdhc.h> +#include <imx_wdog.h> +#include <imx7_def.h> + +#define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ + CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M) + +uintptr_t plat_get_ns_image_entrypoint(void) +{ + return IMX7_UBOOT_BASE; +} + +static uint32_t imx7_get_spsr_for_bl32_entry(void) +{ + return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, + DISABLE_ALL_EXCEPTIONS); +} + +static uint32_t imx7_get_spsr_for_bl33_entry(void) +{ + return SPSR_MODE32(MODE32_svc, + plat_get_ns_image_entrypoint() & 0x1, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); +} + +#ifndef AARCH32_SP_OPTEE +#error "Must build with OPTEE support included" +#endif + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + int err = 0; + bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); + bl_mem_params_node_t *hw_cfg_mem_params = NULL; + + bl_mem_params_node_t *pager_mem_params = NULL; + bl_mem_params_node_t *paged_mem_params = NULL; + + assert(bl_mem_params); + + switch (image_id) { + case BL32_IMAGE_ID: + pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); + assert(pager_mem_params); + + paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); + assert(paged_mem_params); + + err = parse_optee_header(&bl_mem_params->ep_info, + &pager_mem_params->image_info, + &paged_mem_params->image_info); + if (err != 0) + WARN("OPTEE header parse error.\n"); + + /* + * When ATF loads the DTB the address of the DTB is passed in + * arg2, if an hw config image is present use the base address + * as DTB address an pass it as arg2 + */ + hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID); + + bl_mem_params->ep_info.args.arg0 = + bl_mem_params->ep_info.args.arg1; + bl_mem_params->ep_info.args.arg1 = 0; + if (hw_cfg_mem_params) + bl_mem_params->ep_info.args.arg2 = + hw_cfg_mem_params->image_info.image_base; + else + bl_mem_params->ep_info.args.arg2 = 0; + bl_mem_params->ep_info.args.arg3 = 0; + bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl32_entry(); + break; + + case BL33_IMAGE_ID: + /* AArch32 only core: OP-TEE expects NSec EP in register LR */ + pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); + assert(pager_mem_params); + pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; + + /* BL33 expects to receive the primary CPU MPID (through r0) */ + bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); + bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl33_entry(); + break; + + default: + /* Do nothing in default case */ + break; + } + + return err; +} + +void bl2_el3_plat_arch_setup(void) +{ + /* Setup the MMU here */ +} + +static void imx7_setup_system_counter(void) +{ + unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS; + + /* Set the frequency table index to our target frequency */ + write_cntfrq(freq); + + /* Enable system counter @ frequency table index 0, halt on debug */ + mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, + CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN); +} + +static void imx7_setup_wdog_clocks(void) +{ + uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT; + + imx_clock_set_wdog_clk_root_bits(wdog_en_bits); + imx_clock_enable_wdog(0); + imx_clock_enable_wdog(1); + imx_clock_enable_wdog(2); + imx_clock_enable_wdog(3); +} + + +/* + * bl2_el3_early_platform_setup() + * MMU off + */ +void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4) +{ + static console_imx_uart_t console; + int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME; + + /* Initialize common components */ + imx_aips_init(); + imx_csu_init(); + imx_snvs_init(); + imx_gpt_ops_init(GPT1_BASE_ADDR); + imx_clock_init(); + imx7_setup_system_counter(); + imx7_setup_wdog_clocks(); + + /* Platform specific setup */ + imx7_platform_setup(arg1, arg2, arg3, arg4); + + /* Init UART, clock should be enabled in imx7_platform_setup() */ + console_imx_uart_register(PLAT_IMX7_BOOT_UART_BASE, + PLAT_IMX7_BOOT_UART_CLK_IN_HZ, + PLAT_IMX7_CONSOLE_BAUDRATE, + &console); + console_set_scope(&console.console, console_scope); + + /* Open handles to persistent storage */ + plat_imx7_io_setup(); + + /* Setup higher-level functionality CAAM, RTC etc */ + imx_caam_init(); + imx_wdog_init(); + + /* Print out the expected memory map */ + VERBOSE("\tOPTEE 0x%08x-0x%08x\n", IMX7_OPTEE_BASE, IMX7_OPTEE_LIMIT); + VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT); + VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT); + VERBOSE("\tFIP 0x%08x-0x%08x\n", IMX7_FIP_BASE, IMX7_FIP_LIMIT); + VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", IMX7_DTB_OVERLAY_BASE, IMX7_DTB_OVERLAY_LIMIT); + VERBOSE("\tDTB 0x%08x-0x%08x\n", IMX7_DTB_BASE, IMX7_DTB_LIMIT); + VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", IMX7_UBOOT_BASE, IMX7_UBOOT_LIMIT); +} + +/* + * bl2_platform_setup() + * MMU on - enabled by bl2_el3_plat_arch_setup() + */ +void bl2_platform_setup(void) +{ +} diff --git a/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c similarity index 87% rename from plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c rename to plat/imx/imx7/common/imx7_bl2_mem_params_desc.c index c670d42..c530df9 100644 --- a/plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c +++ b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c @@ -22,8 +22,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = WARP7_OPTEE_BASE, - .image_info.image_max_size = WARP7_OPTEE_SIZE, + .image_info.image_base = IMX7_OPTEE_BASE, + .image_info.image_max_size = IMX7_OPTEE_SIZE, .next_handoff_image_id = BL33_IMAGE_ID, }, @@ -36,8 +36,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = WARP7_OPTEE_BASE, - .image_info.image_max_size = WARP7_OPTEE_SIZE, + .image_info.image_base = IMX7_OPTEE_BASE, + .image_info.image_max_size = IMX7_OPTEE_SIZE, .next_handoff_image_id = INVALID_IMAGE_ID, }, @@ -70,8 +70,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = WARP7_UBOOT_BASE, - .image_info.image_max_size = WARP7_UBOOT_SIZE, + .image_info.image_base = IMX7_UBOOT_BASE, + .image_info.image_max_size = IMX7_UBOOT_SIZE, # endif /* PRELOADED_BL33_BASE */ .next_handoff_image_id = INVALID_IMAGE_ID, diff --git a/plat/imx/imx7/warp7/aarch32/warp7_helpers.S b/plat/imx/imx7/common/imx7_helpers.S similarity index 88% rename from plat/imx/imx7/warp7/aarch32/warp7_helpers.S rename to plat/imx/imx7/common/imx7_helpers.S index 3695b32..3dc808e 100644 --- a/plat/imx/imx7/warp7/aarch32/warp7_helpers.S +++ b/plat/imx/imx7/common/imx7_helpers.S @@ -35,14 +35,14 @@ func plat_get_my_entrypoint endfunc plat_get_my_entrypoint func plat_crash_console_init - mov_imm r0, PLAT_WARP7_BOOT_UART_BASE - mov_imm r1, PLAT_WARP7_BOOT_UART_CLK_IN_HZ - mov_imm r2, PLAT_WARP7_CONSOLE_BAUDRATE + mov_imm r0, PLAT_IMX7_BOOT_UART_BASE + mov_imm r1, PLAT_IMX7_BOOT_UART_CLK_IN_HZ + mov_imm r2, PLAT_IMX7_CONSOLE_BAUDRATE b imx_crash_uart_init endfunc plat_crash_console_init func plat_crash_console_putc - mov_imm r1, PLAT_WARP7_BOOT_UART_BASE + mov_imm r1, PLAT_IMX7_BOOT_UART_BASE b imx_crash_uart_putc endfunc plat_crash_console_putc diff --git a/plat/imx/imx7/warp7/warp7_image_load.c b/plat/imx/imx7/common/imx7_image_load.c similarity index 100% rename from plat/imx/imx7/warp7/warp7_image_load.c rename to plat/imx/imx7/common/imx7_image_load.c diff --git a/plat/imx/imx7/warp7/warp7_io_storage.c b/plat/imx/imx7/common/imx7_io_storage.c similarity index 95% rename from plat/imx/imx7/warp7/warp7_io_storage.c rename to plat/imx/imx7/common/imx7_io_storage.c index fcfb503..d12a8a2 100644 --- a/plat/imx/imx7/warp7/warp7_io_storage.c +++ b/plat/imx/imx7/common/imx7_io_storage.c @@ -19,21 +19,21 @@ static const io_dev_connector_t *fip_dev_con; static uintptr_t fip_dev_handle; -#ifndef WARP7_FIP_MMAP +#ifndef IMX7_FIP_MMAP static const io_dev_connector_t *mmc_dev_con; static uintptr_t mmc_dev_handle; static const io_block_spec_t mmc_fip_spec = { - .offset = WARP7_FIP_MMC_BASE, - .length = WARP7_FIP_SIZE + .offset = IMX7_FIP_MMC_BASE, + .length = IMX7_FIP_SIZE }; static const io_block_dev_spec_t mmc_dev_spec = { /* It's used as temp buffer in block driver. */ .buffer = { - .offset = WARP7_FIP_BASE, + .offset = IMX7_FIP_BASE, /* do we need a new value? */ - .length = WARP7_FIP_SIZE + .length = IMX7_FIP_SIZE }, .ops = { .read = mmc_read_blocks, @@ -49,8 +49,8 @@ static const io_dev_connector_t *memmap_dev_con; static uintptr_t memmap_dev_handle; static const io_block_spec_t fip_block_spec = { - .offset = WARP7_FIP_BASE, - .length = WARP7_FIP_SIZE + .offset = IMX7_FIP_BASE, + .length = IMX7_FIP_SIZE }; static int open_memmap(const uintptr_t spec); #endif @@ -106,7 +106,7 @@ struct plat_io_policy { }; static const struct plat_io_policy policies[] = { -#ifndef WARP7_FIP_MMAP +#ifndef IMX7_FIP_MMAP [FIP_IMAGE_ID] = { &mmc_dev_handle, (uintptr_t)&mmc_fip_spec, @@ -190,7 +190,7 @@ static int open_fip(const uintptr_t spec) return result; } -#ifndef WARP7_FIP_MMAP +#ifndef IMX7_FIP_MMAP static int open_mmc(const uintptr_t spec) { int result; @@ -240,11 +240,11 @@ int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, return result; } -void plat_warp7_io_setup(void) +void plat_imx7_io_setup(void) { int result __unused; -#ifndef WARP7_FIP_MMAP +#ifndef IMX7_FIP_MMAP result = register_io_dev_block(&mmc_dev_con); assert(result == 0); diff --git a/plat/imx/imx7/warp7/warp7_rotpk.S b/plat/imx/imx7/common/imx7_rotpk.S similarity index 57% rename from plat/imx/imx7/warp7/warp7_rotpk.S rename to plat/imx/imx7/common/imx7_rotpk.S index f74b6d2..8bd53c2 100644 --- a/plat/imx/imx7/warp7/warp7_rotpk.S +++ b/plat/imx/imx7/common/imx7_rotpk.S @@ -1,15 +1,15 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ - .global warp7_rotpk_hash - .global warp7_rotpk_hash_end -warp7_rotpk_hash: + .global imx7_rotpk_hash + .global imx7_rotpk_hash_end +imx7_rotpk_hash: /* DER header */ .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 /* SHA256 */ .incbin ROTPK_HASH -warp7_rotpk_hash_end: +imx7_rotpk_hash_end: diff --git a/plat/imx/imx7/warp7/warp7_trusted_boot.c b/plat/imx/imx7/common/imx7_trusted_boot.c similarity index 80% rename from plat/imx/imx7/warp7/warp7_trusted_boot.c rename to plat/imx/imx7/common/imx7_trusted_boot.c index 6a00224..cd27128 100644 --- a/plat/imx/imx7/warp7/warp7_trusted_boot.c +++ b/plat/imx/imx7/common/imx7_trusted_boot.c @@ -6,13 +6,13 @@ #include <plat/common/platform.h> -extern char warp7_rotpk_hash[], warp7_rotpk_hash_end[]; +extern char imx7_rotpk_hash[], imx7_rotpk_hash_end[]; int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, unsigned int *flags) { - *key_ptr = warp7_rotpk_hash; - *key_len = warp7_rotpk_hash_end - warp7_rotpk_hash; + *key_ptr = imx7_rotpk_hash; + *key_len = imx7_rotpk_hash_end - imx7_rotpk_hash; *flags = ROTPK_IS_HASH; return 0; diff --git a/plat/imx/imx7/include/imx7_def.h b/plat/imx/imx7/include/imx7_def.h new file mode 100644 index 0000000..046f031 --- /dev/null +++ b/plat/imx/imx7/include/imx7_def.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __IMX7_DEF_H__ +#define __IMX7_DEF_H__ + +#include <stdint.h> + + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_imx7_io_setup(void); +void imx7_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4); + +#endif /*__IMX7_DEF_H__ */ diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h index d58382f..4f71908 100644 --- a/plat/imx/imx7/warp7/include/platform_def.h +++ b/plat/imx/imx7/warp7/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,13 +74,13 @@ #define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE) /* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */ -#define WARP7_OPTEE_SIZE 0x02000000 -#define WARP7_OPTEE_BASE (DRAM_LIMIT - WARP7_OPTEE_SIZE) -#define WARP7_OPTEE_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE) +#define IMX7_OPTEE_SIZE 0x02000000 +#define IMX7_OPTEE_BASE (DRAM_LIMIT - IMX7_OPTEE_SIZE) +#define IMX7_OPTEE_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) /* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */ #define BL2_RAM_SIZE 0x00100000 -#define BL2_RAM_BASE (WARP7_OPTEE_BASE - BL2_RAM_SIZE) +#define BL2_RAM_BASE (IMX7_OPTEE_BASE - BL2_RAM_SIZE) #define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE) /* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/ @@ -89,28 +89,28 @@ #define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE) /* Define the absolute location of u-boot 0x87800000 - 0x87900000 */ -#define WARP7_UBOOT_SIZE 0x00100000 -#define WARP7_UBOOT_BASE (DRAM_BASE + 0x7800000) -#define WARP7_UBOOT_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE) +#define IMX7_UBOOT_SIZE 0x00100000 +#define IMX7_UBOOT_BASE (DRAM_BASE + 0x7800000) +#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) /* Define FIP image absolute location 0x80000000 - 0x80100000 */ -#define WARP7_FIP_SIZE 0x00100000 -#define WARP7_FIP_BASE (DRAM_BASE) -#define WARP7_FIP_LIMIT (WARP7_FIP_BASE + WARP7_FIP_SIZE) +#define IMX7_FIP_SIZE 0x00100000 +#define IMX7_FIP_BASE (DRAM_BASE) +#define IMX7_FIP_LIMIT (IMX7_FIP_BASE + IMX7_FIP_SIZE) /* Define FIP image location at 1MB offset */ -#define WARP7_FIP_MMC_BASE (1024 * 1024) +#define IMX7_FIP_MMC_BASE (1024 * 1024) /* Define the absolute location of DTB 0x83000000 - 0x83100000 */ -#define WARP7_DTB_SIZE 0x00100000 -#define WARP7_DTB_BASE (DRAM_BASE + 0x03000000) -#define WARP7_DTB_LIMIT (WARP7_DTB_BASE + WARP7_DTB_SIZE) +#define IMX7_DTB_SIZE 0x00100000 +#define IMX7_DTB_BASE (DRAM_BASE + 0x03000000) +#define IMX7_DTB_LIMIT (IMX7_DTB_BASE + IMX7_DTB_SIZE) /* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */ -#define WARP7_DTB_OVERLAY_SIZE 0x00001000 -#define WARP7_DTB_OVERLAY_BASE WARP7_DTB_LIMIT -#define WARP7_DTB_OVERLAY_LIMIT (WARP7_DTB_OVERLAY_BASE + \ - WARP7_DTB_OVERLAY_SIZE) +#define IMX7_DTB_OVERLAY_SIZE 0x00001000 +#define IMX7_DTB_OVERLAY_BASE IMX7_DTB_LIMIT +#define IMX7_DTB_OVERLAY_LIMIT (IMX7_DTB_OVERLAY_BASE + \ + IMX7_DTB_OVERLAY_SIZE) /* * BL2 specific defines. @@ -124,14 +124,14 @@ /* * BL3-2/OPTEE */ -# define BL32_BASE WARP7_OPTEE_BASE -# define BL32_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE) +# define BL32_BASE IMX7_OPTEE_BASE +# define BL32_LIMIT (IMX7_OPTEE_BASE + IMX7_OPTEE_SIZE) /* * BL3-3/U-BOOT */ -#define BL33_BASE WARP7_UBOOT_BASE -#define BL33_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE) +#define BL33_BASE IMX7_UBOOT_BASE +#define BL33_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE) /* * ATF's view of memory @@ -189,9 +189,9 @@ #error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6" #endif -#define PLAT_WARP7_BOOT_UART_BASE PLAT_WARP7_UART_BASE -#define PLAT_WARP7_BOOT_UART_CLK_IN_HZ 24000000 -#define PLAT_WARP7_CONSOLE_BAUDRATE 115200 +#define PLAT_IMX7_BOOT_UART_BASE PLAT_WARP7_UART_BASE +#define PLAT_IMX7_BOOT_UART_CLK_IN_HZ 24000000 +#define PLAT_IMX7_CONSOLE_BAUDRATE 115200 /* MMC defines */ #ifndef PLAT_WARP7_SD @@ -211,13 +211,6 @@ #endif /* PLAT_WARP7_SD == 3 */ /* - * GIC related constants - */ -#define GICD_BASE 0x31001000 -#define GICC_BASE 0x31002000 -#define GICR_BASE 0 - -/* * System counter */ #define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */ diff --git a/plat/imx/imx7/warp7/platform.mk b/plat/imx/imx7/warp7/platform.mk index 6cd7566..c414fd2 100644 --- a/plat/imx/imx7/warp7/platform.mk +++ b/plat/imx/imx7/warp7/platform.mk @@ -1,107 +1,22 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # -# Architecture -$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)) - -# Tune compiler for Cortex-A7 -ifeq ($(notdir $(CC)),armclang) - TF_CFLAGS += -mfpu=neon - ASFLAGS += -mfpu=neon -else ifneq ($(findstring clang,$(notdir $(CC))),) - TF_CFLAGS += -mfpu=neon - ASFLAGS += -mfpu=neon -else - TF_CFLAGS += -mfpu=neon - ASFLAGS += -mfpu=neon -endif +# Include imx7 common +include plat/imx/imx7/common/imx7.mk # Platform -PLAT_INCLUDES := -Idrivers/imx/uart \ - -Iplat/imx/common/include/ \ - -Iplat/imx/imx7/warp7/include \ - -Idrivers/imx/timer \ - -Idrivers/imx/usdhc \ - -Iplat/imx/imx7/include - -# Translation tables library -include lib/xlat_tables_v2/xlat_tables.mk +PLAT_INCLUDES += -Iplat/imx/imx7/warp7/include \ -BL2_SOURCES += common/desc_image_load.c \ - drivers/console/aarch32/console.S \ - drivers/delay_timer/delay_timer.c \ - drivers/mmc/mmc.c \ - drivers/io/io_block.c \ - drivers/io/io_fip.c \ - drivers/io/io_memmap.c \ - drivers/io/io_storage.c \ - drivers/imx/timer/imx_gpt.c \ - drivers/imx/uart/imx_uart.c \ - drivers/imx/uart/imx_crash_uart.S \ - drivers/imx/usdhc/imx_usdhc.c \ - lib/aarch32/arm32_aeabi_divmod.c \ - lib/aarch32/arm32_aeabi_divmod_a32.S \ - lib/cpus/aarch32/cortex_a7.S \ - lib/optee/optee_utils.c \ - plat/imx/common/imx_aips.c \ - plat/imx/common/imx_caam.c \ - plat/imx/common/imx_clock.c \ - plat/imx/common/imx_csu.c \ - plat/imx/common/imx_io_mux.c \ - plat/imx/common/imx_snvs.c \ - plat/imx/common/imx_wdog.c \ - plat/imx/common/imx7_clock.c \ - plat/imx/imx7/warp7/aarch32/warp7_helpers.S \ +BL2_SOURCES += drivers/imx/usdhc/imx_usdhc.c \ plat/imx/imx7/warp7/warp7_bl2_el3_setup.c \ - plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c \ - plat/imx/imx7/warp7/warp7_io_storage.c \ - plat/imx/imx7/warp7/warp7_image_load.c \ - plat/imx/common/aarch32/imx_uart_console.S \ - ${XLAT_TABLES_LIB_SRCS} - -ifneq (${TRUSTED_BOARD_BOOT},0) - -include drivers/auth/mbedtls/mbedtls_crypto.mk -include drivers/auth/mbedtls/mbedtls_x509.mk - -AUTH_SOURCES := drivers/auth/auth_mod.c \ - drivers/auth/crypto_mod.c \ - drivers/auth/img_parser_mod.c \ - drivers/auth/tbbr/tbbr_cot.c - -BL2_SOURCES += ${AUTH_SOURCES} \ - plat/common/tbbr/plat_tbbr.c \ - plat/imx/imx7/warp7/warp7_trusted_boot.c \ - plat/imx/imx7/warp7/warp7_rotpk.S - -ROT_KEY = $(BUILD_PLAT)/rot_key.pem -ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin - -$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) -$(eval $(call MAKE_LIB_DIRS)) - -$(BUILD_PLAT)/bl2/warp7_rotpk.o: $(ROTPK_HASH) - -certificates: $(ROT_KEY) - -$(ROT_KEY): | $(BUILD_PLAT) - @echo " OPENSSL $@" - @if [ ! -f $(ROT_KEY) ]; then \ - openssl genrsa 2048 > $@ 2>/dev/null; \ - fi - -$(ROTPK_HASH): $(ROT_KEY) - @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null -endif # Build config flags # ------------------ +ARM_CORTEX_A7 := yes WORKAROUND_CVE_2017_5715 := 0 # Enable reset to BL31 by default @@ -125,25 +40,3 @@ MULTI_CONSOLE_API := 1 # PLAT_WARP7_UART PLAT_WARP7_UART :=1 $(eval $(call add_define,PLAT_WARP7_UART)) - -# Add the build options to pack BLx images and kernel device tree -# in the FIP if the platform requires. -ifneq ($(BL2),) -$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert)) -endif -ifneq ($(BL32_EXTRA1),) -$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1)) -endif -ifneq ($(BL32_EXTRA2),) -$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2)) -endif -ifneq ($(HW_CONFIG),) -$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config)) -endif - -# Verify build config -# ------------------- - -ifeq (${ARCH},aarch64) - $(error Error: AArch64 not supported on i.mx7) -endif diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c index 0eedd21..dd56e52 100644 --- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c +++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,8 +8,6 @@ #include <platform_def.h> -#include <arch_helpers.h> -#include <common/bl_common.h> #include <common/debug.h> #include <common/desc_image_load.h> #include <drivers/console.h> @@ -17,21 +15,14 @@ #include <lib/xlat_tables/xlat_mmu_helpers.h> #include <lib/xlat_tables/xlat_tables_defs.h> #include <lib/mmio.h> -#include <lib/optee_utils.h> #include <lib/utils.h> -#include <imx_aips.h> #include <imx_caam.h> #include <imx_clock.h> -#include <imx_csu.h> -#include <imx_gpt.h> #include <imx_io_mux.h> #include <imx_uart.h> -#include <imx_snvs.h> #include <imx_usdhc.h> -#include <imx_wdog.h> - -#include "warp7_private.h" +#include <imx7_def.h> #define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M) @@ -43,102 +34,9 @@ CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\ CCM_TARGET_POST_PODF(2)) -#define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ - CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M) - #define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\ CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL) -uintptr_t plat_get_ns_image_entrypoint(void) -{ - return WARP7_UBOOT_BASE; -} - -static uint32_t warp7_get_spsr_for_bl32_entry(void) -{ - return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS); -} - -static uint32_t warp7_get_spsr_for_bl33_entry(void) -{ - return SPSR_MODE32(MODE32_svc, - plat_get_ns_image_entrypoint() & 0x1, - SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); -} - -#ifndef AARCH32_SP_OPTEE -#error "Must build with OPTEE support included" -#endif - -int bl2_plat_handle_post_image_load(unsigned int image_id) -{ - int err = 0; - bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); - bl_mem_params_node_t *hw_cfg_mem_params = NULL; - - bl_mem_params_node_t *pager_mem_params = NULL; - bl_mem_params_node_t *paged_mem_params = NULL; - - assert(bl_mem_params); - - switch (image_id) { - case BL32_IMAGE_ID: - pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); - assert(pager_mem_params); - - paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); - assert(paged_mem_params); - - err = parse_optee_header(&bl_mem_params->ep_info, - &pager_mem_params->image_info, - &paged_mem_params->image_info); - if (err != 0) - WARN("OPTEE header parse error.\n"); - - /* - * When ATF loads the DTB the address of the DTB is passed in - * arg2, if an hw config image is present use the base address - * as DTB address an pass it as arg2 - */ - hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID); - - bl_mem_params->ep_info.args.arg0 = - bl_mem_params->ep_info.args.arg1; - bl_mem_params->ep_info.args.arg1 = 0; - if (hw_cfg_mem_params) - bl_mem_params->ep_info.args.arg2 = - hw_cfg_mem_params->image_info.image_base; - else - bl_mem_params->ep_info.args.arg2 = 0; - bl_mem_params->ep_info.args.arg3 = 0; - bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry(); - break; - - case BL33_IMAGE_ID: - /* AArch32 only core: OP-TEE expects NSec EP in register LR */ - pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); - assert(pager_mem_params); - pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; - - /* BL33 expects to receive the primary CPU MPID (through r0) */ - bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); - bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry(); - break; - - default: - /* Do nothing in default case */ - break; - } - - return err; -} - -void bl2_el3_plat_arch_setup(void) -{ - /* Setup the MMU here */ -} - #define WARP7_UART1_TX_MUX \ IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA @@ -215,29 +113,6 @@ static void warp7_usdhc_setup(void) imx_usdhc_init(&params, &info); } -static void warp7_setup_system_counter(void) -{ - unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS; - - /* Set the frequency table index to our target frequency */ - write_cntfrq(freq); - - /* Enable system counter @ frequency table index 0, halt on debug */ - mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, - CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN); -} - -static void warp7_setup_wdog_clocks(void) -{ - uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT; - - imx_clock_set_wdog_clk_root_bits(wdog_en_bits); - imx_clock_enable_wdog(0); - imx_clock_enable_wdog(1); - imx_clock_enable_wdog(2); - imx_clock_enable_wdog(3); -} - static void warp7_setup_usb_clocks(void) { uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT; @@ -248,67 +123,24 @@ static void warp7_setup_usb_clocks(void) imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY); imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY); } -/* - * bl2_el3_early_platform_setup() - * MMU off - */ -void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, - u_register_t arg3, u_register_t arg4) + +void imx7_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4) { uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT; uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT; uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1; - static console_imx_uart_t console; - int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME; - - /* Initialize the AIPS */ - imx_aips_init(); - imx_csu_init(); - imx_snvs_init(); - imx_gpt_ops_init(GPT1_BASE_ADDR); - /* Initialize clocks, regulators, pin-muxes etc */ - imx_clock_init(); + /* Initialize clocks etc */ imx_clock_enable_uart(0, uart1_en_bits); imx_clock_enable_uart(5, uart6_en_bits); + imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT); - warp7_setup_system_counter(); - warp7_setup_wdog_clocks(); + warp7_setup_usb_clocks(); /* Setup pin-muxes */ warp7_setup_pinmux(); - /* Init UART, storage and friends */ - console_imx_uart_register(PLAT_WARP7_BOOT_UART_BASE, - PLAT_WARP7_BOOT_UART_CLK_IN_HZ, - PLAT_WARP7_CONSOLE_BAUDRATE, - &console); - console_set_scope(&console.console, console_scope); - warp7_usdhc_setup(); - - /* Open handles to persistent storage */ - plat_warp7_io_setup(); - - /* Setup higher-level functionality CAAM, RTC etc */ - imx_caam_init(); - imx_wdog_init(); - - /* Print out the expected memory map */ - VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT); - VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT); - VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT); - VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT); - VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", WARP7_DTB_OVERLAY_BASE, WARP7_DTB_OVERLAY_LIMIT); - VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT); - VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT); -} - -/* - * bl2_platform_setup() - * MMU on - enabled by bl2_el3_plat_arch_setup() - */ -void bl2_platform_setup(void) -{ } diff --git a/plat/imx/imx7/warp7/warp7_private.h b/plat/imx/imx7/warp7/warp7_private.h deleted file mode 100644 index cb6d900..0000000 --- a/plat/imx/imx7/warp7/warp7_private.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef WARP7_PRIVATE_H -#define WARP7_PRIVATE_H - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ -void plat_warp7_io_setup(void); - -#endif /* WARP7_PRIVATE_H */ -- 2.7.4

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Re: [TF-A] [RFC 0/2] psci: Add core wakeup operation

by John Tsichritzis

Hello Abel, What is the status of this workaround? I saw that you had a similar discussion at the kernel mailing list (https://lkml.org/lkml/2019/3/27/542) which, however, has been inactive for some time. Do you still intend to pursue that solution? If you do so, please submit your patches to review.trustedfirmware.org under the "TF-A/trusted-firmware-a" project. To login you just need your GitHub account. You can find further information about contributions in https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/about/docs/proc…, especially the "Submitting Changes" section, or contact us here. Kind regards, John -- John Tsichritzis | Graduate Software Engineer Email: john.tsichritzis(a)arm.com<mailto:john.tsichritzis@arm.com> 110 Fulbourn Road, Cambridge, CB1 9NJ, United Kingdom https://www.arm.com/ On 2019-03-27 15:35, Abel Vesa via TF-A wrote: On 19-03-27 13:45:21, Soby Mathew wrote: Hi Abel, Thanks for the RFC. On the face of it, this is a new PSCI command that would need further discussion involving Architecture and Kernel teams. I know this might be a pain. That's why I'm just asking for as many opinions on this as possible. Just to summarize my understanding: Currently any interrupt targeted to a suspended core can wake it up, but it seems that this mechanism is broken on i.MX8MQ and hence you need an explicit command to wake it. This assumes that one CPU is always ON within the system ready to poke the suspended CPU back to life. This assumption is not true always as it is legal for all the CPUs to be in suspend state at the same time. That errata is specifically for IPIs. If all the cores are in suspend, any interrupt will be able to wake one of the cores. That's why the workaround suggested in that document works. But that workaround is waking up all the cores, that's why I added this poking mechanism which is per-core. Adding the kernel team for their input. JFYI, We do not intend to review patches via the mailing list and patches should be pushed as mentioned here: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.co… Currently the project is in github but we expect to migrate to trustedfirmware.org in April. Hmm, ok. Good to know. Best Regards Soby Mathew -----Original Message----- From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org><mailto:tf-a-bounces@lists.trustedfirmware.org> On Behalf Of Abel Vesa via TF-A Sent: 27 March 2019 12:16 To: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> Subject: [TF-A] [RFC 0/2] psci: Add core wakeup operation This is more like a workaround for platforms like i.MX8MQ that have an issue related to the wake_request GIC signal integration. See E11171 here: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.nxp.c… The workaround mentioned in the document has the dissadvantage of waking up all the sleeping cores instead of just one. This patchset adds another psci op for core 'poking' (waking up). On i.MX8MQ, the plat specific implementation writes the corresponding bits in GPC to wake up independently each core. Abel Vesa (2): psci: Add cpu wake operation plat: imx8mq: Trigger SW power up per core include/lib/psci/psci.h | 3 +++ lib/psci/psci_main.c | 17 +++++++++++++++++ lib/psci/psci_setup.c | 2 ++ plat/imx/imx8m/imx8mq/gpc.c | 7 +++++++ plat/imx/imx8m/imx8mq/imx8mq_psci.c | 8 ++++++++ plat/imx/imx8m/include/gpc.h | 2 ++ 6 files changed, 39 insertions(+) -- 2.7.4 -- TF-A mailing list TF-A(a)lists.trustedfirmware.org<mailto:TF-A@lists.trustedfirmware.org> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.tru…

6 years, 1 month

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Arm trusted firmware reads wrong fip file from flash on hikey960v2

by David Cerdeira

Greetings, i’m having trouble getting arm trusted firmware to work on hikey960v2 I followed all the steps in this guide https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/…, and the steps in https://optee.readthedocs.io/building/devices/hikey960.html The problem seems to be in reading the fip.bin, or rather the problem is writing the fip file as it seems it is not properly flashed. ATF bl2 fails to find the UUID of the BL2_SCP image in the fip.bin output by the build process, the fip file it reads from flash only has the BL31 and BL33 UUIDs. I tried checking older versions of ATF, as I figured it might be a problem in current versions, but the same problems occurred. At this moment I feel the problem is in the flashing step. I tried moving the partitions in the partition tables, as well as the value of the macro HIKEY960_FIP_BASE present in hikey960_def.h to match what I thought would be the writing position of the file in the partition, but without success. If anyone could give me any idea as to what the problem might be, that’d be great Best regards, David Cerdeira

6 years, 1 month

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Regression on Poplar eMMC

by Shawn Guo

Hi Tien, We recently found a regression on Poplar eMMC in U-Boot, which seems caused by commit 3d0f30bb544a ("drivers: synopsys: Fix synopsys MMC driver"). For some reason, the setup of FIFO threshold breaks eMMC support in U-Boot [1]. Would you please suggest a sensible fix for this regression? Thanks. Shawn [1] https://discuss.96boards.org/t/uboot-mmc-init-problem/8130/3

6 years, 1 month

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New console interface porting examples

by Ambroise Vincent

Hi, An update on the new console API (https://github.com/ARM-software/tf-issues/issues/692): You will find patches below for the platforms that haven't done the migration to the new interface yet, in order to give them something to test and potentially adapt if it doesn't work as intended. The commits are independent from each other and can be easily cherry-picked. Tegra: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1192/ Zynqmp: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1193/ Uniphier: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1194/ Qemu: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1195/ Warp7: a very small patch to look at, removing a soon to be deleted legacy file from the platform makefile: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1191/ As you know, the old interface is going to be removed at the end of June by https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/842/ Regards

6 years, 1 month

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