Dear community:
I apologize in advance if this is the incorrect place to solicit for input on an issue I am having when enabling support of RSA key sizes > 2048. The environment is described below:
TI AM642-EVM board
Debian Bookworm running kernel 6.6.100, tpm_ftpm_tee.ko kernel module
Uboot booting from sdcard UEFI partition and rootfs partition
optee_os version 4.5.0 , 4.6.0, 4.7.0 (no difference in behaviour)
optee_client version 4.5.0, 4.6.0, 4.7.0 (no difference in behaviour)
optee_ftpm version 4.5.0 or 4.6.0, 4.7.0 (no difference in behaviour)
ms-tpm-20-ref commit id 98b60a44aba79b15fcce1c0d1e46cf5918400f6a and e9fc7b89d865536c46deb63f9c7d0121a3ded49c
Due to issues with RPMB, we decided to use REE_FS instead. Everything works correctly when I create RSA 2048 keys using tpm2-openssl and related tools:
sudo tpm2_createprimary -C o -G rsa2048 -g sha256 -c primary.ctx, When I try rsa3072 or 4096, I get errors from the command line response saying invalid input parameters. I changed the ms-tpm-20-ref include file TpmProfile.h to set RSA_3072 and RSA_4096 macros both to (ALG_RSA && YES). After rebuilding and running, I now get an optee panic for ANY RSA key request INCLUDING rsa2048. I read suggestions to increase the MAX_COMMAND_SIZE/MAX_RESPONSE_SIZE on both the kernel driver tpm_ftpm_tee.ko and also optee_os/optee_ftpm, as well to increase relevant TA_STACK_SIZE and TA_HEAP_SIZE and TA_DATA_SIZE, but nothing seems to change the panic output:
sudo tpm2_createprimary -C o -G rsa2048 -g sha256 -c primary.ctx============================================================
E/TC:? 0
E/TC:? 0 TA panicked with code 0xffff0007
E/LD: Status of TA bc50d971-d4c9-42c4-82cb-343fb7f37896
E/LD: arch: aarch64
E/LD: region 0: va 0x40005000 pa 0x9e8b0000 size 0x002000 flags rw-s (ldelf)
E/LD: region 1: va 0x40007000 pa 0x9e8b2000 size 0x008000 flags r-xs (ldelf)
E/LD: region 2: va 0x4000f000 pa 0x9e8ba000 size 0x001000 flags rw-s (ldelf)
E/LD: region 3: va 0x40010000 pa 0x9e8bb000 size 0x004000 flags rw-s (ldelf)
E/LD: region 4: va 0x40014000 pa 0x9e8bf000 size 0x001000 flags r--s
E/LD: region 5: va 0x40015000 pa 0x9e934000 size 0x011000 flags rw-s (stack)
E/LD: region 6: va 0x40026000 pa 0x8ebf0000 size 0x002000 flags rw-- (param)
E/LD: region 7: va 0x4006e000 pa 0x9e8c0000 size 0x058000 flags r-xs [0]
E/LD: region 8: va 0x400c6000 pa 0x9e918000 size 0x01c000 flags rw-s [0]
E/LD: [0] bc50d971-d4c9-42c4-82cb-343fb7f37896 @ 0x4006e000
E/LD: Call stack:
E/LD: 0x4006f394
E/LD: 0x40095edc
E/LD: 0x4007b5a8
E/LD: 0x400985fc
E/LD: 0x40098a70
E/LD: 0x4006fae0
E/LD: 0x400a5508
E/LD: 0x40098b9c
D/TC:? 0 user_ta_enter:195 tee_user_ta_enter: TA panicked with code 0xffff0007
D/TC:? 0 release_ta_ctx:670 Releasing panicked TA ctx
D/TC:? 0 tee_ta_invoke_command:798 Error: ffff3024 of 3
[ 218.944680] tpm tpm0: ftpm_tee_tpm_op_send: SUBMIT_COMMAND invoke error: 0xffff3024
[ 218.952379] tpm tpm0: tpm_try_transmit: send(): error -53212
D/TC:? 0 tee_ta_invoke_command:798 Error: ffff3024 of 3
[ 218.963359] tpm tpm0: ftpm_tee_tpm_op_send: SUBMIT_COMMAND invoke error: 0xffff3024
[ 218.974241] tpm tpm0: tpm_try_transmit: send(): error -53212
D/TC:? 0 tee_ta_invoke_command:798 Error: ffff3024 of 3
[ 218.985675] tpm tpm0: ftpm_tee_tpm_op_send: SUBMIT_COMMAND invoke error: 0xffff3024
[ 218.993366] tpm tpm0: tpm_try_transmit: send(): error -53212
[ 218.999044] tpm tpm0: tpm2_commit_space: error -14
ERROR:tcti:src/tss2-tcti/tcti-device.c:198:tcti_device_receive()D/TC:? 0 tee_ta_invoke_command:798 Error: ffff3024 of 3
Failed to get response size fd 3, got errno 14: Bad address
E[ 219.015351] tpm tpm0: ftpm_tee_tpm_op_send: SUBMIT_COMMAND invoke error: 0xffff3024
RROR:esys:src/tss2-esys/api/Esys_CreatePrimary.c:404:Esys_Create[ 219.028348] tpm tpm0: tpm_try_transmit: send(): error -53212
Primary_Finish() Received a non-TPM Error
ERROR:esys:src/tss2-esys/api/Esys_CreatePrimary.c:135:Esys_CreatePrimary() Esys Finish ErrorCode (0x000a000a)
ERROR: Esys_CreatePrimary(0xA000A) - tcti:IO failure
ERROR:esys:src/tss2-esys/esys_iutil.c:1145:iesys_check_sequence_async() Esys called in bad sequence.
ERROR:esys:src/tss2-esys/api/Esys_FlushContext.c:66:Esys_FlushContext() Error in async function ErrorCode (0x00070007)
=============================================================================
The last suggestion I saw was to change my dtb file to include a reserved memory region for optee shared memory and not use the default dynamic shared memory. The issue I have is kernel 6.6.100's tpm_ftpm_tee ignores the "memory-region" dts statement that references the optee_shm reserved memory at at 0xa4000000 in my case. Below is my snippet of the dts file. I heard there are patches in the kernel ftpm driver to support the reserved shared memory, but before I try the patches, can anyone opine whether this could cause the panic that I am seeing? Thanks in advance for anyone who can share any information
optee_shm: optee-shm@a4000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xa4000000 0x0 0x01000000>;
no-map;
reusable;
};
....
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
memory-region = <&optee_shm>;
};
}
Dennis Kong, P.Eng.
Staff Engineer
Perle Systems Limited
60 Renfrew Drive,
Markham, ON L3R 0E1
(905) 475-6070 ext. 2126
Hi there,
Do spmd_group0_interrupt_handler_nwd() and spmd_handle_group0_intr_swd() need to take into account handling of special INTIDs?
Like ehf_el3_interrupt_handler():
/*
* Acknowledge interrupt. Proceed with handling only for valid interrupt
* IDs. This situation may arise because of Interrupt Management
* Framework identifying an EL3 interrupt, but before it's been
* acknowledged here, the interrupt was either deasserted, or there was
* a higher-priority interrupt of another type.
*/
intr_raw = plat_ic_acknowledge_interrupt();
intr = plat_ic_get_interrupt_id(intr_raw);
if (intr == INTR_ID_UNAVAILABLE)
return 0;
Best Regards,
Joe Yang
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Hi all,
Hope you are well. I have recently joined this mailing list and am quite
keen to contribute to this project but don't know where to start.
Currently, I am going through Trusted Firmware A Documentation
<https://trustedfirmware-a.readthedocs.io/en/latest/index.html> document
and Gerrit code reviews
<https://review.trustedfirmware.org/q/status:open+-is:wip> to develop some
initial understanding and familiarity about the project.
As a first step, I am trying to understand areas where I can contribute. Is
there any simple issue for me to pick? I am happy to volunteer.
Looking forward to hearing from you,
Waqas
Hi, In the TF-A Tech Forum on July 10th 2025 Mark Dykes from Arm TF-A team
will present the topic of SMC Fuzzing with the agenda: Overview of the TF-A
fuzzer and its basic implementation in practice. Regards, Olivier.
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Hello,
Background & Justification:
MISRA C:2012 Rule 11.1 forbids the conversion from a function pointer to any
other type.
However, in the context of TF-A, we encounter scenarios where this conversion
is necessary and performed with full knowledge of the target architecture and
toolchain behavior. A prominent example is in low-level platform code, such as
transferring control between bootloader stages or passing function entry points
for CPU/core bring-up, where the conversion is unavoidable and well-understood.
One such example is the K3 PSCI driver [1] where we pass the k3_sec_entrypoint
which is of type uintptr_t, to the ti_sci_proc_set_boot_cfg
function where the parameter is of type uint64_t.
Another place that triggered the discussions behind this MISRA C issue
was the TI AM62L PSCI driver [2] that needs a 16b aligned function pointer.
We don't have to go into specific case by case discussion of solving these issues,
but just wanted to share example use cases of function pointer conversion.
Request:
I propose we formally document a project-wide MISRA C:2012 Rule 11.1 deviation,
reflecting current and future usage throughout the TF-A codebase. This deviation
allows us to balance MISRA objectives with the practical and architectural
necessities of TF-A development.
Rationale:
* Conversions between function pointers and other types are essential in several
parts of the TF-A codebase, not limited to one module or file.
* Platform-specific code (e.g., power management, bootloader hand-offs) relies
on this pattern for correct operation.
References:
[1] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/ti/k3…
[2] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/ti/k3…
--
Best regards,
Dhruva Gole
Texas Instruments Incorporated
Hello,
I want to boot Linux on ZynqMP (XCZU15EG).
I follow the standard procedure.
I have generated FSBL using Vitis.
I have compiled bl31 (tag: xilinx-v2025.1).
I have a standard boot.bif configuration looking as follows:
the_ROM_image:
{
[bootloader] fsbl.elf
[pmufw_image] pmufw.elf
[destination_cpu = a53-0, exception_level= el-3, trustzone] bl31.bin
[destination_cpu = a53-0, exception_level= el-2, load = 0x10000000] images/u-boot.bin
}
However, the bl31 reports the following error during the handoff to u-boot:
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:788
BACKTRACE: START: assert
0: F_FUNCTION: 0x2880
1: F_FUNCTION: 0x4cac
2: F_FUNCTION: 0x2628
3: F_FUNCTION: 0x36e0
4: F_FUNCTION: 0x108
5: F_FUNCTION: 0xfffcd8e8
BACKTRACE: END: assert
This is an assertion for context being uninitialized in the mmap_add_region_ctx function.
/* Static regions must be added before initializing the xlat tables. */
assert(!ctx->initialized);
Does anyone have any idea what might be wrong?
Best regards,
Michał Kruszewski
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Hi, In the TF-A Tech forum on June 26th 2025 Dhruva Gole from Texas
Instruments will present: Building Modern Industrial SoC Support in Arm
Trusted Firmware Pragmatic Approaches to Power and Clock Management
Regards, Olivier.
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Hi,
I have below queries regarding nested sError handling in TF-A, please help.
1. While handling exceptions in EL3, sError is almost unmask most of the time. Any specific reason to keep sError unmasked?
For example, while handing nested sError, we can keep sError masked in serror_sp_elx. So that no further sError comes to EL3.
And unmask sError when returning to lower ELs. Do you think this will create any problem in the system?
1. In system, sError can happen at any time. At EL3, we have nested sError handling in serror_sp_elx.
Do you think we should have similar nested sError handling in serror_sp_el0? If not, what is the reason?
1. Double fault will always lead to unhandled exception.
* Can someone help define double fault scenario?
* What is the purpose of this patch - https://github.com/ARM-software/arm-trusted-firmware/commit/c72200357aed49f…<https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_ARM-2Dsoftw…>
Is purpose only to save esr_el3 register?
Thanks
Regards,
Jaiprakash
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Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
5 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 5 of 5 defect(s)
** CID 472149: Integer handling issues (NEGATIVE_RETURNS)
_____________________________________________________________________________________________
*** CID 472149: Integer handling issues (NEGATIVE_RETURNS)
/lib/psci/psci_main.c: 300 in psci_affinity_info()
294 * - the cluster was removed from coherency as part of the CPU shutdown
295 *
296 * In this case the cache maintenace that was performed as part of the
297 * target CPUs shutdown was not seen by the current CPU's cluster. And
298 * so the cache may contain stale data for the target CPU.
299 */
>>> CID 472149: Integer handling issues (NEGATIVE_RETURNS)
>>> "target_idx" is passed to a parameter that cannot be negative.
300 flush_cpu_data_by_index(target_idx,
301 psci_svc_cpu_data.aff_info_state);
302
303 return psci_get_aff_info_state_by_idx(target_idx);
304 }
305
** CID 472148: Memory - corruptions (OVERRUN)
_____________________________________________________________________________________________
*** CID 472148: Memory - corruptions (OVERRUN)
/lib/psci/psci_main.c: 39 in psci_cpu_on()
33
34 /* Validate the target CPU */
35 if (!is_valid_mpidr(target_cpu)) {
36 return PSCI_E_INVALID_PARAMS;
37 }
38
>>> CID 472148: Memory - corruptions (OVERRUN)
>>> Overrunning callee's array of size 2 by passing argument "target_idx" (which evaluates to 4294967295) in call to "_cpu_data_by_index".
39 ep = get_cpu_data_by_index(target_idx, warmboot_ep_info);
40 /* Validate the lower EL entry point and put it in the entry_point_info */
41 rc = psci_validate_entry_point(ep, entrypoint, context_id);
42 if (rc != PSCI_E_SUCCESS) {
43 return rc;
44 }
** CID 472147: (OVERRUN)
_____________________________________________________________________________________________
*** CID 472147: (OVERRUN)
/lib/psci/psci_main.c: 300 in psci_affinity_info()
294 * - the cluster was removed from coherency as part of the CPU shutdown
295 *
296 * In this case the cache maintenace that was performed as part of the
297 * target CPUs shutdown was not seen by the current CPU's cluster. And
298 * so the cache may contain stale data for the target CPU.
299 */
>>> CID 472147: (OVERRUN)
>>> Overrunning callee's array of size 2 by passing argument "target_idx" (which evaluates to 4294967295) in call to "_cpu_data_by_index".
300 flush_cpu_data_by_index(target_idx,
301 psci_svc_cpu_data.aff_info_state);
302
303 return psci_get_aff_info_state_by_idx(target_idx);
304 }
305
/lib/psci/psci_main.c: 303 in psci_affinity_info()
297 * target CPUs shutdown was not seen by the current CPU's cluster. And
298 * so the cache may contain stale data for the target CPU.
299 */
300 flush_cpu_data_by_index(target_idx,
301 psci_svc_cpu_data.aff_info_state);
302
>>> CID 472147: (OVERRUN)
>>> Overrunning callee's array of size 2 by passing argument "target_idx" (which evaluates to 4294967295) in call to "psci_get_aff_info_state_by_idx".
303 return psci_get_aff_info_state_by_idx(target_idx);
304 }
305
306 int psci_migrate(u_register_t target_cpu)
307 {
308 int rc;
** CID 472146: Memory - corruptions (OVERRUN)
_____________________________________________________________________________________________
*** CID 472146: Memory - corruptions (OVERRUN)
/lib/el3_runtime/aarch64/context_debug.c: 107 in report_allocated_memory()
101 if (is_ctx_pauth_supported()) {
102 PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
103 }
104
105 PRINT_MEM_USAGE_SEPARATOR();
106
>>> CID 472146: Memory - corruptions (OVERRUN)
>>> Overrunning callee's array of size 2 by passing argument "i" (which evaluates to 7) in call to "cm_get_context_by_index".
107 cpu_context_t *ctx = (cpu_context_t *)cm_get_context_by_index(i,
108 security_state_idx);
109 core_total = sizeof(*ctx);
110 el3_size = sizeof(ctx->el3state_ctx);
111 gp_size = sizeof(ctx->gpregs_ctx);
112 size_other = core_total - (el3_size + gp_size);
** CID 472145: Integer handling issues (NEGATIVE_RETURNS)
_____________________________________________________________________________________________
*** CID 472145: Integer handling issues (NEGATIVE_RETURNS)
/lib/psci/psci_main.c: 39 in psci_cpu_on()
33
34 /* Validate the target CPU */
35 if (!is_valid_mpidr(target_cpu)) {
36 return PSCI_E_INVALID_PARAMS;
37 }
38
>>> CID 472145: Integer handling issues (NEGATIVE_RETURNS)
>>> "target_idx" is passed to a parameter that cannot be negative.
39 ep = get_cpu_data_by_index(target_idx, warmboot_ep_info);
40 /* Validate the lower EL entry point and put it in the entry_point_info */
41 rc = psci_validate_entry_point(ep, entrypoint, context_id);
42 if (rc != PSCI_E_SUCCESS) {
43 return rc;
44 }
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…
Hi, On June 12th 2025, the TF-A Tech forum will take place at 4.00pm UK
with the following topic: TF-RMM live activation design discussion
Presenters: Andre Przywara Soby Mathew Manish Badarkhe In this meeting, we
aim to discuss the details of live firmware activation for TF-RMM. The key
topics will include: * Design details of TF-RMM live activation * Rationale
for EL3-RMM communication changes: We will explain the motivation behind
the proposed changes to the communication mechanism between EL3 and RMM
which simplifies internal state migration for LFA, enables sharing of the
state across RMM instances that are live-activated, supports localized
per-CPU allocations for NUMA and multi-chip configurations, decouples the
RMM binary from platform-specifics. * LFA SMC Implementation in EL3: We
will also provide an overview of the LFA SMC implementation at EL3.
Regards, Olivier.
TF-A Tech Forum
Thursday Jun 12, 2025 ⋅ 5pm – 6pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A
Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu,
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Hi All,
I'm new to TF-A. While working on enabling Linux on A-520 FVP, I ran into
an issue that I wanted to ask about.
My stack looks like this:TF-A->U-boot->kernel. Initially I was able to boot
on Base FVP(FVP_Base_RevC-2xAEMvA) and get to the linux console. Now we
need to enable the same for A-520 FVP as our soc will be A-520. I saw the
crash happening very early in "cpu_helpers.S.
I made the change in plat/arm/board/fvp/platform.mk by adding
lib/cpus/aarch64/cortex_a520.S in one of the FVP_CPU_LIBS and enabling the
ERRATA_A520_2938996, ERRATA_A520_2858100 and ERRATA_A520_2630792. These
changes helped me get past the TF-A and now i ' m seeing a crash inside
kernel in pci.
16.720973] pci-host-generic 40000000.pci: host bridge /pci@40000000
ranges:
[ 16.721375] pci-host-generic 40000000.pci: MEM
0x0050000000..0x005fffffff -> 0x0050000000
[ 16.722013] pci-host-generic 40000000.pci: ECAM at [mem
0x40000000-0x4fffffff] for [bus 00-ff]
[ 16.723128] pci-host-generic 40000000.pci: PCI host bridge to bus 0000:00
[ 16.723461] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 16.723761] pci_bus 0000:00: root bus resource [mem
0x50000000-0x5fffffff]
[ 16.724101] Internal error: synchronous external abort: 0000000096000010
[#1] SMP
[ 16.724216] Modules linked in:
[ 16.724302] CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted
6.15.0-rc7-dirty #12 PREEMPT
[ 16.724449] Hardware name: FVP Base RevC (DT)
[ 16.724531] pstate: 214000c9 (nzCv daIF +PAN -UAO -TCO +DIT -SSBS
BTYPE=--)
[ 16.724666] pc : pci_generic_config_read+0x38/0xb8
[ 16.724802] lr : pci_generic_config_read+0x24/0xb8
[ 16.724939] sp : ffff80008272b940
[ 16.725012] x29: ffff80008272b940 x28: 0000000000000000 x27:
ffff800081dc00b0
[ 16.725205] x26: ffff800081ec9060 x25: ffff800081ec9078 x24:
ffff80008266a9a0
[ 16.725401] x23: 0000000000000000 x22: ffff80008272b9f4 x21:
ffff000800fa8000
[ 16.725594] x20: ffff80008272b964 x19: 0000000000000004 x18:
0000000000000006
[ 16.725781] x17: 6666666666663478 x16: 302d303030303030 x15:
ffff800082edbbbf
[ 16.725980] x14: 0000000000000000 x13: 0000000000000000 x12:
0000000000000000
[ 16.726166] x11: 0000000000000001 x10: 3ea1f6d484b7e318 x9 :
69631046f78aed23
[ 16.726355] x8 : ffff000800169108 x7 : ffff800082250960 x6 :
00000000000000ff
[ 16.726547] x5 : 0000000000000000 x4 : 0000000000000000 x3 :
ffff800090000000
[ 16.726738] x2 : 0000000000000000 x1 : 0000000000000000 x0 :
ffff800090000000
Do i need to do enable somethign else in TF-A?
I tried adding :
pci: pci@40000000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
bus-range = <0x0 0xff>;
reg = <0x0 0x40000000 0x0 0x10000000>;
ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0
0x10000000>;
};
in plat/arm/board/fvp/fdts/fvp_soc_fw_config.dts but it does not help.
Also I see the kernel is not able to bring all the cpu's online:
[ 0.040364] smp: Bringing up secondary CPUs ...
[ 5.116993] CPU1: failed to come online
[ 5.117063] CPU1: failed in unknown state : 0x0
[ 10.266076] CPU2: failed to come online
[ 10.266152] CPU2: failed in unknown state : 0x0
[ 15.415178] CPU3: failed to come online
[ 15.415247] CPU3: failed in unknown state : 0x0
[ 15.421021] psci: failed to boot CPU4 (-22)
[ 15.421099] CPU4: failed to boot: -22
[ 15.425045] psci: failed to boot CPU5 (-22)
[ 15.425123] CPU5: failed to boot: -22
[ 15.429079] psci: failed to boot CPU6 (-22)
[ 15.429157] CPU6: failed to boot: -22
[ 15.433153] psci: failed to boot CPU7 (-22)
[ 15.433227] CPU7: failed to boot: -22
[ 15.433587] smp: Brought up 1 node, 1 CPU
[ 15.433672] SMP: Total of 1 processors activated.
[ 15.433746] CPU: All CPU(s) started at EL2
I’m still getting familiar with the codebase and community, so apologies if
this has already been addressed. I’d really appreciate any guidance or
pointers, and if this is a known issue or good for a first-time
contributor, I’d be happy to help.
Regards,
Shaunak
Hi folks,
We are planning on going live with the migration of the TF.org Open CI tomorrow, Friday 30th May, which will migrate Jenkins (ci.trustedfirmware.org) from on-premises to cloud-managed infrastructure. We expect a downtime of 2-4 hours beginning at 14:30 GMT+1, during which anything which interacts with Jenkins will be unavailable.
Please note that the Jenkins build history is not being transferred - if you have Gerrit changes in review with the Allow-CI+1/+2 label, you will need to retrigger the CI once migration is complete by reapplying the label.
We will send out a follow-up email once we have restored service availability.
Regards,
Chris
This event has been canceled with a note:
"Hi, Cancelling as no topic planned for this week. Regards, Olivier. "
TF-A Tech Forum
Thursday May 29, 2025 ⋅ 5pm – 6pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A
Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu,
78 occurrence(s)Please download and import the following iCalendar (.ics)
files to your calendar
system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics…
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(Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1
301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1
312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623
US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558
8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128
US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US•
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Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853
5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find
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