This event has been changed.
Title: TF-A Tech Forum
Agenda for Session on 27th January 2020Introduction of Arm CCA Context
ManagementSession Presented by: Manish Pandey, Soby Mathew and Zelalem
AwekeDetails: With the introduction of Arm CCA, the context management
library needs to manage the context for one more world (realm world). Since
the current context management library has evolved over time, some of
design principles need sharpening / re-defining to make it easier to manage
and make it less error-prone when managing the 3 worlds. The proposal lists
down the design principles and discusses about introduction of new CPU
Context for the root world (EL3). The refactor will increase the overall
robustness of EL3 firmware as it will enforce a design pattern in software
plus have a more predictable sysreg state during execution at EL3.We run an
open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
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Calendar: tf-a(a)lists.trustedfirmware.org
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Agenda for Session on 27th January 2020
* Introduction of Arm CCA Context Management
* Session Presented by: Manish Pandey, Soby Mathew and Zelalem Aweke
* Details: With the introduction of Arm CCA, the context management library needs to manage the context for one more world (realm world). Since the current context management library has evolved over time, some of design principles need sharpening / re-defining to make it easier to manage and make it less error-prone when managing the 3 worlds. The proposal lists down the design principles and discusses about introduction of new CPU Context for the root world (EL3). The refactor will increase the overall robustness of EL3 firmware as it will enforce a design pattern in software plus have a more predictable sysreg state during execution at EL3.
We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC.
Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/<https://www.google.com/url?q=https://www.trustedfirmware.org/meetings/tf-a-…>
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This event has been changed.
Title: TF-A Tech Forum
Agenda for Session on 27th January 2020introduction of Arm CCA Context
ManagementSession Presented by: Manish Pandy, Soby Mathew and Zelalem
AwekeDetails: With the introduction of Arm CCA, the context management
library needs to manage the context for one more world (realm world). Since
the current context management library has evolved over time, some of
design principles need sharpening / re-defining to make it easier to manage
and make it less error-prone when managing the 3 worlds. The proposal lists
down the design principles and discusses about introduction of new CPU
Context for the root world (EL3). The refactor will increase the overall
robustness of EL3 firmware as it will enforce a design pattern in software
plus have a more predictable sysreg state during execution at EL3.We run an
open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap
mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US
(San Jose)Dial by your location +1 646 558
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Toll-free 888 788 0099 US Toll-freeMeeting ID:
915 970 4974Find your local
number: https://zoom.us/u/ad27hc6t7h (changed)
When: Thu Jan 27, 2022 4pm – 5pm United Kingdom Time
Calendar: tf-a(a)lists.trustedfirmware.org
Who:
* Bill Fletcher - creator
* marek.bykowski(a)gmail.com
* okash.khawaja(a)gmail.com
* tf-a(a)lists.trustedfirmware.org
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Hello Everyone,
We have a proposal to refactor the Context management framework in TF-A and an RFC is pushed for review here: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13651 . The abstract of the RFC is given below:
With the introduction of Arm CCA, the context management library needs to manage the context for one more world (realm world). Since the current context management library has evolved over time, some of design principles need sharpening / re-defining to make it easier to manage and make it less error-prone when managing the 3 worlds. The proposal lists down the design principles and discusses about introduction of new CPU Context for the root world (EL3). The refactor will increase the overall robustness of EL3 firmware as it will enforce a design pattern in software plus have a more predictable sysreg state during execution at EL3.
The plus point here is that many of the design principles are already adhered to in one way or other in the current the implementation so much of the work can be done in an incremental fashion without much disruption. Along with @Zelalem Aweke<mailto:Zelalem.Aweke@arm.com> and @Manish Pandey2<mailto:Manish.Pandey2@arm.com>, we hope to discuss the this RFC and how this translates to code changes in TF-A during the Tech Forum this week.
Best Regards
Soby Mathew
Hi,
arm_validate_ns_entrypoint() in plat/arm/common/arm_pm.c check ARM_NS_DRAM1_BASE
and ARM_NS_DRAM2_BASE only, for some platform there are include more than two
non-secure dram areas.
It will bring dependencies between TF-A and physical memory space which can get
from uefi atfer memory initialization, if arm_validate_ns_entrypoint() include the
entire physical memory space.
In my mind, the kernel should guarantee the validity of entry point.
So why this check is need?
Thanks,
Ming
Hi,
I am running U-Boot 2022.01 on imx8mm-evk. If I build the NXP
vendor-based TF-A (imx_5.4.47_2.2.0) I am able to boot kernel 5.16
just fine.
However, if I use the upstream TF-A (v2.5 or v2.6), the kernel fails
to boot most of the attempts.
Peng, Jacky,
Could you please try booting kernel 5.16 + U-Boot 2022.01 built with TF-A v2.6?
What is missing in upstream TF-A to be able to boot kernel 5.16?
Thanks,
Fabio Estevam
Dear all,
(and may the new year be happy to you and your beloved)
In the course of evaluating the FW update flows for systems with FIP images, we identified the following requirements:
Req1:
The FIP image, or the components in the FIP, must have a version field. Each version field will be compared against the anti-rollback counter of the platform that the FIP or its component is bound to.
Req2:
We must be able to increment the FIP version field (though a FIP image FW update) without affecting the anti-rollback counter value. The anti-rollback counter should be incremented only for security updates upon explicit request.
Req3:
The version field should be present even if the FIP does not contain image certificates.
Currently the FIP carries a version field in the different certificates, the anti-rollback counters are updated every time the root certificate value increased. This is not flexible enough and does not allow trial/acceptance of updates.
Can we open a discussion on how to enhance the version/anti-rollback counter update in TF-A?
Best regards,
Etienne Carriere
ST Restricted
This event has been changed.
Title: TF-A Tech Forum
The Tech Forum this week will cover two discussion subjects:Hafnium Build
and Tooling Options. Discussion led by Olivier Deprez.Covering
recent changes to the Hafnium project that has neem announced on the
Hafnium mailing list
https://lists.trustedfirmware.org/archives/list/hafnium@lists.trustedfirmwa…
Update and Anti-Rollback VersioningDiscussion led by Manish Badarkhe
and Manish Pandey2An opportunity to discuss the recent email thread on
this topic on the TF-A mailing list.
https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…
run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap
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Toll-free 888 788 0099 US Toll-freeMeeting ID:
915 970 4974Find your local
number: https://zoom.us/u/ad27hc6t7h (changed)
When: Thu Jan 13, 2022 4pm – 5pm United Kingdom Time
Calendar: tf-a(a)lists.trustedfirmware.org
Who:
* Bill Fletcher - creator
* marek.bykowski(a)gmail.com
* okash.khawaja(a)gmail.com
* tf-a(a)lists.trustedfirmware.org
Event details:
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Hi TF-A committee,
We are trying to access to the MISRA C spreadsheet mentioned over here.
[cid:image001.jpg@01D806BE.A535F7C0]
https://developer.trustedfirmware.org/file/download/lamajxif3w7c4mpjeoo5/PH…
However, we are facing issue to open the spreadsheet and we are getting "Invalid Authorization".
[cid:image002.jpg@01D806BE.A535F7C0]
After we click on the "Continue", the website show Restricted File and we have no access permission.
[cid:image003.jpg@01D806BE.A535F7C0]
Thus, we would like to get your help to assist us on how to obtain the spreadsheet.
Hope to hear from you soon.
Thanks
Best Regards
JL Lim (Benjamin)
Hi all,
I am running FVP with 2CPUs, Cactus SP (SEL1), Hafnium (SEL2) and KVM VHE.
Sometimes I send the "FFA_MSG_SEND_DIRECT_REQ" smc call from KVM (I fill
0x8400006f in x0, then VMID and SP ID in x1, let x2 as 0). It says
assert failed, like this:
ASSERT: lib/el3_runtime/aarch64/context_mgmt.c:651
BACKTRACE: START: assert
0: EL3: 0x4005cac
1: EL3: 0x400323c
2: EL3: 0x400620c
3: EL3: 0x400e180
4: EL3: 0x4005a94
BACKTRACE: END: assert
After I check the bl31.dump, I notice that:
when services/std_svc/spmd/spmd_main.c sends the FFA
call (from NS to S) via "spmd_smc_forward(smc_fid, secure_origin,x1,
x2, x3, x4, handle)", it will go to
cm_el1_sysregs_context_restore(secure_state_out) and
cm_el2_sysregs_context_restore(secure_state_out), then it will assert
the cm_get_context(). it gets the NULL context, so assert failed.
Before the problem appeared, I have modified many codes on a dirty
TF-A v2.4 (commit hash is 0aa70f4c4c023ca58dea2d093d3c08c69b652113),
Hafnium and TF-A-TESTS. I also mail with Hafnium MailList, they
consider it can be a problem in EL3.
Such assert is NOT ALWAYS failed. I mean, maybe when I run FVP and
send "smc" now, it is failed. But when I shut down, run FVP, and send
the same instruction with the same parameter again, it is OK.
I want to know, what is the possible reasons for suddenly losing the
secure context. Can you give me some advice on debugging? e.g., where
should I check? Need I provide more info?
Sincerely,
Wang
Hi all,
I want to add some big data structures in BL31 (e.g., create a large
uint32_t array). Also, I reserve a secure memory space (assume it is
0xa000_0000 - 0xb000_0000) by configuring TZASC.
Now, the BL31 says
build/fvp/debug/bl31/bl31.elf section `.bss' will not fit in region `RAM'
aarch64-none-elf-ld: BL31 image has exceeded its limit.
aarch64-none-elf-ld: region `RAM' overflowed by 458752 bytes
It looks like that the previous RAM cannot hold my big data
structures. If I want to add my reserved region into RAM (so I may
allocate these data into the reserved region), what should I do?
Sincerely,
Wang
Hi,
Please allow me to add some more details. Also posting to the TF-A list, as all tf.org repositories are affected.
The root cause of this issue is OpenSSH dropping support for SHA-1 RSA signatures with the 8.8 release, and thus any OS (or git client) coming with a recent version is affected. I.e. the newest git for windows is affected too, and so are “top notch” Linux distributions like Arch.
For details see the “Potentially-incompatible changes” chapter here: https://www.openssh.com/releasenotes.html
As the above page states “Incompatibility is more likely when connecting to older SSH implementations…”, and thus a server-side update would eliminate the problem. Till that happens the page above list multiple client-side workarounds. (It is possible to amend the ssh config in a way that fixes all repositories.)
/George
From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Kevin Townsend via TF-M
Sent: December 15, 2021 13:06
To: Thomas Törnblom via TF-M <tf-m(a)lists.trustedfirmware.org>
Subject: [TF-M] Tip on cloning TF-M on OS X Monterey
I recently switched to a new MBP that ships with OS X Monterey, and on both 12.0 and 12.1 (released this week) git clone seems to be broken when you're using HTTP rather than SSH:
digital envelope routines:CRYPTO_internal:bad key length
In order to clone TF-M, I had to make the following changes.
1. Add these details to $HOME/.ssh/config (microbuilder being my github username, associated with my TF-M account):
Host trustedfirmware.org<http://trustedfirmware.org>
User microbuilder
Hostname review.trustedfirmware.org<http://review.trustedfirmware.org>
Port 29418
IdentityFile ~/.ssh/id_rsa
IdentitiesOnly yes
2. Then try to clone with:
$ git clone trustedfirmware.org:/TF-M/trusted-firmware-m.git
This fails, however, since it tries to clone tf-m-tests.git, so:
3. Edit lib/ext/tf-m-tests/fetch_repo.cmake, changing:
FetchContent_Declare(tfm_test_repo
GIT_REPOSITORY trustedfirmware.org:TF-M/tf-m-tests.git
# GIT_REPOSITORY https://git.trustedfirmware.org/TF-M/tf-m-tests.git
GIT_TAG ${TFM_TEST_REPO_VERSION}
GIT_PROGRESS TRUE
)
This let me at least clone TF-M until the issues with HTTP-based cloning are fixed.
Hope this is useful to someone else working on OS X natively.
Kevin
Hi,
On STM32MP1, we'd like BL2 to be agnostic of what BL32 is in the FIP.
It can be either OP-TEE or TF-A SP_min.
But on STM32MP1, SP_min needs a device tree file (TOS_FW_CONFIG_ID),
whereas OP-TEE doesn't use this separate DT image.
As TOS_FW_CONFIG_ID is in list of images to be loaded by BL2, we then
have a warning message in case OP-TEE is used:
WARNING: FCONF: Invalid config id 26
I'd like to silence this warning with this kind of patch:
diff --git a/lib/fconf/fconf_dyn_cfg_getter.c
b/lib/fconf/fconf_dyn_cfg_getter.c
index 25dd7f9eda..f7e9834c3b 100644
--- a/lib/fconf/fconf_dyn_cfg_getter.c
+++ b/lib/fconf/fconf_dyn_cfg_getter.c
@@ -51,7 +51,11 @@ struct dyn_cfg_dtb_info_t
*dyn_cfg_dtb_info_getter(unsigned int config_id)
}
}
- WARN("FCONF: Invalid config id %u\n", config_id);
+ if (config_id == TOS_FW_CONFIG_ID) {
+ VERBOSE("FCONF: No TOS_FW_CONFIG image\n");
+ } else {
+ WARN("FCONF: Invalid config id %u\n", config_id);
+ }
return NULL;
}
I can change the VERBOSE message to INFO.
Do you think it is OK if I push the patch?
Thanks,
Yann
I’m not sure if the cancellations have been sent from the trustedfirmware.org calendar system so confirming that they are cancelled to the list.
Next scheduled Tech Forum is 13th January 2022.
Joanna
Hi all,
I want to load a specific image in BL31. But when I call
load_auth_image(). It says
"in function `load_image':
trusted-firmware-a/common/bl_common.c:87: undefined reference to
`plat_get_image_source'"
Also, the io_read, io_size and etc. are undefined reference.
I find other BL files (bl1, bl2) will call the load_auth_image() in
their main functions or sub-functions. If I want to implement it on
BL31, what should I do? Should I modify the Makefile?
Sincerely,
Wang
Hi all,
We are pleased to announce the formal release of Trusted Firmware-A version 2.6, Trusted Firmware-A Tests version 2.6, Hafnium version 2.6 and TF-A OpenCI Scripts 2.6 Releases involving the tagging of multiple sub repositories.
These went live on 24th November 2021.
Notable Features of the Version 2.6 Release across repositories are as follows:
* v8-R64 Upstream support, trusted-boot (BL1) only
* RME patches (4 world support)
* Hunter & Hayes CPU support
* Demeter (Makalu ELP for Infra) CPU support
* ARM v9.0-A ETE V1.0
* ARM v9.1-A ETE V1.1
* Armv9 RME support
* Generic Firmware Update support
* Measured Boot Enhancements
* MPMM AMU support SME (Mortlach) for non-secure world (FEAT_SME)
* Security hardening LLVM/clang support.
* FF-A v1.1 notifications support.
* FF-A v1.1 interrupt handling support.
* S-EL0 partitions (through VHE in the secure world).
* SPM support for saving/restoring the normal world SVE live state.
* Build system update to LLVM/Clang 12.
* Updates to FF-A Setup and discovery.
* FF-A compliance fixes.
* Threat model introduced for SPMC at SEL2
* Eight new partner and Arm platforms support added
Please refer to the TF-A [1], Hafnium [2] and TF-A Tests [3] changelogs for the complete summary of changes the previous release.
The test plan and results [4] for the v2.6 release captures the release test activities.
TF-A [5], TF-A Test [6], Hafnium [7] and TF-A OpenCI Scripts [8] repositories are available
[1] https://trustedfirmware-a.readthedocs.io/en/v2.6/
[2] https://review.trustedfirmware.org/plugins/gitiles/hafnium/hafnium/+/HEAD/d…
[3] https://trustedfirmware-a-tests.readthedocs.io/en/v2.6/
[4] https://confluence.arm.com/display/BSGSoftware/TF-A+v2.6+Test+Plan+and+Resu…
[5] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tag/?h=v2.6
[6] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tag/?h=v2.6
[7] https://git.trustedfirmware.org/hafnium/hafnium.git/tag/?h=v2.6
[8] https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tag/?h=v2.6
Thanks & best regards,
[cid:image001.jpg@01D7E120.C34F0DA0]
Bipin Ravi | Principal Design Engineer
Bipin.Ravi(a)arm.com<mailto:Bipin.Ravi@arm.com> | Skype: Bipin.Ravi.ARM
Direct: +1-512-225 -1071 | Mobile: +1-214-212-0794
5707 Southwest Parkway, Suite 100, Austin, TX 78735
Hi.
I'm trying to run on our new platform Linux as BL33, preloaded to DDR.
currently simulated over QEMU.
I think that BL31 started BL33 in EL0, which cause problems:
QEMU outputs this message: (complete log below)
Exception return from AArch64 EL3 to AArch64 EL0 PC 0x800080000
What could I have done wrong in the configuration that caused it ?
What should I check ?
Thanks !
Ramon.
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.5(debug):v2.5-61-g84d7d6a30-dirty
NOTICE: BL1: Built : 14:53:02, Nov 21 2021
INFO: BL1: RAM 0x15500000 - 0x15513000
WARNING: BL1: neoverse_n1: CPU workaround for 1946160 was missing!
INFO: BL1: Loading BL2
INFO: Using mmap
INFO: Using FIP
INFO: Loading image id=1 at address 0x14300000
INFO: Image id=1 loaded: 0x14300000 - 0x143052d1
INFO: bl1_mem_layout->total_base = 0x14000000x
NOTICE: BL1: Booting BL2
INFO: Entry point address = 0x14300000
INFO: SPSR = 0x3c5
Exception return from AArch64 EL3 to AArch64 EL1 PC 0x14300000
INFO: BL1 inherited memory layout: 0x14000000 [size = 22020096]
NOTICE: BL2: v2.5(debug):v2.5-61-g84d7d6a30-dirty
NOTICE: BL2: Built : 14:53:02, Nov 21 2021
INFO: BL2: Skip loading image id 23
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: Using mmap
INFO: Using FIP
INFO: Loading image id=3 at address 0x800000000
INFO: Image id=3 loaded: 0x800000000 - 0x8000080a9
INFO: BL2: Skip loading image id 5
Taking exception 13 [Secure Monitor Call]
...from EL1 to EL3
...with ESR 0x17/0x5e000000
...with ELR 0x14302a04
...to EL3 PC 0x5400 PSTATE 0x3cd
NOTICE: BL1: Booting BL31
INFO: Entry point address = 0x800000000
INFO: SPSR = 0x3cd
Exception return from AArch64 EL3 to AArch64 EL3 PC 0x800000000
INFO: Boot BL33 from 0x800080000 for 0 Bytes
NOTICE: BL31: v2.5(debug):v2.5-61-g84d7d6a30-dirty
NOTICE: BL31: Built : 14:53:04, Nov 21 2021
INFO: GICv3 without legacy support detected.
INFO: ARM GICv3 driver initialized in EL3
INFO: Maximum SPI INTID supported: 63
INFO: BL31: Initializing runtime services
WARNING: BL31: neoverse_n1: CPU workaround for 1946160 was missing!
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x800080000
INFO: SPSR = 0x0
Exception return from AArch64 EL3 to AArch64 EL0 PC 0x800080000
Taking exception 1 [Undefined Instruction]
...from EL0 to EL1
...with ESR 0x18/0x6232c061
...with ELR 0x8000b7164
...to EL1 PC 0x400 PSTATE 0x3c5
Taking exception 4 [Data Abort]
This event has been canceled with this note:
"Cancelling TF-A Tech Forum this week as the team have nothing to present.
We expect to have a topic for December 2nd."
Title: TF-A Tech Forum
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
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Hi Pali,
My understanding of the errata reporting mechanism is that some erratas are always checked during CPU boot. If the corresponding MACRO (ERRATA_A53_*) is disabled, then the ERRATA_MISSING code is reported.
I would be concerned if the CPU is affected by the errata. If the errata needs to be enabled, the fix would be to enable the ERRATA_A53_* from the platform makefile.
Hope this helps.
-Varun
-----Original Message-----
From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Pali Rohár via TF-A
Sent: Wednesday, July 7, 2021 9:11 PM
To: Olivier Deprez <Olivier.Deprez(a)arm.com>; Bipin Ravi <Bipin.Ravi(a)arm.com>; tf-a(a)lists.trustedfirmware.org
Cc: Konstantin Porotchkin <kostap(a)marvell.com>; Marek Behún <marek.behun(a)nic.cz>
Subject: Re: [TF-A] Missing CPU workaround warning message
External email: Use caution opening links or attachments
Hello! Could somebody from TF-A helps with these two topics? I would really need to know if "missing errata warnings" debug message is some critical and needs to be fixed (and how?) or it is just a debug message and therefore should not be a warning...
On Monday 28 June 2021 17:11:18 Pali Rohár wrote:
> On Monday 28 June 2021 14:03:06 Olivier Deprez wrote:
> > Hi,
> >
> > Is the question strictly related to this platform not implementing the mentioned errata (for which a platform change can be emitted)?
>
> Hello! The first question is if this is an issue that CPU workaround
> is missing. And if yes (which seems to be) how big issue it is? And
> how to resolve it?
>
> > Or is it more generally that those "missing errata warnings" are not printed in release mode?
> > Assuming the latter, it looks to me it is the integrator mistake to not include the appropriate mitigations at development phase (hence while using debug mode for building TF-A).
> > Then when the device is deployed (hence most often built for release mode), if this message is printed it is an indication for a malicious agent that such attack vector through mis-implemented errata is possible. So the consequence is possibly even worst than just "missing" to include the errata.
> >
> > Other TF-Aers (Bipin?) may have other opinions?
>
> And this is a second question. If missing CPU workaround is an issue,
> should not be it printed also in release build?
>
> Also I see that in release builds are omitted not only messages about
> missing CPU workarounds, but basically _all_ warning messages. But
> notice messages are _not_ omitted. Which seems strange as in most
> cases notice message has lower priority than warning message.
>
> >
> > Regards,
> > Olivier.
> >
> > ________________________________________
> > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of
> > Pali Rohár via TF-A <tf-a(a)lists.trustedfirmware.org>
> > Sent: 28 June 2021 15:36
> > To: tf-a(a)lists.trustedfirmware.org
> > Cc: Konstantin Porotchkin; Marek Behún
> > Subject: [TF-A] Missing CPU workaround warning message
> >
> > Hello! If TF-A for Marvell Armada 3720 platform is compiled in debug
> > mode then at runtime it prints following warning messages:
> >
> > WARNING: BL1: cortex_a53: CPU workaround for 855873 was missing!
> > WARNING: BL1: cortex_a53: CPU workaround for 1530924 was missing!
> >
> > These lines are not printed in non-debug mode. It is an issue?
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Thanks, Soby. I agree that this needs to be re-evaluated for platforms. I think we should introduce an option to disable them, if required.
We plan to try some more experiments and hopefully remove the locks at least for Tegra platforms.
Looking forward to the elaborate answer.
From: Soby Mathew <Soby.Mathew(a)arm.com>
Sent: Tuesday, 2 November 2021 10:18 AM
To: Varun Wadekar <vwadekar(a)nvidia.com>; Manish Pandey2 <Manish.Pandey2(a)arm.com>; Dan Handley <Dan.Handley(a)arm.com>
Cc: Joanna Farley <Joanna.Farley(a)arm.com>; Matteo Carlini <Matteo.Carlini(a)arm.com>
Subject: RE: PSCI lock contention
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Hi Varun,
The short answer is that the locks are used to differentiate the last-CPU-to-suspend and similarly first-CPU-to-powerup at a given power domain level. Now, recent CPU features like DynamIQ means that we don't need to do this differentiation upto cluster level which TF-A hasn't optimized for yet AFAICS. I am happy to elaborate further , but could you please send the query to the TF-A mailing list as I would prefer this discussion to happen in the open if possible.
Best Regards
Soby Mathew
From: Varun Wadekar <vwadekar(a)nvidia.com<mailto:vwadekar@nvidia.com>>
Sent: 01 November 2021 20:14
To: Soby Mathew <Soby.Mathew(a)arm.com<mailto:Soby.Mathew@arm.com>>; Manish Pandey2 <Manish.Pandey2(a)arm.com<mailto:Manish.Pandey2@arm.com>>; Dan Handley <Dan.Handley(a)arm.com<mailto:Dan.Handley@arm.com>>
Cc: Joanna Farley <Joanna.Farley(a)arm.com<mailto:Joanna.Farley@arm.com>>; Matteo Carlini <Matteo.Carlini(a)arm.com<mailto:Matteo.Carlini@arm.com>>
Subject: PSCI lock contention
Hi,
We were trying performance benchmarking for CPU_SUSPEND on Tegra platforms. We take all CPU cores to CPU_SUSPEND and then wake them up with IPI - all at once and in serial order. From the numbers, we see that the CPUs powering up later take more time than the first one. We have narrowed the most time consumed to the PSCI locks - documented at docs/perf/psci-performance-juno.rst.
Can you please help me understand why these locks were added? As a quick experiment we tried the same benchmarking *without* the locks and the firmware does not blow up, but I would like to understand the impact from the analysis on Juno (docs/perf/psci-performance-juno.rst)
Happy to hop on a call to discuss further.
Thanks.
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TF-A Community,
Just a reminder we are looking to freeze the tree for release activities starting Monday.
Thanks
Joanna
From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Joanna Farley via TF-A <tf-a(a)lists.trustedfirmware.org>
Reply to: Joanna Farley <Joanna.Farley(a)arm.com>
Date: Monday, 1 November 2021 at 12:41
To: Joanna Farley via TF-A <tf-a(a)lists.trustedfirmware.org>
Subject: [TF-A] Trusted Firmware-A v2.6 release activities in November
TF-A Community,
This is to notify that we are planning to target the Trusted Firmware-A 2.6 release during the fourth week of Nov 2021 as part of the regular 6 month cadence.
The aim is to consolidate all TF-A work since the 2.5 release. As part of this, a release candidate tag will be created and release activities will commence from 15th November 2021 across all TF-A repositories.
Essentially we will not merge any major enhancements from this date until the release is made.
Please ensure any patches desired to make the 2.6 release are submitted in good time to be complete by 12th November 2021.
Any major enhancement patches still open after that date will not be merged until after the release.
This will involve the various repositories making up the broader TF-A project including the TF-A mainline, TF-A Tests, Hafnium, TF-A CI Scripts and TF-A CI Jobs.
We will endeavour minimise the disruption on patch merging and complete release activities ASAP after we start.
Thanks
Joanna
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* marek.bykowski(a)gmail.com
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