[AMD Official Use Only - AMD Internal Distribution Only]
Hello Maintainers,
We are observing a reproducible runtime regression on the ZynqMP (Cortex-A53) platform after enabling LTO (ENABLED_LTO=1) and merging the changes from the topic NUMA_AWARE_PER_CPU into our integration branch (https://github.com/ARM-software/arm-trusted-firmware/commit/7303319b3823e9e…).
Summary of the issue
1. Baseline behavior
* Platform: ZynqMP (Cortex-A53)
* Configuration: ENABLED_LTO=1
* Without NUMA_AWARE_PER_CPU: Linux boots and runs stably
* After merging NUMA_AWARE_PER_CPU, Linux boots but hangs during runtime
* During the hang, CPUs are observed to unexpectedly re-enter EL3
* Re-entry into EL3 should not occur during normal Linux runtime execution and strongly suggests corruption or mismanagement of PSCI and/or per-CPU state(arm-trusted-firmware/lib/per_cpu/aarch64/per_cpu_asm.S at master * ARM-software/arm-trusted-firmware<https://github.com/ARM-software/arm-trusted-firmware/blob/master/lib/per_cp…>)
* Reverting the NUMA_AWARE_PER_CPU changes restores stable Linux execution
* The issue is reproducible only when NUMA_AWARE_PER_CPU is present
* This clearly identifies NUMA_AWARE_PER_CPU as the regression source
2. Suspect with LTO
* With NUMA_AWARE_PER_CPU enabled, LTO breaks the per-CPU base calculation
* BL31 contains hand-written assembly that relies on linker-script symbols (e.g., per-CPU section boundaries)
* Under LTO, symbol placement and retention are no longer guaranteed in the same way, leading to incorrect per-CPU base computation
* This results in corrupted per-CPU data and subsequent erroneous PSCI suspend behavior (EL3 re-entry)
3. CPU idle dependency
* The following kernel configuration options are enabled:
* CONFIG_CPU_IDLE=y
* CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
* CONFIG_CPU_IDLE_GOV_MENU=y
* CONFIG_DT_IDLE_STATES=y
* This further suggests the issue is triggered during CPU idle / suspend-resume paths, where correct per-CPU state handling is critical
Based on the above:
* This is specific to NUMA_AWARE_PER_CPU combined with LTO
* The failure mode points to per-CPU base calculation and PSCI state corruption
* Reverting NUMA_AWARE_PER_CPU fully restores stability on ZynqMP
We wanted to report this issue upstream and seek guidance on:
* Whether NUMA_AWARE_PER_CPU is expected to be LTO-safe on platforms relying on linker-defined per-CPU sections
* Or if additional constraints / fixes are required for platforms like ZynqMP
We are happy to provide further logs, configuration details, or help to fixes.
Regards,
Prasad Kummari
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TF-A Tech Forum Jan 22nd 10.00am -Part II Scaling Hafnium for advanced
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Hi, As follow up to the last session on Nov 13th 2025 [1], a new TF-A Tech
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Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 501137: Integer handling issues (CONSTANT_EXPRESSION_RESULT)
/common/runtime_svc.c: 261 in handler_sync_exception()
_____________________________________________________________________________________________
*** CID 501137: Integer handling issues (CONSTANT_EXPRESSION_RESULT)
/common/runtime_svc.c: 261 in handler_sync_exception()
255 /* advance the PC to continue after the instruction */
256 write_ctx_reg(state, CTX_ELR_EL3, read_ctx_reg(state, CTX_ELR_EL3) + 4);
257 } /* otherwise return to the trapping instruction (repeating it) */
258 return;
259 /* If FFH Support then try to handle lower EL EA exceptions. */
260 } else if ((exc_class == EC_IABORT_LOWER_EL || exc_class == EC_DABORT_LOWER_EL)
>>> CID 501137: Integer handling issues (CONSTANT_EXPRESSION_RESULT)
>>> "state->ctx_regs[0U /* 0U >> 3U */] | (8UL /* 1UL << 3 */)" is always 1/true regardless of the values of its operand. This occurs as the logical second operand of "&&".
261 && (read_ctx_reg(state, CTX_SCR_EL3) | SCR_EA_BIT)) {
262 #if FFH_SUPPORT
263 /*
264 * Check for Uncontainable error type. If so, route to the
265 * platform fatal error handler rather than the generic EA one.
266 */
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…
+ TF-A list
________________________________
From: Olivier Deprez
Sent: 05 January 2026 15:11
To: Taehoon Kim <gth1919(a)adtek.co.kr>
Cc: Raef Coles <Raef.Coles(a)arm.com>; Jackson Cooper-Driver <Jackson.Cooper-Driver(a)arm.com>; Nishant Sharma <Nishant.Sharma(a)arm.com>; Rohit Mathew <Rohit.Mathew(a)arm.com>; Manish Pandey2 <Manish.Pandey2(a)arm.com>; Manish Badarkhe <Manish.Badarkhe(a)arm.com>
Subject: Questions about Chain-of-Trust and RSE Connectivity
Hi Taehoon Kim,
We seem to experience an issue with the mailing list where messages are not properly dispatched. I reproduced your initial email sent Dec 18th 2025 below and Cced relevant folks just in case.
Regards,
Olivier.
____________________________________________________________
Hello, I'm firmware developer for RD-V3-R1 chipset.
I have developed our firmware based on Neoverse Reference Platform RD-INFRA-2025.07.03, but I have also kept an eye on the code to ensure we remain in step with the latest release.
While inquiring on the TF-M forum to update the TF-M code, I also developed a query regarding the TF-A section.
Re: Several Questions related to RSE Provisioning - TF-M - lists.trustedfirmware.org<https://lists.trustedfirmware.org/archives/list/tf-m@lists.trustedfirmware.…>
This link includes that RSE API codes are removed in the SotA TF-A codes.
I check this in the TF-A commit.
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/46314
I was already aware that this API was not used outside of test code. However, I would like to know the reason why that code was removed, beyond the simple fact that it was not being used. Is it possible that Chain-of-Trust is established in whole firmware stack from RSE ROM to AP BL33 bootloader, without RSE assist? If possible, what does TF-A rely upon as the basis for trust in establishing the Root of Trust?
Our team believed that CoT was established on the premise of the RSE API, and was therefore designing to ensure the trustworthiness of the entire firmware using that code. However, we recognise that to use the latest version of the code, we must abandon that belief and design in a different manner. Before the new version of RD-INFRA is released, we intend to resolve this internally as a team.
Should you feel the scope of the question extends beyond what is typically addressed in the forum, please do not hesitate to let us know.
Thank you for reading this mail.
Best Regard,
Taehoon Kim
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
2 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 500810: Incorrect expression (SIZEOF_MISMATCH)
/contrib/libeventlog/src/event_log.c: 394 in event_log_write_specid_event()
_____________________________________________________________________________________________
*** CID 500810: Incorrect expression (SIZEOF_MISMATCH)
/contrib/libeventlog/src/event_log.c: 394 in event_log_write_specid_event()
388 }
389
390 /* TCG_EfiSpecIdEvent.VendorInfo */
391 if (vendor_info_size > 0) {
392 vendor_info_ptr =
393 (tcg_vendor_info_t
>>> CID 500810: Incorrect expression (SIZEOF_MISMATCH)
>>> Adding "4UL /* sizeof (id_event_algorithm_size_t) */ * algo_count" to pointer "spec_id_ptr->digest_size" of type "id_event_algorithm_size_t *" is suspicious because adding an integral value to this pointer automatically scales that value by the size, 4 bytes, of the pointed-to type, "id_event_algorithm_size_t". Most likely, the multiplication by "sizeof (id_event_algorithm_size_t)" in this expression is extraneous and should be eliminated.
394 *)(spec_id_ptr->digest_size +
395 sizeof(id_event_algorithm_size_t) *
396 algo_count);
397
398 vendor_info_ptr->vendor_info_size = vendor_info_size;
399
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…
Hello, I'm firmware developer for RD-V3-R1 chipset.
I have developed our firmware based on Neoverse Reference Platform RD-INFRA-2025.07.03, but I have also kept an eye on the code to ensure we remain in step with the latest release.
While inquiring on the TF-M forum to update the TF-M code, I also developed a query regarding the TF-A section.
Re: Several Questions related to RSE Provisioning - TF-M - lists.trustedfirmware.org
This link includes that RSE API codes are removed in the SotA TF-A codes.
I check this in the TF-A commit.
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/46314
I was already aware that this API was not used outside of test code. However, I would like to know the reason why that code was removed, beyond the simple fact that it was not being used. Is it possible that Chain-of-Trust is established in whole firmware stack from RSE ROM to AP BL33 bootloader, without RSE assist? If possible, what does TF-A rely upon as the basis for trust in establishing the Root of Trust?
Our team believed that CoT was established on the premise of the RSE API, and was therefore designing to ensure the trustworthiness of the entire firmware using that code. However, we recognise that to use the latest version of the code, we must abandon that belief and design in a different manner. Before the new version of RD-INFRA is released, we intend to resolve this internally as a team.
Should you feel the scope of the question extends beyond what is typically addressed in the forum, please do not hesitate to let us know.
Thank you for reading this mail.
Best Regard,
Taehoon Kim
Please have a look at following patch, where on our platform we try to maintain single image of TFA (for custom CPU and Cortex A55)
Cortex A55 does not have Secure EL2 implemented, while on the other hand our custom CPU has secure EL2 (and we run Hafnium there)
On Cortex A55 ARM AEM model:
write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
the context was set before as
u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
and setting ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT causes crash since secure EL2 is not implemented.
resulting into following patch which resolves the issue. seeking feedback/discussion if I can post it to upstream TFA,
let me know if I am missing something here.
lib/el3_runtime: set NS bit if secure el2 is not implemented
before setting icc_sre_el2 set NS bit for non-secure context so that
the ICC_SRE_DIB_BIT and ICC_SRE_DFB_BIT are preserved
Signed-off-by: Oza Pawandeep <quic_poza(a)quicinc.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index e31255868..5100f2f00 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1411,7 +1411,18 @@ static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t securit
u_register_t scr_el3 = read_scr_el3();
#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
- write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
+ if (is_feat_sel2_supported()) {
+ write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
+ } else {
+ write_scr_el3(scr_el3 | SCR_NS_BIT);
+ isb();
+
+ write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
+
+ write_scr_el3(scr_el3);
+ isb();
+ }
+
#else
write_scr_el3(scr_el3 | SCR_NS_BIT);
isb();
Regards,
Oza.
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Hi, On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will
present a design update on TF-RMM Live Firmware Activation: This
presentation describes the revised TF-RMM Low-VA MMU and
global-runtime-data design required to support Live Firmware Activation
(LFA). Compared to the earlier approach (outlined in the TFA Tech Forum
session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings
and per-platform handcrafted Low-VA contexts, the new design is driven by
several changes in RMM specification: RMM must now support runtime
mapping/unmapping of PAs for RMM objects like struct granule , reuse those
dynamic mappings across LFA transitions. These PAs can come either from NS
world at runtime or EL3 reservation from RMM carveout. In order to migrate
Stage 1 dynamic mappings across LFA instances, RMM needs to reduce
dependence on platform-specific MMU setup, and provide a structured
framework for allocating, versioning and migrating global runtime data. The
Stage 1 Low-VA is therefore split into static and dynamic regions managed
by the common xlat layer. The detailed design is captured in the TF-RMM
wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial
design presented in the TFA Tech Forum session on 12-Jun-2025 [1] : [1]
Previous LFA discussion:
https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations [2]
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act…
Regards, Olivier.
TF-A Tech Forum
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Hi,
On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will present a design update on TF-RMM Live Firmware Activation:
This presentation describes the revised TF-RMM Low-VA MMU and global-runtime-data design required to support Live Firmware Activation (LFA). Compared to the earlier approach (outlined in the TFA Tech Forum session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings and per-platform handcrafted Low-VA contexts, the new design is driven by several changes in RMM specification: RMM must now support runtime mapping/unmapping of PAs for RMM objects like struct granule , reuse those dynamic mappings across LFA transitions. These PAs can come either from NS world at runtime or EL3 reservation from RMM carveout.
In order to migrate Stage 1 dynamic mappings across LFA instances, RMM needs to reduce dependence on platform-specific MMU setup, and provide a structured framework for allocating, versioning and migrating global runtime data. The Stage 1 Low-VA is therefore split into static and dynamic regions managed by the common xlat layer. The detailed design is captured in the TF-RMM wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial design presented in the TFA Tech Forum session on 12-Jun-2025 [1] :
[1] Previous LFA discussion: https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations
[2] https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act…
Regards,
Olivier.
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Hi
I'm looking for a suggestion for a reliable place to store a small boot
index for PSA Firmware Update. SNVS LPGPRs looked promising, but NXP’s
guidance is thin and we don’t keep the battery-backed LP domain alive, so
those values won’t survive many power cycles. Are there better options on
LS1028A? Would using the user RAM byte in our external I2C RTC make sense?
Or perhaps should I store it on eMMC? (we don't use raw NOR/NAND flash).
That RTC I mentioned is already accessed in both U-Boot and Linux, so I’m
wary of conflicts but can try it if you think it’s viable.
Any suggestions would be much appreciated.
Best regards
Patryk
Hi,
I have a sort of generic Arm architecture question that's not directly
related to TF-A (other than that TF-A controls some of the registers
involved in this decision), but I'm hoping that one of the experts
here can still help me out or at least refer me to someone who can.
I'm trying to figure out how exception routing for SError aborts works
in EL2. Specifically, I have a bootloader (BL33) running in NS-EL2 and
I want the "simple" setup that it manages all its own exceptions, the
same way that an OS kernel normally manages all exceptions at EL1. I
assumed that I could achieve that simply by installing exception
handlers, unmasking all exceptions in PSTATE, and leaving all the
special trap feature bits in the MSRs at 0 (disabled).
This seems to work for synchronous exceptions and external aborts, but
not for SErrors. Looking at the architecture reference manual
(revision L.b), table D1-14 in section D1.3.6.3 (page D1-6114), I can
see that my case is represented by the first line (all special trap
bits 0), which shows that SErrors caused by EL0 and EL1 would be
routed to EL1 as expected (though even when PSTATE.A is 1 which seems
odd?), but SErrors caused by EL2 will get ignored and remain pending
(with no regard to PSTATE.A). Instead, the "default" behavior I expect
(aborts get routed to the EL that caused them if PSTATE.A is 0) seems
to require me to enable SCTLR_EL2.NMEA. But if you're looking at the
description of SCTLR_EL2.NMEA, it says that it controls whether
PSTATE.A masks SError exceptions at EL2 (and that if it is 0, SError
exceptions are not taken at EL2 if PSTATE.A == 1). Doesn't that imply
that SError exceptions *are* taken at EL2 if PSTATE.A == 0? What does
a control that seems to be about trapping masked aborts from a lower
EL have to do with unmasked aborts from my current EL?
Basically, I think what I'm asking is: is that table really correct as
printed (some behavior we've observed seems to indicate it is), and if
so, why? Why do SError exceptions seem to behave differently by
default in EL1 and EL2 (in regards to unmasked exceptions taken from
the same exception level)? Why does the PSTATE.A bit only seem to
apply to EL0 and EL1, not EL2 and EL3, even for exceptions taken from
the same level, when this peculiarity seems to not be mentioned
anywhere else in the manual? Why do SError exceptions get treated so
differently from external aborts in EL2/EL3, when in EL1 they seem to
mostly count as the same? Is the current description of the NMEA bit
in the SCTLR_EL2 register documentation really accurate, if it also
seems to make fundamental changes to cases not really mentioned in
that description? Is there any way for EL2 to only handle its own
SError exceptions without interfering with EL1's exception handling
when FEAT_DoubleFault2 is not implemented (other than flipping
HCR_EL2.AMO on every EL2 entry/exit)? And am I the only one who finds
this all incredibly inconsistent and confusing?
I feel like I'm missing some critical insight in how you were meant to
think about this to make it make sense, would appreciate any help in
that regard!
Thanks,
Julius
Hi,
We are pleased to announce the formal release of Trusted Firmware-A version 2.14 bundle of project deliverables.
This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium, TF-RMM, Trusted Services, and TF-A OpenCI scripts/jobs components.
These went live on Nov, 24th 2025.
Please find tag references and change logs at the end of this email.
Many thanks to the trustedfirmware.org community for the active engagement in delivering this release!
Notable features of the release version 2.14 are as follows:
TF-A/EL3
* New architectural features support: FEAT_FGWTE3, FEAT_IDTE3, FEAT_RME_GPC2, FEAT_AIE, FEAT_CPA2, FEAT_MPAM_PE_BW_CTRL, FEAT_PFAR, FEAT_RME_GDI.
*
Live Firmware Activation: base support enabling TF-RMM LFA, added RMM MEM RESERVE ABI.
*
Armv9 CPU power down abandon support
* GICv5 driver permitting normal world kernel boot
* GIC720-AE support added
* Per-cpu framework supporting NUMA platforms
* SMCCC SoC name support (SMCCC v1.6 SMCCC_ARCH_SOC_ID)
* SPMD: added FF-A v1.3 FFA_NS_RES_INFO_GET, FFA_ABORT interfaces
* EL3 SPMC: add multiple UUIDs support, TPM event log delivered by HOB list, FFA_MEM_RETRIEVE_REQ from hypervisor
* RME: FEAT_D128 for realm world, SMCCC_ARCH_FEATURE_AVAILABILITY
* Platforms: RD-Aspen added, updates to Arm FVP/Juno, AMD Versal Gen2, Intel, MT8189, MT8196, i.MX94, i.MX95, S32G274A, QTI Kodiak, Renesas R-Car, STM32MP1, STM32MP2, STM32MP21, STM32MP25, Xilinx Versal, ZynqMP
Boot flow
* Transfer list and event log libraries now offered as shared libraries consumed as submodules by TF-A.
* Update to mbedTLS 3.6.5
* Various PSA FWU improvements, namely BL2 in a dedicated FIP, GPT-corruption notifications to BL32, and expanded FWU tests.
Errata/Security mitigations (CPU/GIC)
* New CPU support: Arm Lumex C1, Dionysus, Caddo/Veymont, Venom.
* Added close to 30 new CPU errata across multiple processor families, based on the latest SDEN updates.
Hafnium/SPM (S-EL2)
* FF-A v1.3 early adoption
* FFA_NS_RES_INFO_GET ABI added
* Partition lifecycle support: new states, abort handling. Pre-requisite to secure partitions live firmware activation.
* Notifications support refactored with per-vCPU notifications removed.
* Multi-GIC configuration supporting complex topologies.
* Shrinkwrap used at core of Hafnium testing infrastructure.
TF-RMM (R-EL2)
* RMM v1.1 Planes support
* PMU, timer, GIC ownership transfer.
* Support for FEAT_S1POE/S1PIE, FEAT_S2POE/S2PIE
* RMM v1.1 Memory Encryption Contexts (MEC) support
* Realm Device Assignment
* RMM v1.1. ALP12 base Device Assignment support
* RMI VDEV ABIs, PDEV life cycle, root port IDE key programming, SPDM client as EL0 app.
* Improved ID registers trapping leveraging SMCCC ARCH_FEATURE_AVAILABILITY, in light of future FEAT_IDTE3 support.
* Additional architectural support: FEAT_TCR2, FEAT_D128, single-copy atomics,
TF-A Tests
*
RME: DA and PCIe, Planes, MEC
*
SPM/FF-A
* Bumped support o FF-A v1.3
* FFA_ABORT ABI
* Deprecated per-vCPU notifications.
* FWU: added negative testing (invalid image size, corrupted ROTPK)
* GICv5 support added
* Arm architecture tests
* FEAT_TCR2 (for RME) , FEAT_IDTE3, FEAT_MPAM_PE_BW_CTRL, FEAT_EBEP, FEAT_AIE, FEAT_PFAR
* SMCCC_ARCH_SOC_ID
* SMCCC_ARCH_FEATURE_AVAILABILITY
* Fuzzing: added SMC fuzzer documentation
* Basic LFA framework tests
* Platforms updates: AMD/Xilinx, Arm FVP, Corstone-1000
Trusted Services
* RD-Aspen platform support added.
* EFI ESRT handling in FWU Proxy (supporting Corstone1000 platform).
* Block Storage service threat modelling.
Release tags across repositories:
https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r…https://git.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags…https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-ci-scripts/+/refs/t…https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-job-configs/+/refs/…https://git.trustedfirmware.org/plugins/gitiles/hafnium/hafnium/+/refs/tags…https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-ci-scripts/+/ref…https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-job-configs/+/re…https://git.trustedfirmware.org/plugins/gitiles/TF-RMM/tf-rmm/+/refs/tags/t…https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/…
Change logs:
https://trustedfirmware-a.readthedocs.io/en/v2.14.0/change-log.html#id1https://trustedfirmware-a-tests.readthedocs.io/en/v2.14.0/change-log.html#v…https://hafnium.readthedocs.io/en/v2.14.0/change-log.html#id1https://tf-rmm.readthedocs.io/en/tf-rmm-v0.8.0/about/change-log.html#v0-8-0https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/…
Regards,
Olivier.
Hi,
This is a one off session for a partner to present coming improvements related to Hafnium project.
Apologies for the meeting time not accommodating people in US timezones.
We'll record the session and publish in the TF-A tech forum page as usual.
Regards,
Olivier.
________________________________
From: Google Calendar <calendar-notification(a)google.com> on behalf of Olivier Deprez via Hafnium <hafnium(a)lists.trustedfirmware.org>
Sent: 07 November 2025 09:13
To: hafnium(a)lists.trustedfirmware.org <hafnium(a)lists.trustedfirmware.org>
Subject: [Hafnium] Invitation: TF-A Tech Forum - Hafnium future looking improvements @ Thu Nov 13, 2025 12pm - 1pm (GMT+1) (hafnium(a)lists.trustedfirmware.org)
TF-A Tech Forum - Hafnium future looking improvements
Thursday Nov 13, 2025 ⋅ 12pm – 1pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
Hi, This is a one off session for a partner to present coming improvements
related to Hafnium project. Apologies for the meeting time not
accommodating people in US timezones. We'll record the session and publish
in the TF-A tech forum page as usual. Regards,Olivier.Trusted Firmware is
inviting you to a scheduled Zoom meeting.Please download and import the
following iCalendar (.ics) files to your calendar
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