Hi All,
SCR_EL3.EA define whether to route External Abort and SError Interrupt to EL3 or EL2/1. ATF have a compile time flag to HANDLE_EA_EL3_FIRST_NS to program SCR_EL3.EA.
Below text from ATF documentation.
- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError
Interrupts, resulting from errors in NS world, will be always trapped in
EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions
will be trapped in the current exception level (or in EL1 if the current
exception level is EL0).
Have question related to forwarding of these errors when External Abort and SError Interrupt are routed to EL3.
In this case will ATF forward Asynchronous SError Interrupt to Linux via RAS?
Thanks
-Bharat
It is observed that functions like macros like NOTICE, WARN and assert are present in the Trusted Firmware-A code. MISRA-C standard treats these as violations. shall we take these as deviation? please suggest.
TFA Guidelines recommends using logging macros. So can we make deviations or need to change the MACRO into function.
Hello,
It is observed that device tree functions are present under lib/libfdt/... in Trusted Firmware-A code, but this device tree are not present in symbol table and also if we remove this device tree functions in code, board was successfully booting. However, while doing Coverity build to fix MISRA-C violations getting violations from this device tree code.
So, is it possible to leave those violations please suggest? And when it will be enabled, please suggest.
Thanks & Regards
Nithin G
Hi Everyone,
I have cancelled the TF-A techforum for latter today as we have no topic scheduled to be discussed.
Calendar cancellations have been sent.
Apologies for the late notification.
Joanna
This event has been canceled with a note:
"Cancelling as we have no topics for today. Apologies for the late
cancellation. Joanna"
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Hi
I ported TF-A and OPTEE on multi-core SoC, and I checked that xtest passed
on CPU0 without failure. However, I'm failing in secondary CPU boot, and
I'd like to get some help.
I'm using ARMv8, and I'm using spintable as CPU enable method (not using
PSCI FW). TF-A is in EL3.
What I did ...
1. I released secondary CPU reset from bl31_early_platform_setup2() during
primary CPU cold booting
- set secondary CPU's RVBAR to bl31_entrypoint
- release secondary CPU reset
2. I implemeneted plat_secondary_cold_boot_setup(), which is spining until
linux kernel updates cpu-release-addr. Once linux kernel updates
cpu-release-addr, then it changes EL to EL1 and jumps to
secondary_startup() in linux
3. But secondary core goes to panic. It seems to happen when linux invokes
optee_probe()
Should I initialize some contexts (e.g. optee ..)? If so, where should I
implement the corresponding codes? I'm wondering if I'm missing something,
and I'd like to get some advice
Thanks,
--Bin
This event has been canceled with a note:
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Hello,
Trusted Firmware-A LTS version 2.8.8 is now available. This release contains the following patches.
* ec3fafa24 fix(cpus): workaround for Neoverse V2 erratum 2801372
The readthedocs update can be found at https://trustedfirmware-a.readthedocs.io/en/lts-v2.8/change-log.html.
Thanks.
Hi Boyan,
Some questions about erratum in TF-A:
1 Why workaround's flag is 0? In my mind, all flag should be 1 because there is func to check cpu revisions,
such as check_errata_2326639.
43438ad1a patch:
+ERRATA_N2_2326639 ?=0
2 After e444763d6(shorten errata flag defines) patch, introduce CPU_FLAG_LIST,
Is the workaround's flag change to 1?
e444763d6 patch:
-ERRATA_N2_2326639 ?=0
+CPU_FLAG_LIST += ERRATA_N2_2326639
Regards,
Ming
Hi All,
I wanted to let you know that next Thursday, July 27th, the TF-A Tech Forum
will be hosting a presentation on OpenCI and MISRA presented by Paul
Sokolovski of Linaro and Roberto Bagnara from Bugseng. MISRA is being
enabled on both TF-A and TF-M in OpenCI, so sending this out to both lists
since users in both domains may be interested in the session.
Meeting time and dial up info can be found in the TF community calendar
located here: https://www.trustedfirmware.org/meetings/
Best Regards,
Don Harbin
TrustedFirmware Community Manager
don.harbin(a)linaro.org
Hi,
Typically, BL31 runs in SRAM which tends to be limited. As we add
support for newer architectural features e.g. CCA, general features
and standards, the size of BL31 image will grow and become harder to
fit in most SRAMs.
This email is to share ideas on how to address this problem.
A simple approach will be to identify parts of NOBITS ELF sections of
BL31 which can be moved out to DRAM. Since NOBITS sections aren't part
of the file image, loading and authentication code doesn't have to
change. The challenge will be to come up with some criteria to help
decide what kind of buffers can be kept in DRAM vs SRAM.
Other ideas are also welcome. Please share your thoughts.
Thanks,
Okash
Hi,
We have two topics for the upcoming TF-A Tech Forum on Jul, 13th:
Certificate signer-id retrieval - Manish Badarkhe
* Quick recap
* Authentication Mechanism
* Role of public key
* What is signer ID and its usage?
* Design of signer ID retrieval for attestation
Updates to EL3 vector entry path to cater for async EA(SError) exceptions - Manish Pandey
*
Description of error synchronization during EL3 entry.
* Go through the implementation of handling of these errors in EL3 for Firmware First Handling (FFH) scenarios.
* Reflecting it back in Kernel First Handling (KFH) scenario.
* Description of the test scenarios introduced.
Regards,
Olivier.
________________________________
From: Trusted Firmware Public Meetings
Sent: 14 June 2020 19:21
To: Trusted Firmware Public Meetings <linaro.org_havjv2figrh5egaiurb229pd8c(a)group.calendar.google.com>; tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org>
Subject: [TF-A] Invitation: TF-A Tech Forum @ Every 2 weeks from 16:00 to 17:00 on Thursday (BST) (tf-a(a)lists.trustedfirmware.org)
When: 13 July 2023 17:00-18:00.
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Hi Manish,
I'll answer on behalf of Benjamin and Sieu because I think they are offline now.
I reached out to these guys privately this morning and they said they will post patches to fix these defects.
Cheers,
Sandrine
Hi All,
It has happened in the past that developers have posted patches for review, but have been unable to respond to the comments on those patches for a long time and hence, maintainers pitched in and abandoned the patches in such cases.
I created a patch [1] to make this official because the coding-review guidelines didn't mention it today. I would appreciate your help in reviewing this patch. Please let us know if you disagree about this approach. If you'd like, we can discuss this upcoming tech-forum.
[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/21848
Thanks,
Manish Badarkhe
This event has been canceled with a note:
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FYI to all TF dev teams leveraging Open CI.
Best regards,
Don
---------- Forwarded message ---------
From: Glen Valante via Tf-openci-triage <
tf-openci-triage(a)lists.trustedfirmware.org>
Date: Fri, 23 Jun 2023 at 08:41
Subject: [Tf-openci-triage] FYI; Cambridge Lab Down
To: tf-openci-triage(a)lists.trustedfirmware.org <
tf-openci-triage(a)lists.trustedfirmware.org>
Hello All;
FYI; the Cambridge lab took a serious power hit and is down. They are
scrambling to get things back up, but it may take all weekend.
Expect LAVA failures and other strange results.
Thanks;
-g
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This event has been updated with a note:
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Changed: description
TF-A Tech Forum
Thursday Jul 27, 2023 ⋅ 4pm – 5pm
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Topic:MISRA testing in the OpenCI with BUGSENG's ECLAIR Software
Verification PlatformPresenters:Roberto Bagnara (BUGSENG) and Paul
Sokolovskyy (Linaro)Summary:Overview of MISRA C, BUGSENG's ECLAIR Software
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the OpenCIContinuous Integration System for the TF-A and TF-M
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Hi Varun,
* for platforms with SPMD_SPM_AT_SEL2=1. These platforms already use EHF for servicing RAS interrupts today.
Can you please have a look at https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16047 ?
and https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16047/6/docs…
The model, by the FF-A specification, is to permit G0 interrupts to trap to EL3 when NWd runs.
A G0 interrupt is routed to a SP through the SPMD/SPMC by the use of EL3-SP direct messages:
https://review.trustedfirmware.org/q/topic:%22el3_direct_msg%22+(status:ope…
When SEL1/0 runs, G0 interrupts are first trapped to SEL2 and forwarded to EL3 by the FFA_EL3_INTR_HANDLE ABI.
I appreciate the legacy capability to let G0 interrupts trap to EL3 while SWd runs is not possible/recommended with this design.
This might indeed break earlier implementations; would it make sense aligning SW stacks to the latest of the FF-A spec recommendations?
I let Raghu chime in if need be.
Regards,
Olivier.
________________________________
From: Varun Wadekar via TF-A <tf-a(a)lists.trustedfirmware.org>
Sent: 06 June 2023 13:12
To: TF-A Mailing List <tf-a(a)lists.trustedfirmware.org>
Subject: [TF-A] EHF and SPMD G0 interrupt handling issues
Hi,
We are in the process of upgrading the downstream TF-A to v2.9 for platforms with SPMD_SPM_AT_SEL2=1. These platforms already use EHF for servicing RAS interrupts today.
I noticed that v2.9 has added G0 interrupt handling support to the SPMD. But I think the SPMD support still needs some work as it does not play nicely with EHF.
I have found the following issues with the implementation.
1. SPMD and EHF both register handlers for G0 interrupts. But the interrupt management framework only allows one handler for INTR_TYPE_EL3.
2. The RAS framework still uses EHF and the SPMD interrupt handler breaks that functionality.
3. The SPMD handler calls into the platform which does not have any means to invoke the RAS interrupt handler.
IMO, we should make SPMD a client of the EHF instead of creating yet another way for interrupt handling. For now, I register SPMD's G0 interrupt handler only if EL3_EXCEPTION_HANDLING=0, as a workaround.
Thoughts?