Please have a look at following patch, where on our platform we try to maintain single image of TFA (for custom CPU and Cortex A55)
Cortex A55 does not have Secure EL2 implemented, while on the other hand our custom CPU has secure EL2 (and we run Hafnium there)
On Cortex A55 ARM AEM model:
write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
the context was set before as
u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
and setting ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT causes crash since secure EL2 is not implemented.
resulting into following patch which resolves the issue. seeking feedback/discussion if I can post it to upstream TFA,
let me know if I am missing something here.
lib/el3_runtime: set NS bit if secure el2 is not implemented
before setting icc_sre_el2 set NS bit for non-secure context so that
the ICC_SRE_DIB_BIT and ICC_SRE_DFB_BIT are preserved
Signed-off-by: Oza Pawandeep <quic_poza(a)quicinc.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index e31255868..5100f2f00 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1411,7 +1411,18 @@ static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t securit
u_register_t scr_el3 = read_scr_el3();
#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
- write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
+ if (is_feat_sel2_supported()) {
+ write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
+ } else {
+ write_scr_el3(scr_el3 | SCR_NS_BIT);
+ isb();
+
+ write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
+
+ write_scr_el3(scr_el3);
+ isb();
+ }
+
#else
write_scr_el3(scr_el3 | SCR_NS_BIT);
isb();
Regards,
Oza.
This event has been canceled with a note:
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Hi, On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will
present a design update on TF-RMM Live Firmware Activation: This
presentation describes the revised TF-RMM Low-VA MMU and
global-runtime-data design required to support Live Firmware Activation
(LFA). Compared to the earlier approach (outlined in the TFA Tech Forum
session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings
and per-platform handcrafted Low-VA contexts, the new design is driven by
several changes in RMM specification: RMM must now support runtime
mapping/unmapping of PAs for RMM objects like struct granule , reuse those
dynamic mappings across LFA transitions. These PAs can come either from NS
world at runtime or EL3 reservation from RMM carveout. In order to migrate
Stage 1 dynamic mappings across LFA instances, RMM needs to reduce
dependence on platform-specific MMU setup, and provide a structured
framework for allocating, versioning and migrating global runtime data. The
Stage 1 Low-VA is therefore split into static and dynamic regions managed
by the common xlat layer. The detailed design is captured in the TF-RMM
wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial
design presented in the TFA Tech Forum session on 12-Jun-2025 [1] : [1]
Previous LFA discussion:
https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations [2]
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act…
Regards, Olivier.
TF-A Tech Forum
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Hi,
On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will present a design update on TF-RMM Live Firmware Activation:
This presentation describes the revised TF-RMM Low-VA MMU and global-runtime-data design required to support Live Firmware Activation (LFA). Compared to the earlier approach (outlined in the TFA Tech Forum session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings and per-platform handcrafted Low-VA contexts, the new design is driven by several changes in RMM specification: RMM must now support runtime mapping/unmapping of PAs for RMM objects like struct granule , reuse those dynamic mappings across LFA transitions. These PAs can come either from NS world at runtime or EL3 reservation from RMM carveout.
In order to migrate Stage 1 dynamic mappings across LFA instances, RMM needs to reduce dependence on platform-specific MMU setup, and provide a structured framework for allocating, versioning and migrating global runtime data. The Stage 1 Low-VA is therefore split into static and dynamic regions managed by the common xlat layer. The detailed design is captured in the TF-RMM wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial design presented in the TFA Tech Forum session on 12-Jun-2025 [1] :
[1] Previous LFA discussion: https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations
[2] https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act…
Regards,
Olivier.
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Hi
I'm looking for a suggestion for a reliable place to store a small boot
index for PSA Firmware Update. SNVS LPGPRs looked promising, but NXP’s
guidance is thin and we don’t keep the battery-backed LP domain alive, so
those values won’t survive many power cycles. Are there better options on
LS1028A? Would using the user RAM byte in our external I2C RTC make sense?
Or perhaps should I store it on eMMC? (we don't use raw NOR/NAND flash).
That RTC I mentioned is already accessed in both U-Boot and Linux, so I’m
wary of conflicts but can try it if you think it’s viable.
Any suggestions would be much appreciated.
Best regards
Patryk
Hi,
I have a sort of generic Arm architecture question that's not directly
related to TF-A (other than that TF-A controls some of the registers
involved in this decision), but I'm hoping that one of the experts
here can still help me out or at least refer me to someone who can.
I'm trying to figure out how exception routing for SError aborts works
in EL2. Specifically, I have a bootloader (BL33) running in NS-EL2 and
I want the "simple" setup that it manages all its own exceptions, the
same way that an OS kernel normally manages all exceptions at EL1. I
assumed that I could achieve that simply by installing exception
handlers, unmasking all exceptions in PSTATE, and leaving all the
special trap feature bits in the MSRs at 0 (disabled).
This seems to work for synchronous exceptions and external aborts, but
not for SErrors. Looking at the architecture reference manual
(revision L.b), table D1-14 in section D1.3.6.3 (page D1-6114), I can
see that my case is represented by the first line (all special trap
bits 0), which shows that SErrors caused by EL0 and EL1 would be
routed to EL1 as expected (though even when PSTATE.A is 1 which seems
odd?), but SErrors caused by EL2 will get ignored and remain pending
(with no regard to PSTATE.A). Instead, the "default" behavior I expect
(aborts get routed to the EL that caused them if PSTATE.A is 0) seems
to require me to enable SCTLR_EL2.NMEA. But if you're looking at the
description of SCTLR_EL2.NMEA, it says that it controls whether
PSTATE.A masks SError exceptions at EL2 (and that if it is 0, SError
exceptions are not taken at EL2 if PSTATE.A == 1). Doesn't that imply
that SError exceptions *are* taken at EL2 if PSTATE.A == 0? What does
a control that seems to be about trapping masked aborts from a lower
EL have to do with unmasked aborts from my current EL?
Basically, I think what I'm asking is: is that table really correct as
printed (some behavior we've observed seems to indicate it is), and if
so, why? Why do SError exceptions seem to behave differently by
default in EL1 and EL2 (in regards to unmasked exceptions taken from
the same exception level)? Why does the PSTATE.A bit only seem to
apply to EL0 and EL1, not EL2 and EL3, even for exceptions taken from
the same level, when this peculiarity seems to not be mentioned
anywhere else in the manual? Why do SError exceptions get treated so
differently from external aborts in EL2/EL3, when in EL1 they seem to
mostly count as the same? Is the current description of the NMEA bit
in the SCTLR_EL2 register documentation really accurate, if it also
seems to make fundamental changes to cases not really mentioned in
that description? Is there any way for EL2 to only handle its own
SError exceptions without interfering with EL1's exception handling
when FEAT_DoubleFault2 is not implemented (other than flipping
HCR_EL2.AMO on every EL2 entry/exit)? And am I the only one who finds
this all incredibly inconsistent and confusing?
I feel like I'm missing some critical insight in how you were meant to
think about this to make it make sense, would appreciate any help in
that regard!
Thanks,
Julius
Hi,
We are pleased to announce the formal release of Trusted Firmware-A version 2.14 bundle of project deliverables.
This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium, TF-RMM, Trusted Services, and TF-A OpenCI scripts/jobs components.
These went live on Nov, 24th 2025.
Please find tag references and change logs at the end of this email.
Many thanks to the trustedfirmware.org community for the active engagement in delivering this release!
Notable features of the release version 2.14 are as follows:
TF-A/EL3
* New architectural features support: FEAT_FGWTE3, FEAT_IDTE3, FEAT_RME_GPC2, FEAT_AIE, FEAT_CPA2, FEAT_MPAM_PE_BW_CTRL, FEAT_PFAR, FEAT_RME_GDI.
*
Live Firmware Activation: base support enabling TF-RMM LFA, added RMM MEM RESERVE ABI.
*
Armv9 CPU power down abandon support
* GICv5 driver permitting normal world kernel boot
* GIC720-AE support added
* Per-cpu framework supporting NUMA platforms
* SMCCC SoC name support (SMCCC v1.6 SMCCC_ARCH_SOC_ID)
* SPMD: added FF-A v1.3 FFA_NS_RES_INFO_GET, FFA_ABORT interfaces
* EL3 SPMC: add multiple UUIDs support, TPM event log delivered by HOB list, FFA_MEM_RETRIEVE_REQ from hypervisor
* RME: FEAT_D128 for realm world, SMCCC_ARCH_FEATURE_AVAILABILITY
* Platforms: RD-Aspen added, updates to Arm FVP/Juno, AMD Versal Gen2, Intel, MT8189, MT8196, i.MX94, i.MX95, S32G274A, QTI Kodiak, Renesas R-Car, STM32MP1, STM32MP2, STM32MP21, STM32MP25, Xilinx Versal, ZynqMP
Boot flow
* Transfer list and event log libraries now offered as shared libraries consumed as submodules by TF-A.
* Update to mbedTLS 3.6.5
* Various PSA FWU improvements, namely BL2 in a dedicated FIP, GPT-corruption notifications to BL32, and expanded FWU tests.
Errata/Security mitigations (CPU/GIC)
* New CPU support: Arm Lumex C1, Dionysus, Caddo/Veymont, Venom.
* Added close to 30 new CPU errata across multiple processor families, based on the latest SDEN updates.
Hafnium/SPM (S-EL2)
* FF-A v1.3 early adoption
* FFA_NS_RES_INFO_GET ABI added
* Partition lifecycle support: new states, abort handling. Pre-requisite to secure partitions live firmware activation.
* Notifications support refactored with per-vCPU notifications removed.
* Multi-GIC configuration supporting complex topologies.
* Shrinkwrap used at core of Hafnium testing infrastructure.
TF-RMM (R-EL2)
* RMM v1.1 Planes support
* PMU, timer, GIC ownership transfer.
* Support for FEAT_S1POE/S1PIE, FEAT_S2POE/S2PIE
* RMM v1.1 Memory Encryption Contexts (MEC) support
* Realm Device Assignment
* RMM v1.1. ALP12 base Device Assignment support
* RMI VDEV ABIs, PDEV life cycle, root port IDE key programming, SPDM client as EL0 app.
* Improved ID registers trapping leveraging SMCCC ARCH_FEATURE_AVAILABILITY, in light of future FEAT_IDTE3 support.
* Additional architectural support: FEAT_TCR2, FEAT_D128, single-copy atomics,
TF-A Tests
*
RME: DA and PCIe, Planes, MEC
*
SPM/FF-A
* Bumped support o FF-A v1.3
* FFA_ABORT ABI
* Deprecated per-vCPU notifications.
* FWU: added negative testing (invalid image size, corrupted ROTPK)
* GICv5 support added
* Arm architecture tests
* FEAT_TCR2 (for RME) , FEAT_IDTE3, FEAT_MPAM_PE_BW_CTRL, FEAT_EBEP, FEAT_AIE, FEAT_PFAR
* SMCCC_ARCH_SOC_ID
* SMCCC_ARCH_FEATURE_AVAILABILITY
* Fuzzing: added SMC fuzzer documentation
* Basic LFA framework tests
* Platforms updates: AMD/Xilinx, Arm FVP, Corstone-1000
Trusted Services
* RD-Aspen platform support added.
* EFI ESRT handling in FWU Proxy (supporting Corstone1000 platform).
* Block Storage service threat modelling.
Release tags across repositories:
https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r…https://git.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags…https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-ci-scripts/+/refs/t…https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-job-configs/+/refs/…https://git.trustedfirmware.org/plugins/gitiles/hafnium/hafnium/+/refs/tags…https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-ci-scripts/+/ref…https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-job-configs/+/re…https://git.trustedfirmware.org/plugins/gitiles/TF-RMM/tf-rmm/+/refs/tags/t…https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/…
Change logs:
https://trustedfirmware-a.readthedocs.io/en/v2.14.0/change-log.html#id1https://trustedfirmware-a-tests.readthedocs.io/en/v2.14.0/change-log.html#v…https://hafnium.readthedocs.io/en/v2.14.0/change-log.html#id1https://tf-rmm.readthedocs.io/en/tf-rmm-v0.8.0/about/change-log.html#v0-8-0https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/…
Regards,
Olivier.
Hi,
This is a one off session for a partner to present coming improvements related to Hafnium project.
Apologies for the meeting time not accommodating people in US timezones.
We'll record the session and publish in the TF-A tech forum page as usual.
Regards,
Olivier.
________________________________
From: Google Calendar <calendar-notification(a)google.com> on behalf of Olivier Deprez via Hafnium <hafnium(a)lists.trustedfirmware.org>
Sent: 07 November 2025 09:13
To: hafnium(a)lists.trustedfirmware.org <hafnium(a)lists.trustedfirmware.org>
Subject: [Hafnium] Invitation: TF-A Tech Forum - Hafnium future looking improvements @ Thu Nov 13, 2025 12pm - 1pm (GMT+1) (hafnium(a)lists.trustedfirmware.org)
TF-A Tech Forum - Hafnium future looking improvements
Thursday Nov 13, 2025 ⋅ 12pm – 1pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
Hi, This is a one off session for a partner to present coming improvements
related to Hafnium project. Apologies for the meeting time not
accommodating people in US timezones. We'll record the session and publish
in the TF-A tech forum page as usual. Regards,Olivier.Trusted Firmware is
inviting you to a scheduled Zoom meeting.Please download and import the
following iCalendar (.ics) files to your calendar
system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics…
Zoom
Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting
ID: 935 5786 3987Passcode: 939141---One tap
mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US
(Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1
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312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623
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8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128
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833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US
Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853
5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find
your local number: https://linaro-org.zoom.us/u/adoz9mILli
Reply for hafnium(a)lists.trustedfirmware.org and view more details
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Your attendance is optional.
~~//~~
Invitation from Google Calendar: https://calendar.google.com/calendar/
You are receiving this email because you are an attendee on the event.
Forwarding this invitation could allow any recipient to send a response to
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To unsubscribe send an email to hafnium-leave(a)lists.trustedfirmware.org
All,
Please be aware that today we have published our AI policy with Guidance on
AI-assisted contributions.
See the full details here: https://www.trustedfirmware.org/aipolicy/
Should you have any questions feel free to raise them.
Thanks,
Shaun
Community Manager
Hi All,
The next release of the Firmware-A bundle of projects tagged v2.12 has an expected code freeze date of Nov, 8th 2024.
Refer to the release cadence section from TF-A documentation (https://trustedfirmware-a.readthedocs.io/en/latest/about/release-informatio…).
Closing out the release takes around 6-10 working days after the code freeze.
v2.12 release preparation tasks start from now.
We want to ensure that planned feature patches for the release are submitted in good time for the review process to conclude.
As a kind recommendation and a matter of sharing CI resources, please launch CI jobs with care e.g.:
-For simple platform, docs changes, or one liners, use Allow-CI+1 label (no need for a full Allow-CI+2 run).
-For large patch stacks use Allow-CI+2 at top of the patch stack (and if required few individual Allow+CI+1 labels in the middle of the patch stack).
-Carefully analyze results and fix the change if required, before launching new jobs on the same change.
-If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not added as a gerrit comment on the patch right away please be patient as under heavy load CI jobs can be queued and in extreme conditions it can be over an hour before the Build start notice is issued. Issuing another Allow-CI+1 or Allow-CI+2 label will just result in an additional job being queued.
--
Thanks,
Govindraj R
Hi,
This issue was raised long time ago but unfortunately never got fixed/merged.
It may be ok restoring the change and progress it:
Https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/11002<https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/11002>
Https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…<https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…>
https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…
On a related note, I hope you saw the deprecation notice:
https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…
Regards,
Olivier.
________________________________
From: Sureshkumar Ponnusamy <sponnusamy(a)microsoft.com>
Sent: 11 November 2025 05:46
To: David Daney <daviddaney(a)microsoft.com>; tf-a-owner(a)lists.trustedfirmware.org <tf-a-owner(a)lists.trustedfirmware.org>
Cc: Giri Mudusuru <girimudusuru(a)microsoft.com>; Kun Qin <Kun.Qin(a)microsoft.com>
Subject: RE: Question about SPM-MM SMC function ids
Yes, the problem is in comparing logic and masks used.
From: David Daney <daviddaney(a)microsoft.com>
Sent: Monday, November 10, 2025 7:38 PM
To: Sureshkumar Ponnusamy <sponnusamy(a)microsoft.com>; tf-a-owner(a)lists.trustedfirmware.org
Cc: Giri Mudusuru <girimudusuru(a)microsoft.com>; Kun Qin <Kun.Qin(a)microsoft.com>
Subject: Re: Question about SPM-MM SMC function ids
According to the DEN0060A specification the only values used are:
MM_VERSION: 0x8400 0040
MM_COMMUNICATE: 0x8400 0041/0xC400 0041
These don't overlap with the TRNG function IDs defined in DEN0098
David.
________________________________
From: Sureshkumar Ponnusamy <sponnusamy(a)microsoft.com<mailto:sponnusamy@microsoft.com>>
Sent: Monday, November 10, 2025 7:32 PM
To: tf-a-owner(a)lists.trustedfirmware.org<mailto:tf-a-owner@lists.trustedfirmware.org> <tf-a-owner(a)lists.trustedfirmware.org<mailto:tf-a-owner@lists.trustedfirmware.org>>
Cc: Giri Mudusuru <girimudusuru(a)microsoft.com<mailto:girimudusuru@microsoft.com>>; David Daney <daviddaney(a)microsoft.com<mailto:daviddaney@microsoft.com>>; Kun Qin <Kun.Qin(a)microsoft.com<mailto:Kun.Qin@microsoft.com>>
Subject: Question about SPM-MM SMC function ids
Hi Manish, Levi Yun , TF-A community ,
I am facing an issue when enabling SPM-MM feature and it looks like there is a minor issue with the SMC ID range check.
When SPM-MM is enabled, I cannot use the TRNG SMC services.
/* These macros are used to identify SPM-MM calls using the SMC function ID */
#define SPM_MM_FID_MASK U(0xffff)
#define SPM_MM_FID_MIN_VALUE U(0x40)
#define SPM_MM_FID_MAX_VALUE U(0x7f)
#define is_spm_mm_fid(_fid) \
((((_fid) & SPM_MM_FID_MASK) >= SPM_MM_FID_MIN_VALUE) && \
(((_fid) & SPM_MM_FID_MASK) <= SPM_MM_FID_MAX_VALUE))
Here, the SPM-MM SMC ID range spans from 0x40 to 0x7F, which overlaps with the TRNG SMC service IDs:
/* SMC function IDs for TRNG queries */
#define ARM_TRNG_VERSION U(0x84000050)
#define ARM_TRNG_FEATURES U(0x84000051)
#define ARM_TRNG_GET_UUID U(0x84000052)
#define ARM_TRNG_RND32 U(0x84000053)
#define ARM_TRNG_RND64 U(0xC4000053)
Could you please clarify the rationale behind including the TRNG SMC IDs within the SPM-MM ID range? If this overlap was unintentional, we have to fix it.
Looking forward to your insights and feedback on this matter.
Thanks
Suresh
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 493457: Control flow issues (UNREACHABLE)
/plat/arm/board/fvp/fvp_spmd_logical_sp.c: 37 in fvp_get_partition_info()
_____________________________________________________________________________________________
*** CID 493457: Control flow issues (UNREACHABLE)
/plat/arm/board/fvp/fvp_spmd_logical_sp.c: 37 in fvp_get_partition_info()
31 * SPM.
32 *
33 * TODO: Integrate this helper function for a new anticipated feature.
34 */
35 return;
36
>>> CID 493457: Control flow issues (UNREACHABLE)
>>> This code cannot be reached: "struct ffa_value ret = {0UL};".
37 struct ffa_value ret = { 0 };
38 uint32_t target_uuid[4] = { 0 };
39 static struct ffa_partition_info_v1_1
40 part_info[SPMD_LP_MAX_SUPPORTED_SP] = { 0 };
41
42 uint16_t num_partitions = 0;
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…
TF-A Tech Forum - Hafnium future looking improvements
Thursday Nov 13, 2025 ⋅ 12pm – 1pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
Hi, This is a one off session for a partner to present coming improvements
related to Hafnium project. Apologies for the meeting time not
accommodating people in US timezones. We'll record the session and publish
in the TF-A tech forum page as usual. Regards,Olivier.Trusted Firmware is
inviting you to a scheduled Zoom meeting.Please download and import the
following iCalendar (.ics) files to your calendar
system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics…
Zoom
Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting
ID: 935 5786 3987Passcode: 939141---One tap
mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US
(Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1
301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1
312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623
US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558
8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128
US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US•
833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US
Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853
5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find
your local number: https://linaro-org.zoom.us/u/adoz9mILli
Reply for tf-a(a)lists.trustedfirmware.org and view more details
https://calendar.google.com/calendar/event?action=VIEW&eid=MDdmMGs0NjBkcW5q…
Your attendance is optional.
~~//~~
Invitation from Google Calendar: https://calendar.google.com/calendar/
You are receiving this email because you are an attendee on the event.
Forwarding this invitation could allow any recipient to send a response to
the organizer, be added to the guest list, invite others regardless of
their own invitation status, or modify your RSVP.
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