Hi all,
This email is to inform the community that support for OpenSSL 1.x is planned to be deprecated going forward. TF-A v2.15 will be the last release for which OpenSSL 1.x receives full support.
The primary reason for this change is that OpenSSL 1.1.1 reached end-of-life in September 2023, and OpenSSL 1.0.2 reached end-of-life significantly earlier. The OpenSSL project now recommends migration to OpenSSL 3.x for ongoing security updates, maintenance and feature development.
While OpenSSL offers commercial extended support for some legacy releases, the resulting patch sets are not generally available to the wider open-source community. As a result, TF-A maintainers and contributors cannot reasonably test, validate or debug against these versions. Supporting software versions that are not publicly available creates practical challenges for CI coverage, issue reproduction and long-term maintenance.
For these reasons, OpenSSL 3.x will become the supported OpenSSL version for TF-A.
To be clear, this change does not mean that TF-A will intentionally remove OpenSSL 1.x compatibility or deliberately break existing users. Existing compatibility code will remain in place where practical. However, after TF-A v2.15:
* OpenSSL 1.x will no longer be a supported configuration.
* CI testing will not cover OpenSSL 1.x.
* Bug reports affecting only OpenSSL 1.x may not be investigated.
* New features and maintenance changes will not be required to preserve OpenSSL 1.x compatibility.
* Patches to retain compatibility may be accepted on a best-effort basis, but no guarantees will be provided.
Users are therefore strongly encouraged to migrate their build environments to OpenSSL 3.x.
OpenSSL 3.x is the actively maintained upstream release series and provides ongoing security support, public availability of fixes, improved maintainability, and alignment with the direction of the OpenSSL project. Adopting OpenSSL 3.x also ensures that TF-A can be developed and tested against versions that are available to all maintainers and contributors.
Comments are welcome.
Regards,
Matthew
Hi everyone,
I am sending this email to all tf.org project mailing lists to ensure all maintainers are aware and on board regarding this matter. If you have any concerns or questions, please reply on tf.org Discord #general channel, where I'll create a thread, as I think it will be much easier than dealing with cross-mailing lists emails.
Background
When a security vulnerability is discovered in one of the trustedfirmware.org projects, it is common to request a "Common Vulnerabilities and Exposures" (CVE) number. This number uniquely references the issue, which can then be searched in the vulnerability databases. One of these databases is NIST's "National Vulnerability Database" (NVD): https://nvd.nist.gov<https://nvd.nist.gov/vuln/detail/CVE-2023-51712>
Entering a specific CVE number in NVD search engine will allow you to easily find the details of a specific issue, for example:
https://nvd.nist.gov/vuln/detail/CVE-2023-51712
However, sometimes one is not looking for a specific CVE number but rather wants to list all known vulnerabilities affecting a particular project. For this, one can use the Common Platform Enumerations (CPE) search engine:
https://nvd.nist.gov/products/cpe/search
CPE is a structured naming scheme that includes information like the vendor name, the project name, the version / tag, and so on.
See https://nvd.nist.gov/products/cpe for more details.
So for example, https://nvd.nist.gov/vuln/detail/CVE-2023-51712 referenced above has the following CPE:
cpe:2.3:o:arm:trusted_firmware-m:*:*:*:*:*:*:*:*
This basically means
*
CPE version 2.3 is in use
*
'o is the type of project, in this case it stands for Operating Systems (which is probably the closest match for low-level code like TF-M)
*
'arm' is the vendor (that is wrong, see below)
*
'trusted_firmware-m' is the project name,
Problem statement
It appears that CPEs used in NVD to reference vulnerabilities in tf.org projects differ a lot across projects. For some projects, there's even multiple of them. Sometimes the vendor is "arm", sometimes it's "linaro", or something else.
Some of the TF-A and MbedTLS maintainers have initiated discussions with NVD to get this simplified and unified, but it would make sense to align other tf.org projects as well.
Proposal
CPE naming rules are that the vendor name should the parent organization of the project. Thus the proposal would be for all tf.org projects to use "trustedfirmware" as the vendor name in their CPE.
For example:
cpe:2.3:o:trustedfirmware:trusted_firmware-m:*:*:*:*:*:*:*:*
cpe:2.3:a:trustedfirmware:mbed_tls:*:*:*:*:*:*:*:*
We're only proposing to change the vendor name here ; each project is then free to choose how they want the project name or the type of software project they want to encode there.
Thanks for reading,
Best regards,
Sandrine Afsa
Hi,
I would suggest looking into the platform ports:
https://trustedfirmware-a.readthedocs.io/en/latest/plat/arm/fvp/fvp-specifi…https://trustedfirmware-a.readthedocs.io/en/latest/plat/rpi3.html#build-ins… RPI3_DIRECT_LINUX_BOOT
https://trustedfirmware-a.readthedocs.io/en/latest/plat/qemu.html#qemu-virt… ARM_LINUX_KERNEL_AS_BL33
Regards,
Olivier.
________________________________
From: Joita Mitra <joita.m(a)delopt.co.in>
Sent: 11 June 2026 09:19
To: tf-a-owner(a)lists.trustedfirmware.org <tf-a-owner(a)lists.trustedfirmware.org>
Subject: Guidance on direct Linux boot from TF-A (bypassing U-Boot) on ARM64
Hi,
I am working on an RZ/G2L based platform and exploring the possibility of booting Linux directly from TF-A without using U-Boot as BL33.
Current boot flow:
BL2 -> BL31 -> U-Boot (BL33) -> Linux
Target boot flow:
BL2 -> BL31 -> Linux
I have been studying the TF-A image loading framework, including:
* desc_image_load.h
* bl2_image_load_v2.c
* bl2_plat_mem_params_desc.c
* bl31_main.c
* bl31_prepare_next_image_entry()
My understanding is that BL2 loads images according to the image descriptors and passes entry point information to BL31 through the BL33 descriptor.
I modified the BL33 descriptor to point to the Linux kernel entry address instead of U-Boot and attempted to transfer execution directly to Linux from BL31.
However, Linux does not start successfully, which suggests that additional preparation normally performed by U-Boot may be missing.
I would appreciate guidance on the following:
1. Is using the BL33 descriptor to describe the Linux kernel the correct architectural approach when bypassing U-Boot?
2. How should the Linux kernel Image and DTB be loaded from BL2?
* Should Linux be treated as BL33?
* Should the DTB be loaded as a separate image descriptor?
* Is there an existing TF-A mechanism intended for this use case?
3. Which TF-A components are typically modified to support direct Linux boot?
* BL2 image loading descriptors?
* BL31 handoff logic?
* Platform-specific image loading code?
4. Are there any reference implementations or platforms in TF-A that directly boot Linux without U-Boot?
5. Are there any ARM64 Linux boot protocol requirements that TF-A must satisfy before transferring control to Linux?
Any guidance or examples would be greatly appreciated.
Thank you.
[cid:19da2837-2e52-4337-8b03-1cc393171495]<http://www.delopt.co.in/>
Joita Mitra
Embedded Software Engineer
[cid:7d7fa5b9-a852-48ac-a797-7ed0723558b3] +91-7985313796
Fortune Serene, 3rd Floor, Plot No: 89/B, 90/A, West Avenue 9, Electronic City Phase 1,Bangalore 560100
Hi, On Jun 11th 2026 4.00pm UK, Rustam Ismayilov will present the topic of
TF-RMM fuzzing with the following agenda: Fuzzed Interfaces fake_host AFL++
seed generation statefull fuzzing Results and performance Limitations and
planned improvements Regards, Olivier.
TF-A Tech Forum
Thursday Jun 11, 2026 ⋅ 5pm – 6pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
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Hi all,
I am sending this note to get feedback from platform maintainers on an EL3 SPMC change in my current series (https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/50778/).
The patch updates spmc_ffa_mem_retrieve_req() to take a snapshot of the caller's FFA_MEM_RETRIEVE_REQ descriptor into the EL3 SPMC shmem datastore before validation and response handling. The intent is to avoid repeatedly reading mutable fields from the caller-owned TX buffer while the request is being processed. In other words, once the request enters EL3 SPMC, we operate on a stable local copy rather than on memory that remains under the caller's control.
The EL3 SPMC datastore is already used to cache shared memory transaction descriptors. With this change, it is also used to hold a temporary copy of the retrieve request. That means datastore sizing becomes more important, since a valid larger retrieve request may now fail if the backing datastore is too small.
The datastore sizes are defined in platform_def.h (https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… for the fvp platform) and while looking through the existing platform definitions, I noticed that datastore sizes vary quite a lot. For example, some platforms provide a relatively large backing store, while others define much smaller regions. In particular, rdn2 currently defines only a 1024-byte datastore. My concern is that for such platforms, larger memory-share / retrieve flows could fail simply because the datastore is too small to hold the request snapshot.
Before I proceed further, I wanted to ask platform maintainers:
1. Is there any platform-specific reason for these reduced datastore sizes?
2. If not, would maintainers be happy for these datastore sizes to be increased so they can accommodate larger valid transactions?
In short, I want to confirm whether the smaller datastore definitions are deliberate platform constraints, or whether they should be treated as undersized defaults that now need revisiting.
Feedback from maintainers would be very helpful before I post the next revision.
Kind Regards,
Daniel Boulby
Hi all,
We will be upgrading Cloudbees CI and clusters hosting review.trustedfirmware.org and ci.trustedfirmware.org on Wednesday, 3rd June 2025 at 16:00 GMT+1.
During this maintenance window, both services will be unavailable for approximately 8 hours.
A follow-up email will be sent once the services are fully restored.
Best regards,
Saheer
[LOGO SMALL]
Saheer Babu
Principal Software Engineer
CESW – Engineering Infrastructure
Hi All,
The next release of the Firmware-A bundle of projects tagged v2.12 has an expected code freeze date of Nov, 8th 2024.
Refer to the release cadence section from TF-A documentation (https://trustedfirmware-a.readthedocs.io/en/latest/about/release-informatio…).
Closing out the release takes around 6-10 working days after the code freeze.
v2.12 release preparation tasks start from now.
We want to ensure that planned feature patches for the release are submitted in good time for the review process to conclude.
As a kind recommendation and a matter of sharing CI resources, please launch CI jobs with care e.g.:
-For simple platform, docs changes, or one liners, use Allow-CI+1 label (no need for a full Allow-CI+2 run).
-For large patch stacks use Allow-CI+2 at top of the patch stack (and if required few individual Allow+CI+1 labels in the middle of the patch stack).
-Carefully analyze results and fix the change if required, before launching new jobs on the same change.
-If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not added as a gerrit comment on the patch right away please be patient as under heavy load CI jobs can be queued and in extreme conditions it can be over an hour before the Build start notice is issued. Issuing another Allow-CI+1 or Allow-CI+2 label will just result in an additional job being queued.
--
Thanks,
Govindraj R
Hi, On May 28th at 4.00pm UK, in the TF-A Tech Forum, Manish Badarkhe and
John Powell from Arm will present the topic of BL31 Live Firmware
Activation with the following agenda: -Quick recap of LFA SMC
implementation -BL31 live activation implementation -Assumptions and scope
for live activating BL31 -Test cases added for BL31 live activation
Regards, Olivier.
TF-A Tech Forum
Thursday May 28, 2026 ⋅ 5pm – 6pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
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This event has been canceled with a note:
"Hi, May 14th TF-A Tech Forum instance is cancelled with lack of topics.
Regards, Olivier. "
TF-A Tech Forum
Thursday May 14, 2026 ⋅ 5pm – 6pm
Central European Time - Paris
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Hello,
Thanks for the patch and the detailed commit message.
For ST boards, we usually treat this kind of issues with watchdog.
But I admit some watchdogs patches are still missing upstream.
I'll try to send them soon.
We are discussing internally to see if this particular use-case could be
done as you proposed.
I'll get back to you next week about this, when one of my colleagues
comes back.
Maybe this could be selected with a compilation flag.
About the patch submission, TF-A uses gerrit, and we do not merge
patches from mailing-list like Linux does.
Please check this page:
https://trustedfirmware-a.readthedocs.io/en/latest/process/contributing.html
Best regards,
Yann
On 4/29/26 05:21, Chanhong Jung wrote:
> A failed eMMC initialization in BL2's boot_mmc() currently calls
> panic(), leaving the system spinning forever and forcing an external
> power cycle to recover. In production deployments where the eMMC is
> the on-board boot medium, transient init failures (power-rail ramp
> timing, bus-line noise just after eMMC fast-boot mode entry, RCC
> clock-domain settling jitter, etc.) are far more common than hard
> failures, and the recovery path for all of them is "boot again from
> cold."
>
> Invoke stm32mp_system_reset() before panic() in the
> stm32_sdmmc2_mmc_init() failure path so the SoC restarts and BootROM
> re-runs the entire boot chain from scratch. Transient failures that
> clear themselves between cold boots are then resolved automatically
> without operator intervention.
>
> stm32mp_system_reset() carries the __dead2 (no-return) attribute, so
> control never reaches the following panic() in normal operation. The
> panic() call is intentionally retained for two reasons:
>
> 1. Defensive fallback should the reset circuit / power sequencer
> fail to actually issue a reset; staying in a tight panic() loop
> is then still preferable to executing past the failure point.
>
> 2. As an explicit "this branch must not continue" signal to static
> analyzers and future readers, so a subsequent edit cannot
> accidentally drop the reset call and silently revert the policy.
>
> This change has been in production on a downstream STM32MP153D board
> running a TF-A v2.4 backport for over a year. Only the central
> panic-to-reset change is sent here; related debug NOTICE() prints and
> an MMC retry-count bump that lived alongside the downstream patch are
> intentionally not included, as the unconditional reset fallback
> already covers the recovery cases the retry bump targeted.
>
> Signed-off-by: Chanhong Jung <happycpu(a)gmail.com>
> ---
> plat/st/common/bl2_io_storage.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
> index c478b497c..e6a73e0d3 100644
> --- a/plat/st/common/bl2_io_storage.c
> +++ b/plat/st/common/bl2_io_storage.c
> @@ -28,6 +28,7 @@
> #include <drivers/st/stm32_fmc2_nand.h>
> #include <drivers/st/stm32_qspi.h>
> #include <drivers/st/stm32_sdmmc2.h>
> +#include <drivers/st/stm32mp_reset.h>
> #include <drivers/usb_device.h>
> #include <lib/fconf/fconf.h>
> #include <lib/mmio.h>
> @@ -255,7 +256,19 @@ static void boot_mmc(enum mmc_device_type mmc_dev_type,
>
> params.device_info = &mmc_info;
> if (stm32_sdmmc2_mmc_init(¶ms) != 0) {
> - ERROR("SDMMC%u init failed\n", boot_interface_instance);
> + ERROR("SDMMC%u init failed - resetting system\n",
> + boot_interface_instance);
> + /*
> + * eMMC init failures here are usually transient (rail-ramp
> + * timing, bus-line noise on fast-boot entry, RCC clock-domain
> + * settling jitter). panic() leaves the SoC frozen and forces
> + * an external power cycle; a system reset lets BootROM re-run
> + * the entire boot path, which most transient failures survive.
> + * stm32mp_system_reset() is __dead2, so panic() below is a
> + * defensive fallback if the reset circuit is itself wedged,
> + * and a no-return marker for analyzers.
> + */
> + stm32mp_system_reset();
> panic();
> }
>
>
> base-commit: de387341ee73d99446fbbf6a7053d7b759b8b3a6
Hi All,
The next release of the Firmware-A bundle of projects tagged v2.15 has an
expected code freeze date of 15/05/2026.
Refer to the release cadence section from TF-A documentation
(https://trustedfirmware-a.readthedocs.io/en/latest/about/release-informatio…).
Closing out the release takes around 6-10 working days after the code freeze.
v2.15 release preparation tasks are on-going and well progressed.
We want to ensure that planned feature patches for the release are submitted in
good time for the review process to conclude.
As a kind reminder and a matter of sharing CI resources, please launch CI
jobs with care e.g.:
*
For simple platform, docs changes, or one liners, use Allow-CI+1 label (no
need for a full Allow-CI+2 run).
*
For large patch stacks use Allow-CI+2 at top of the patch stack (and if
required few individual Allow+CI+1 labels in the middle of the patch stack).
*
Carefully analyze results and fix the change if required, before launching new
jobs on the same change.
*
If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not
added as a gerrit comment on the patch right away please be patient as under
heavy load CI jobs can be queued and in extreme conditions it can be over an
hour before the Build start notice is issued. Issuing another Allow-CI+1 or
Allow-CI+2 label will just result in an additional job being queued.
Thanks & Regards,
Harrison on behalf of the TF-A team
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*Environment:*
- *Exception Level:* EL3 (AArch64)
- *Component:* [image: 微信图片_20260304154227_69_553.png]
ARM Trusted Firmware (TF-A) - BL2/BL31
- *Platform:* Arm FVP / Base_Revc_2xAEMvA / Bare Metal Debug
/ARMAEM-A_MP_0 [ Arm Development Studio ]
*Observation:*
I am observing a strange thing of the ARMv8-A architecture's memory
translation rules. Despite the translation table explicitly marking the
memory region as Execute-Never, the CPU continues to fetch and execute
instructions from this region without triggering an exception. I'm a
student with limited hardware background, and I'm learning TF-A and doing
porting during my internship. I'd really like to know the reason behind
this.
*Code I use:* ARM Trusted Firmware v2.13
*Github:* github.com/.../arm-trusted-firmware
<https://github.com/ARM-software/arm-trusted-firmware>
*Take the case of running BL31 in Development Studio as an example.
(Breakpoint at the beginning of bl31_setup)*
*Technical Evidence (Verified via Debugger):*
SCTLR_EL3: M=1 (MMU enabled), WXN=1 (Write implies execute-never), I=1
(Instruction Cache enabled).
BL31’s code is loaded at: 0x04003000
Translation Table Entry (L3 Descriptor): 0x00400000_04003743
Physical Address: Verified via TTBR0_EL3 walk. (0x04034600 -> 0x04035003 ->
0x04037003 -> 0x00400000_04003743)
Attributes: AP[2:1]=0x1 (Read/Write), XN=1 (Execute-Never), AF=1, SH=0x3
(Inner Shareable), NS=0, AttrIndx = 0x0 (See the MAIR_EL3)
MAIR_EL3: 0x4404FF (Attr0 = 0xFF, Normal Memory).
Synchronization Performed: DSB SY + ISB
The PC (Program Counter) is confirmed to executing from the first
instruction of BL31 code at address 0x04003000.
*The Problem:*
This evidence should point to one conclusion: it cannot execute the BL31
code and will report an error. However, the execution flow remains
uninterrupted.
From my point of view, it should cause "ESR_EL3 = 0x8600000F", which means:
"Instruction Abort taken without a change in Exception level.
Used for MMU faults generated by instruction accesses and synchronous
External aborts, including synchronous parity or ECC errors. Not used for
debug-related exceptions."
+
"Permission Fault, level 3".
As I test on a real fpga by using similar code by making some changes at
the end of BL1 so that it would execute BL2 at level EL3 (but instead of
bl2_el3_entrypoint.S, it would execute bl2_entrypoint.S). In this case, it
throws an error when it jumps to the first instruction of BL2, and the
ESR_EL3 register displays "Permission Fault, level 3".
If I add the instruction to disable the MMU (setting SCTLR_EL3.M_BIT to 0)
at the end of BL1, and change the function to enable the MMU in the
official code "arm_bl2_plat_arch_setup" to use "enable_mmu_el3(0)", it can
run normally on the FPGA and bring up the UEFI. (In this real-world test, I
used DDR instead of SRAM, so BL2 and BL31 were also placed here after being
parsed.)
*Request for Help:*
The above content is beyond my comprehension; even my internship supervisor
doesn't understand the reasoning behind it. Therefore, I need help from the
experts on this forum.
*Reference:*
DDI0487M_a_a-profile_architecture_reference_manual.pdf
ARM Development Studio@Docs (such as Docs/ARM_A/xhtml/AArch64-esr_el3.html)
armv8_a_address_translation version1.1
Hi, this is Scaria Kochidanadu, from Texas Instruments and would like to
present : "s2idle-driven Low Power Mode Selection using PSCI on AM62L",
in the TF-A tech forum on April 2nd, 2026.
We present a runtime-configurable low power mode(LPM) management
approach for *PSCI* firmware in ATF, implemented on the AM62L SoC, a
2-core system with A53 cores. The primary goal of this session is to
gather feedback on the *suitability of this design for upstreaming*, and
to get guidance on key challenges encountered during implementation
before proceeding with further debugging and optimization. In this
design, we transition to an *s2idle-based flow* where Linux cpuidle
framework and governor drive idle state selection, from the multiple
platform-specific standby and low power modes that are provided in the
devicetree. The PSCI driver in ATF is then responsible for the
validation of the idle-states passed and the entire suspend-resume flow,
with the *Operating-System Initiated (OSI) mode in PSCI*. As ATF now
handles the full suspend-resume flow, it has the responsibility of
managing the powering down and bringing up of the cores, along with the
state of the system. We observe issues related to core *coordination in
a multi-core system*, as well as system state management during resume,
including *GIC* and (*Interrupt Translation Service*)ITS context
handling. In this session, we will present our suspend and resume design
in the AM62L PSCI implementation and discuss these challenges in detail.
We would also like to discuss the *current validation logic* for the
context-preserving retention states like standby and our approach to
enable standby mode. We are particularly interested in feedback on
whether this *OS-driven LPM selection model aligns with ATF design
expectations*, and on recommended approaches for handling *inter-core
coordination and system state restoration within PSCI-based flows*.
Regards, Scaria Kochidanadu, Texas Instruments.
[+ TF-A list for FYI]
Hi All,
An update on v2.0 migration.
As RMM and the rest of the software stack are being prepared for the initial v2.0 migration, TF-A has introduced a new build configuration flag, RMM_V1_COMPAT, to control the world-switch behaviour between RMM v1.x and RMM v2.0 [1] .
This flag is enabled by default, meaning the default behaviour currently corresponds to RMM v1.x. Once TF-RMM is ready to merge the v2.0 support, the default value of this flag will be changed to 0.
The flag also updates the EL3–RMM interface major version, allowing incompatibility with TF-A related to this build configuration to be detected at runtime.
We expect the initial v2.0 changes in TF-RMM to be merged by the end of this month. As mentioned in the previous email, we will create a v1.x branch prior to this and provide an update here.
[1] https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r…
Best regards,
Soby Mathew
From: Soby Mathew via tf-rmm <tf-rmm(a)lists.trustedfirmware.org>
Date: Thursday, 5 February 2026 at 09:42
To: tf-rmm(a)lists.trustedfirmware.org <tf-rmm(a)lists.trustedfirmware.org>
Cc: nd <nd(a)arm.com>
Subject: [tf-rmm] RMMv2.0 implementation plan for TF-RMM
Hi Everyone,
The RMM v2.0 Beta 0 specification has been published here:
https://developer.arm.com/documentation/den0137/latest/
As you may have noticed, this release introduces breaking changes to the RMI APIs (host side), while the RSIs (guest side) remain backward compatible. Nearly all ABIs are affected, and the scope of these changes makes it highly disruptive to maintain support for both RMI v1.x and RMI v2.0 within the same codebase. We do not expect RMI v1.x to be deployed in production, and retaining support for it would increase development overhead and the risk of introducing bugs.
A more pragmatic approach is to branch the current RMM codebase at the RMI v1.x ABI and then migrate the mainline to the RMI v2.0 ABI. This will be a breaking change for host-side components that rely on the older RMI ABI. Given the extent of the ABI changes, significant effort will be required to align with RMI v2.0, and this approach allows the team to focus on upstreaming the new ABI support efficiently.
The initial RMI v2.0 upstreaming will consist of a series of commits that together form an initial RMM implementation targeting the RMM v2.0 specification. This initial implementation will not be fully feature-complete with respect to the v2.0 spec, and we expect to continue layering additional RMM v2.0 ABI-related changes on top as the implementation matures during the course of the year.
That said, we intend to maintain integration with an externally available, compatible Linux host kernel branch throughout this process. The initial RMI v2.0 RMM implementation will be compatible with an initial v2.0-based host kernel, and we will notify the mailing list once this integration is available to pick up (likely end of March ’26). If and when we need to introduce further ABI changes that break compatibility with a previously published kernel branch, we will call this out explicitly in advance and indicate when an updated kernel branch will be available for integration.
We plan to keep RMI v1.x ABI as a separate branch and selectively merge bug fixes on a request or need basis. Please let us know if you have any concerns regarding this plan within the next two weeks.
Best Regards
Soby Mathew