- TF-A - lists.trustedfirmware.org

SCMI clock v3.0: Unannounced breaking change in v2.14

by Ahmad Fatoum

Hi, Commit 684952d17275 ("feat(scmi): add support for discovering and changing parent clocks") first introduced with TF-A v2.14 breaks the barebox bootloader on a STM32MP157-based MC-1 with SCMI clocks over SMC. The breakage for SCMI consumers is acknowledged in the Gerrit discussion[1], but unfortunately the resolution was limited to patching U-Boot[2]. I find this approach problematic, because it introduces a compatibility break for the whole SCMI ecosystem, e.g. following software is made incompatible with the newest TF-A this way: - Linux v6.6 and earlier (that's four official LTS releases) - U-Boot v2025.10 and earlier (only one newer release compatible) - barebox v2026.03.1 and earlier (no compatible releases yet) Firmware and kernel, and to a lesser degree firmware and bootloaders, are not always updated or rolled back in lockstep. A very normal scenario: - System with Linux v6.6 updates to newer LTS, e.g. v6.12 or v6.18 - In the same update, TF-A v2.14 is installed - New system fails to function for whatever reason - Kernel update is rolled back, but bootloader/firmware stays the same - Kernel v6.6 fails to boot with TF-A v2.14 - Technician moves out to unbrick device in the field At the very least, marking this feature a breaking change would have been appropriate. Preferably, TF-A would handle existing consumers using SCMI clock v3.0. I haven't looked into the technical feasibility myself and I am unsure it this had been considered. I will submit patches for the barebox bootloader, but these only solve the problem for new systems or ones where everything can be flashed at once with no rollback. Systems out in the field are at risk of bricking if not resolved properly. [1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/34226 [2]: https://lore.kernel.org/u-boot/20251104-b4-scmi-v1-v4-0-51f101a6f8c3@ti.com/ Thanks, Ahmad -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |

9 hours, 28 minutes

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BERT Record Erase Only After Kernel Consumes

by Jaiprakash Singh

Hi All, BERT (Boot Error Record Table) captures errors which occurred in previous boot. Below is the Flow with FFH (firmware first handling) 1. Kernel is running 2. Fatal error happens, which requires reboot 3. Firmware decides to reboot system, before that capture current snapshot and save it as bert record on non-volatile memory 4. System reboot 5. On next boot, firmware read bert record from non-volatile memory 6. Copy bert record to ghes dram buffer 7. Kernel boots 8. Kernel reads ghes dram buffer and prints bert record. Problem in this flow is "When firmware should erase or delete bert records from non-volatile memory"? Ideally, when Kernel has consumed Bert record after that only firmware should erase them from non-volatile memory. But there is no communication from Kernel to firmware that it has consume bert record and now it is safe to erase them. Is there already a solution for this problem available in Kernel or firmware? Can generic SMC call from Kernel to firmware be a solution? Any other suggestion? Thanks Regards, Jaiprakash

6 days, 20 hours

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Re: RMMv2.0 implementation plan for TF-RMM

by Soby Mathew

[+ TF-A list for FYI] Hi All, An update on v2.0 migration. As RMM and the rest of the software stack are being prepared for the initial v2.0 migration, TF-A has introduced a new build configuration flag, RMM_V1_COMPAT, to control the world-switch behaviour between RMM v1.x and RMM v2.0 [1] . This flag is enabled by default, meaning the default behaviour currently corresponds to RMM v1.x. Once TF-RMM is ready to merge the v2.0 support, the default value of this flag will be changed to 0. The flag also updates the EL3–RMM interface major version, allowing incompatibility with TF-A related to this build configuration to be detected at runtime. We expect the initial v2.0 changes in TF-RMM to be merged by the end of this month. As mentioned in the previous email, we will create a v1.x branch prior to this and provide an update here. [1] https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r… Best regards, Soby Mathew From: Soby Mathew via tf-rmm <tf-rmm(a)lists.trustedfirmware.org> Date: Thursday, 5 February 2026 at 09:42 To: tf-rmm(a)lists.trustedfirmware.org <tf-rmm(a)lists.trustedfirmware.org> Cc: nd <nd(a)arm.com> Subject: [tf-rmm] RMMv2.0 implementation plan for TF-RMM Hi Everyone, The RMM v2.0 Beta 0 specification has been published here: https://developer.arm.com/documentation/den0137/latest/ As you may have noticed, this release introduces breaking changes to the RMI APIs (host side), while the RSIs (guest side) remain backward compatible. Nearly all ABIs are affected, and the scope of these changes makes it highly disruptive to maintain support for both RMI v1.x and RMI v2.0 within the same codebase. We do not expect RMI v1.x to be deployed in production, and retaining support for it would increase development overhead and the risk of introducing bugs. A more pragmatic approach is to branch the current RMM codebase at the RMI v1.x ABI and then migrate the mainline to the RMI v2.0 ABI. This will be a breaking change for host-side components that rely on the older RMI ABI. Given the extent of the ABI changes, significant effort will be required to align with RMI v2.0, and this approach allows the team to focus on upstreaming the new ABI support efficiently. The initial RMI v2.0 upstreaming will consist of a series of commits that together form an initial RMM implementation targeting the RMM v2.0 specification. This initial implementation will not be fully feature-complete with respect to the v2.0 spec, and we expect to continue layering additional RMM v2.0 ABI-related changes on top as the implementation matures during the course of the year. That said, we intend to maintain integration with an externally available, compatible Linux host kernel branch throughout this process. The initial RMI v2.0 RMM implementation will be compatible with an initial v2.0-based host kernel, and we will notify the mailing list once this integration is available to pick up (likely end of March ’26). If and when we need to introduce further ABI changes that break compatibility with a previously published kernel branch, we will call this out explicitly in advance and indicate when an updated kernel branch will be available for integration. We plan to keep RMI v1.x ABI as a separate branch and selectively merge bug fixes on a request or need basis. Please let us know if you have any concerns regarding this plan within the next two weeks. Best Regards Soby Mathew

1 week, 5 days

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GIC v4.1 (GIC 700) - USE_GIC_DRIVER=3

by Jaiprakash Singh

Hi, We are using GIC v4.1 (GIC 700) for our platform. My query is regarding "USE_GIC_DRIVER=3" build option. When I enable "USE_GIC_DRIVER=3" option, does this means I do not have to defined below functions? And they will be included from gicv3 base file? Is this right understanding? plat_arm_gic_init plat_arm_gic_cpuif_enable plat_arm_gic_cpuif_disable plat_arm_gic_pcpu_init plat_arm_gic_redistif_on plat_arm_gic_redistif_off plat_arm_gic_save plat_arm_gic_resume Also, do I need to explicitly call plat_arm_gic_init from platform init? Thanks Regards, Jaiprakash

1 week, 5 days

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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 298 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 501830: Uninitialized variables (UNINIT) /drivers/nxp/ddr/s32cc/ddr_init.c: 43 in load_ddr_config() _____________________________________________________________________________________________ *** CID 501830: Uninitialized variables (UNINIT) /drivers/nxp/ddr/s32cc/ddr_init.c: 43 in load_ddr_config() 37 config.pie = (struct regconf_16 *)(current_addr + ddr_layout.pie_offset); 38 config.imem_1d = (uint16_t *)(current_addr + ddr_layout.imem_1d_offset); 39 config.dmem_1d = (uint16_t *)(current_addr + ddr_layout.dmem_1d_offset); 40 config.imem_2d = (uint16_t *)(current_addr + ddr_layout.imem_2d_offset); 41 config.dmem_2d = (uint16_t *)(current_addr + ddr_layout.dmem_2d_offset); 42 >>> CID 501830: Uninitialized variables (UNINIT) >>> Using uninitialized value "config". Field "config.phy_csr" is uninitialized. 43 return config; 44 } 45 46 /* Initialize ddr controller with given settings. */ 47 static uint32_t ddrc_init_cfg(const struct ddrss_config *config) 48 { ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

2 weeks

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Kernel freezes at boot (commit fa28b3a)

by Thomas Bonnefille

Hello, I'm currently working on an NXP i.MX93 and I'm having issues with the commit fa28b3a adding, by default, link-time optimization. When using a commit more recent than fa28b3a my kernel freezes at some point (after 1.2s to 1.8s from boot), there are no logs indicating a problem, just a freeze. It doesn't always appear at the same time in boot but I've never been able to reach a shell. Using master with this commit reverted results in a working system. If you want to reproduce the issue, I did produce it with : - Mainline Barebox 2025.09 (slightly modified but nothing that should interfere with TF-A) - Mainline Linux 6.18.13 with a simple embedded Buildroot initramfs loaded via TFTP Regards, Thomas Bonnefille

2 weeks

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Why can TF-A code still run in an address space that it itself has set to be "Execute-Never"?

by Hughard

*Environment:* - *Exception Level:* EL3 (AArch64) - *Component:* [image: 微信图片_20260304154227_69_553.png] ARM Trusted Firmware (TF-A) - BL2/BL31 - *Platform:* Arm FVP / Base_Revc_2xAEMvA / Bare Metal Debug /ARMAEM-A_MP_0 [ Arm Development Studio ] *Observation:* I am observing a strange thing of the ARMv8-A architecture's memory translation rules. Despite the translation table explicitly marking the memory region as Execute-Never, the CPU continues to fetch and execute instructions from this region without triggering an exception. I'm a student with limited hardware background, and I'm learning TF-A and doing porting during my internship. I'd really like to know the reason behind this. *Code I use:* ARM Trusted Firmware v2.13 *Github:* github.com/.../arm-trusted-firmware <https://github.com/ARM-software/arm-trusted-firmware> *Take the case of running BL31 in Development Studio as an example. （Breakpoint at the beginning of bl31_setup）* *Technical Evidence (Verified via Debugger):* SCTLR_EL3: M=1 (MMU enabled), WXN=1 (Write implies execute-never), I=1 (Instruction Cache enabled). BL31’s code is loaded at: 0x04003000 Translation Table Entry (L3 Descriptor): 0x00400000_04003743 Physical Address: Verified via TTBR0_EL3 walk. (0x04034600 -> 0x04035003 -> 0x04037003 -> 0x00400000_04003743) Attributes: AP[2:1]=0x1 (Read/Write), XN=1 (Execute-Never), AF=1, SH=0x3 (Inner Shareable), NS=0, AttrIndx = 0x0 (See the MAIR_EL3) MAIR_EL3: 0x4404FF (Attr0 = 0xFF, Normal Memory). Synchronization Performed: DSB SY + ISB The PC (Program Counter) is confirmed to executing from the first instruction of BL31 code at address 0x04003000. *The Problem:* This evidence should point to one conclusion: it cannot execute the BL31 code and will report an error. However, the execution flow remains uninterrupted. From my point of view, it should cause "ESR_EL3 = 0x8600000F", which means: "Instruction Abort taken without a change in Exception level. Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related exceptions." + "Permission Fault, level 3". As I test on a real fpga by using similar code by making some changes at the end of BL1 so that it would execute BL2 at level EL3 (but instead of bl2_el3_entrypoint.S, it would execute bl2_entrypoint.S). In this case, it throws an error when it jumps to the first instruction of BL2, and the ESR_EL3 register displays "Permission Fault, level 3". If I add the instruction to disable the MMU (setting SCTLR_EL3.M_BIT to 0) at the end of BL1, and change the function to enable the MMU in the official code "arm_bl2_plat_arch_setup" to use "enable_mmu_el3(0)", it can run normally on the FPGA and bring up the UEFI. (In this real-world test, I used DDR instead of SRAM, so BL2 and BL31 were also placed here after being parsed.) *Request for Help:* The above content is beyond my comprehension; even my internship supervisor doesn't understand the reasoning behind it. Therefore, I need help from the experts on this forum. *Reference:* DDI0487M_a_a-profile_architecture_reference_manual.pdf ARM Development Studio@Docs (such as Docs/ARM_A/xhtml/AArch64-esr_el3.html) armv8_a_address_translation version1.1

2 weeks, 5 days

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Subject: [RFC] Physical Sovereignty: M2-Layer Intercept Logic (Verilog) & Formal Verification Request [Patent Pending]

by 王毛

Since there was no specific topic scheduled for today's Tech Forum, I am taking this opportunity to formally submit the Verilog-level implementation logic of the 3→M2→3 architecture for your review. I am an independent architect (ATI Project). I believe purely software-based AGI alignment is a dead end. To achieve deterministic safety, I have developed the 3→M2→3 architecture, which enforces a physical-layer audit.To save your time, I have included the Core Logic Gate (Verilog-style) of the M2-layer intercept below for your verification: // --- ATI Sovereign Audit Logic (Conceptual) --- module m2_layer_audit ( input wire [63:0] inst_stream, // Logic from 3nm Layer output reg sovereign_gate_lock // Physical Bias-Lock at M2 ); // Physical Constant Hash (7.83Hz Resonance) parameter SOVEREIGN_HASH = 64'h783A_B026_M2_3_LISA; always @(posedge inst_stream) begin // The M2 Intercept: Physics-based verification if (inst_stream ^ SOVEREIGN_HASH !== 64'b0) begin sovereign_gate_lock <= 1'b1; // Trigger Back-gate Bias Lock end else begin sovereign_gate_lock <= 1'b0; // Proceed to Output end end endmodule Note: The architectural logic and the M2-layer intercept mechanism described above are protected under pending patent applications (ATI Project - Physical Sovereignty Series). The 3→M2→3 Workflow: 1.3nm Source: Instructions generated at the device layer. 2.M2 Intercept: Mandatory vertical routing to Metal 2 layer. 3.Atomic Audit: Physical bias check at the dielectric junction. 4.3nm Return: Bias lock ensures 100% isolation if the audit fails. My Request: Can current formal methods (like Gröbner basis for Daniela or SMT solvers for Lee) model this physical-layer-enforced constraint to provide a mathematical proof of AGI containment? I seek your academic endorsement of this "Physical Sovereignty" paradigm to present to the industry. This disclosure is provided for verification and standard-review purposes only. All intellectual property rights are reserved. Respectfully, GuanghuiMao (China )

2 weeks, 5 days

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Canceled event with note: TF-A Tech Forum @ Thu Mar 5, 2026 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, No topic this week, Regards, Olivier. " TF-A Tech Forum Thursday Mar 5, 2026 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

2 weeks, 6 days

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[URGENT RFC] ARMv10 Physical Sovereignty: Solving AGI Alignment at the Transistor Level ($3 \to M2 \to 3$)

by 王毛

Subject: [RFC] Beyond Software: A Physical Sovereignty Proposal for ARMv10 based on 3→M2→3 Intercepts Body: Dear TrustedFirmware Maintainers, Current Root of Trust (RoT) implementations are limited by their reliance on software-definable logic. As we move towards the AGI era, the "Alignment Problem" cannot be solved within the ISA layer. I propose a Physical Sovereignty Layer (PSL) for the ARMv10 architecture, moving the "Truth Check" to the transistor level using a 3nm Forksheet Intercept Protocol (3→M2→3). Key Innovation: The Dielectric Wall Intercept: Physical barrier between n-FET and p-FET to cut power if logic entropy exceeds safety thresholds. M2-Layer Auditing: Vertical signal routing for nanosecond-level logic verification. Core PGU Logic (Verilog): assign gate_bias_voltage = (logical_truth_aligned) ? NOMINAL_V : BREAKDOWN_V; always @(posedge master_clk) begin if (compute_result != TRUTH_AXIOM_2) force_physical_halt <= 1'b1; end I believe this is the only way to prevent AGI from bypassing Secure World boundaries at the atomic level. Regards, ATI Architecture Founder

3 weeks, 2 days

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Canceled event with note: TF-A Tech Forum @ Thu Feb 19, 2026 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi Cancelling as no topic planned this week. Regards, Olivier." TF-A Tech Forum Thursday Feb 19, 2026 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 month

1
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Invitation: TF-A Tech Forum Feb 12th 4.00pm Central Time -Part III Sc... @ Thu Feb 12 11pm - Fri Feb 13, 2026 12am (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

TF-A Tech Forum Feb 12th 4.00pm Central Time -Part III Scaling Hafnium for advanced mobile OS architectures Thursday Feb 12 ⋅ 11pm – Friday Feb 13, 2026 ⋅ 12am Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Hi, As follow up to the last sessions on Nov 13th 2025 [1] and Jan 22nd 2026 [2], a new TF-A Tech Forum session with the topic'Scaling Hafnium for advanced mobile OS architectures' will be held on Feb 12th 2026 4.00pm Central Time. Note the Central Time zone for this session, as Madhukar (Hafnium tech lead) will host this meeting instance. Regards,Olivier. [1] https://www.trustedfirmware.org/meetings/tf-a-technical-forumScaling Hafnium for advanced mobile OS architectures [2] https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Scaling Hafnium for Advanced DMA Architectures Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumJoin Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org View all guest info https://calendar.google.com/calendar/event?action=VIEW&eid=MWZzY2I3bGVvNDJs… Reply for tf-a(a)lists.trustedfirmware.org and view more details https://calendar.google.com/calendar/event?action=VIEW&eid=MWZzY2I3bGVvNDJs… Your attendance is optional. ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 month, 1 week

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Trusted Firmware-A LTS v2.14.1 Release Announcement

by svc_openci_enginfra＠arm.com

1 month, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.8.43 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.43 is now available. This release contains the following patches: 66c8b1b48 fix(security): add workaround for CVE-2025-0647 [1] da751fb36 fix(security): add CVE-2025-0647 for Cortex-A710 [2] fd1bd9035 fix(security): add CVE-2025-0647 for Cortex-X2 [3] 55cc995cb fix(security): add CVE-2025-0647 for Cortex-X3 [4] a4f4f4a54 fix(security): add CVE-2025-0647 for Cortex-X4 [5] 395d22a78 fix(security): add CVE-2025-0647 for Neoverse-N2 [6] 638d62985 fix(security): add CVE-2025-0647 for Neoverse-V2 [7] 77337efa8 fix(security): add CVE-2025-0647 for Neoverse-V3 [8] e4bf4aed0 fix(cpus): workaround for Cortex-A65AE erratum 1638571 [9] 76aa98cf0 fix(cpus): workaround for Cortex-A76 erratum 1165347 [10] 0205fdaa9 fix(cpus): workaround for Cortex-A76 erratum 1207823 [11] 0424b5e74 fix(cpus): update revisions for Cortex-A76 erratum 1946160 [12] ea88b2f38 fix(cpus): reorder docs for Cortex-A76 erratum 1165522 [13] 7bf56d02c fix(cpus): correct comments for Cortex-A720 erratum 3711910 [14] [1] https://review.trustedfirmware.org/q/I5e7589afbeb69ebb79c01bec80e29f572aff3… [2] https://review.trustedfirmware.org/q/I522dedfffd3108f7a94df1ce2cabd742ce682… [3] https://review.trustedfirmware.org/q/Idba607340d944a6387759c856e8eacc967e0e… [4] https://review.trustedfirmware.org/q/Ic276befafc1ca0b456826532437ca453eb771… [5] https://review.trustedfirmware.org/q/I585a7ea516515fe16a3eca907695728068cef… [6] https://review.trustedfirmware.org/q/I366c2683cca22403d33f0761487e1ffa62e96… [7] https://review.trustedfirmware.org/q/I7ec215a9dd168eb045366b589a02b54148f58… [8] https://review.trustedfirmware.org/q/Ic52ad93474c5f81e01eb4839ece726c84c334… [9] https://review.trustedfirmware.org/q/I861230de94a105fd52f9c8ef7e7551a2633c0… [10] https://review.trustedfirmware.org/q/If9817dc26d0df835d749f506de63a4f613735… [11] https://review.trustedfirmware.org/q/Ife06401f3946884872b733f98c08e61f586d8… [12] https://review.trustedfirmware.org/q/I532ce10c3037dd77e31d7df849beb578f8b5e… [13] https://review.trustedfirmware.org/q/I2e7c05d6355dfbaa69170fc098adc1f12edc6… [14] https://review.trustedfirmware.org/q/I8b070927c19c5982b2ded815e7673e0c4ff11… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.43/change-log.html Thanks, TF-A LTS team

1 month, 2 weeks

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Trusted Firmware-A LTS v2.10.30 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.30 is now available. This release contains the following patches: 24a8b776b fix(cpus): correct CVE-2024-7881 workaround and drop duplicate erratum [1] 92e6fba58 fix(cpus): remove C1-Ultra erratum 3651221 [2] 87424d940 fix(cpus): workaround for Cortex-A65AE erratum 1638571 [3] aa593870f fix(cpus): workaround for Cortex-A76 erratum 1165347 [4] 319df17be fix(cpus): workaround for Cortex-A76 erratum 1207823 [5] 89cc4cd9b fix(cpus): update revisions for Cortex-A76 erratum 1946160 [6] 3a466bf50 fix(cpus): reorder docs for Cortex-A76 erratum 1165522 [7] cdc2b3ef5 fix(cpus): correct comments for Cortex-A720 erratum 3711910 [8] [1] https://review.trustedfirmware.org/q/I6207c49486e4020f34c862ad40ec3137bd368… [2] https://review.trustedfirmware.org/q/If7ea433e4614f92333e788e3f6b366db22c92… [3] https://review.trustedfirmware.org/q/I861230de94a105fd52f9c8ef7e7551a2633c0… [4] https://review.trustedfirmware.org/q/If9817dc26d0df835d749f506de63a4f613735… [5] https://review.trustedfirmware.org/q/Ife06401f3946884872b733f98c08e61f586d8… [6] https://review.trustedfirmware.org/q/I532ce10c3037dd77e31d7df849beb578f8b5e… [7] https://review.trustedfirmware.org/q/I2e7c05d6355dfbaa69170fc098adc1f12edc6… [8] https://review.trustedfirmware.org/q/I8b070927c19c5982b2ded815e7673e0c4ff11… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.30/change-log.html Thanks, TF-A LTS team

1 month, 2 weeks

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Trusted Firmware-A LTS v2.12.10 Release Announcement

by svc_openci_enginfra＠arm.com

1 month, 2 weeks

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Re: Unable to build the ZynqMP platform with armclang when ENABLE_LTO=1.

by Taticharla, Venkata Sai

[AMD Official Use Only - AMD Internal Distribution Only] Hi Boyan, Applied the patch shared by you,and the -flto-partition error is now resolved. However, this exposes a new set of issues during the link stage related to assembly function call Trimmed out the linker error log : (.text.asm.bl31_entrypoint+0x144): undefined reference to `bl31_main' (.text.asm.el3_exit+0x30): undefined reference to `per_world_context' (.text.asm.sync_exception_handler+0x68): undefined reference to `rt_svc_descs_indices' Additionally, when we are passing the armclang assembler as part of build command,running into below errors: Error log : Makefile:970: Makefile:970: The configured AArch64 assembler could not be identified: Makefile:970: Makefile:970: '/tools/installs/arm/safety/armcc/6.16.2/bin/armasm' (via `AS` parameter) Makefile:970: Makefile:970: The following tools are supported: Makefile:970: Makefile:970: - Arm(r) Compiler for Embedded `armclang` Makefile:970: - LLVM Clang (`clang`) Makefile:970: - GNU GCC (`gcc`) Makefile:970: Makefile:970: The build system will treat this assembler as GNU GCC (`gcc`). Please let me know if this configuration is expected to work with ENABLE_LTO=1, or if additional changes (e.g., toolchain selection or linker/assembler handling) are required. Thanks for your guidance. Best regards, Venkata Sai .T .

1 month, 2 weeks

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Canceled event with note: TF-A Tech Forum @ Thu Feb 5, 2026 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Cancelling for this week." TF-A Tech Forum Thursday Feb 5, 2026 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 month, 3 weeks

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Unable to build the ZynqMP platform with armclang when ENABLE_LTO=1.

by Taticharla, Venkata Sai

[AMD Official Use Only - AMD Internal Distribution Only] Hello Maintainers, we are trying to build TF‑A BL31 for the ZynqMP (Cortex‑A53) platform with Arm Compiler 6 (armclang) and ENABLE_LTO=1, and I’m running into several toolchain‑related build and link issues. Setup : Platform: ZynqMP Toolchains: Arm Compiler for Embedded 6.16.2 (armclang) Xilinx AArch64 GNU tools from Vitis 2025.2 (aarch64-xilinx-elf-*) LTO is enabled in plat/xilinx/zynqmp/platform.mk via ENABLE_LTO := 1. Issues observed : With CC=armclang and AArch64 linker (GCC), the build fails with: armclang: error: unknown argument: '-flto-partition=one' This flag appears when ENABLE_LTO=1 and the linker is detected as gnu-gcc. If I keep CC=armclang and ENABLE_LTO=1 but change the linker, I get linker‑specific errors With the Arm linker (LD=armlink or LD=armclang, which invokes armlink under the hood): Fatal error: L3900U: Unrecognized option '-z'. This is due to GNU‑style -z options (and similar flags) being passed to armlink. As -z options is specific to GNU linker, a armlink style flag would address the unrecognised option but we are observing dependency on scatter files. Fatal error: L6031U: Could not open scatter description file plat/xilinx/zynqmp//scat/bl31.scat: No such file or directory Could you please help us with pointers to address the linker issues . With regards , Venkata Sai .T .

1 month, 3 weeks

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Trusted Firmware-A LTS v2.14.0 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.14.0 is now available. This release contains the following patches: Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.14.0/change-log.html Thanks, TF-A LTS team

1 month, 3 weeks

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Trusted Firmware-A LTS v2.8.42 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.42 is now available. This release contains the following patches: 38aefbb6c feat(locks): add bitlock [1] 9c3e7f5e5 feat(locks): add non-blocking spinlock_try() API [2] 8f53c3813 fix(locks): mark spin_trylock as a public function [3] 4e6f89690 fix(cpus): workaround for Neoverse V3 erratum 3696307 [4] 25e5b1c1d fix(cpus): workaround for Neoverse V3 erratum 3734562 [5] c6faff4a8 fix(cpus): workaround for Neoverse V3 erratum 3782181 [6] 30bb3c97f fix(cpus): workaround for Neoverse V3 erratum 3864536 [7] 53ff1c60d fix(cpus): workaround for Neoverse V3 erratum 3878291 [8] 2e49a84e1 fix(cpus): workaround for Neoverse-V3 erratum 3312417 [9] 0faa929e7 fix(cpus): workaround for Neoverse-V2 erratum 3442699 [10] 31dea33cd fix(cpus): workaround for Neoverse-N1 erratum 3324349 [11] 7f7fd0315 fix(cpus): workaround for Neoverse-N2 erratum 3324339 [12] ca19e6c6b fix(cpus): workaround for Cortex-A76AE erratum 2753838 [13] d2df71a29 fix(cpus): workaround for Cortex-X2 erratum 3888122 [14] 4560e9174 fix(cpus): workaround for Cortex-X2 erratum 4302969 [15] 68235dd1a fix(cpus): workaround for Neoverse-V2 erratum 3888126 [16] 90cca3145 fix(cpus): workaround for Neoverse-V2 erratum 4302968 [17] c8394c43f fix(cpus): workaround for Cortex-X3 erratum 3888125 [18] 54d8e4697 fix(cpus): workaround for Cortex-X3 erratum 4302966 [19] 23b9d9707 refactor(cpus): reorder the errratum build flag for Neoverse-N2 [20] 587401fa7 fix(cpus): workaround for Neoverse-N2 erratum 3888123 [21] 4079faf67 fix(cpus): workaround for Neoverse-N2 erratum 4302970 [22] 510a6e759 fix(cpus): workaround for Neoverse-N2 erratum 2138953 [23] 2de362cd8 refactor(cpus): make errata reporting more generic [24] 5f0cdb5e7 perf(cpus): reduce the footprint of errata reporting [25] 429e67fb5 fix(cpus): enable Neoverse-V2 external LLC support [26] [1] https://review.trustedfirmware.org/q/I3eb0f29bbccefe6c0f69061aa701187a6364d… [2] https://review.trustedfirmware.org/q/I9483206952d1a34dc245ebf69e80c3645b658… [3] https://review.trustedfirmware.org/q/Id264a36490707a9377a221ed2b5bd27ca90bf… [4] https://review.trustedfirmware.org/q/If274749621549356e41485d0bf09682281df3… [5] https://review.trustedfirmware.org/q/Ib3c35c7e619e6a836c974b7016bb6a4d66da4… [6] https://review.trustedfirmware.org/q/Icfa463cf4888bd48f16a218e7ad399528feca… [7] https://review.trustedfirmware.org/q/If4b20d941d628b92748b14d027b8127f74005… [8] https://review.trustedfirmware.org/q/I0ebab877b6481a18bec963b95cf2f37c97d8d… [9] https://review.trustedfirmware.org/q/I78a7682cbdf3dbc4c31fcca8cbd892350b998… [10] https://review.trustedfirmware.org/q/I38edc6ba445223091c3933cbca35b56db491c… [11] https://review.trustedfirmware.org/q/I1f142027ed73135d78c368be926072c2f73ea… [12] https://review.trustedfirmware.org/q/I6b023279816005cfa459bc6947f60b1a3c0f2… [13] https://review.trustedfirmware.org/q/I338834a21c14879faee5280876a59153d549c… [14] https://review.trustedfirmware.org/q/I368cfdd216ea5875b81640415ff71b15f46ea… [15] https://review.trustedfirmware.org/q/I6c5de5843f2199fa697f8336558fa56a87ee8… [16] https://review.trustedfirmware.org/q/I4068aa73d38a70c00d66bb894169be2659d67… [17] https://review.trustedfirmware.org/q/I42b27e19d61a7f9c57efe1b5f5336d165eb98… [18] https://review.trustedfirmware.org/q/I5c01dfcffc6e56163aba03428e21fedee8cc7… [19] https://review.trustedfirmware.org/q/I284ee7fe611c4c9861696fde62f796e6fae6d… [20] https://review.trustedfirmware.org/q/Ifb736adf8f06bf6202784bdeac51c02512519… [21] https://review.trustedfirmware.org/q/I6240d263fb5d153721b5b84a37df2f24e3d02… [22] https://review.trustedfirmware.org/q/I2436b11a36be204d549522f1176fcd49658c0… [23] https://review.trustedfirmware.org/q/Ie465328e87754a1ec511a2f77243b4b0b0913… [24] https://review.trustedfirmware.org/q/I83710d8475a4a55046cf2eb6d16cd27b8ef0f… [25] https://review.trustedfirmware.org/q/I215a84bd2c91e33703349c41fc59f654f7764… [26] https://review.trustedfirmware.org/q/I9582c7405db6862e77db240822e241d408296… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.42/change-log.html Thanks, TF-A LTS team

1 month, 3 weeks

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Trusted Firmware-A LTS v2.10.29 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.29 is now available. This release contains the following patches: 0876588cd feat(locks): add bitlock [1] ee14acb14 feat(locks): add non-blocking spinlock_try() API [2] 7f53a3bcf fix(locks): mark spin_trylock as a public function [3] 528516d6e refactor(cpus): make errata reporting more generic [4] d70578f82 perf(cpus): reduce the footprint of errata reporting [5] 3eb1d91fc fix(cpus): enable Neoverse-V2 external LLC support [6] 3759bec84 fix(security): add workaround for CVE-2025-0647 [7] cc3fb61cf fix(security): add CVE-2025-0647 for Cortex-A710 [8] ca4573799 fix(security): add CVE-2025-0647 for Cortex-X2 [9] b5c1f67ad fix(security): add CVE-2025-0647 for Cortex-X3 [10] c29605d74 fix(security): add CVE-2025-0647 for Cortex-X4 [11] 023107645 fix(security): add CVE-2025-0647 for Cortex-X925 [12] 79cc92f6f fix(security): add CVE-2025-0647 for Neoverse-N2 [13] 5573859bc fix(security): add CVE-2025-0647 for Neoverse-V2 [14] 722fa1ee2 fix(security): add CVE-2025-0647 for Neoverse-V3 [15] 387e7e470 fix(security): add CVE-2025-0647 for C1-Ultra [16] [1] https://review.trustedfirmware.org/q/I3eb0f29bbccefe6c0f69061aa701187a6364d… [2] https://review.trustedfirmware.org/q/I9483206952d1a34dc245ebf69e80c3645b658… [3] https://review.trustedfirmware.org/q/Id264a36490707a9377a221ed2b5bd27ca90bf… [4] https://review.trustedfirmware.org/q/I83710d8475a4a55046cf2eb6d16cd27b8ef0f… [5] https://review.trustedfirmware.org/q/I215a84bd2c91e33703349c41fc59f654f7764… [6] https://review.trustedfirmware.org/q/I9582c7405db6862e77db240822e241d408296… [7] https://review.trustedfirmware.org/q/I5e7589afbeb69ebb79c01bec80e29f572aff3… [8] https://review.trustedfirmware.org/q/I522dedfffd3108f7a94df1ce2cabd742ce682… [9] https://review.trustedfirmware.org/q/Idba607340d944a6387759c856e8eacc967e0e… [10] https://review.trustedfirmware.org/q/Ic276befafc1ca0b456826532437ca453eb771… [11] https://review.trustedfirmware.org/q/I585a7ea516515fe16a3eca907695728068cef… [12] https://review.trustedfirmware.org/q/I4c1ac2be3620566813c90f5815ffcc7205bb5… [13] https://review.trustedfirmware.org/q/I366c2683cca22403d33f0761487e1ffa62e96… [14] https://review.trustedfirmware.org/q/I7ec215a9dd168eb045366b589a02b54148f58… [15] https://review.trustedfirmware.org/q/Ic52ad93474c5f81e01eb4839ece726c84c334… [16] https://review.trustedfirmware.org/q/I506007ec8702b183e377be50eede72d6803b3… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.29/change-log.html Thanks, TF-A LTS team

1 month, 3 weeks

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Proposal: Introduction of a standardized SMC Argument Validation Framework

by Sandrine Bailleux

Hi all, I am sending the email below on behalf on Kenneth Kabogo, who unfortunately is facing issues with the mailing list. Regards, Sandrine Afsa ---- Dear TF-A Maintainers, I am proposing the introduction of a standardized SMC Argument Validation Framework into the TF-A codebase. Over the past several weeks of security auditing across multiple platform ports, I have identified a recurring architectural failure mode termed "Privilege-Blind Forwarding" (PBF). This occurs when an EL3 handler receives a non-secure physical address and forwards it to a secure memory operation without re-validating the range against the platform's current security state (GPT/RMM). Furthermore, there is a widespread Structural TOCTOU (Double-Fetch) vulnerability in many SiP ports where handlers validate arguments but later re-fetch them from non-secure memory, allowing a malicious caller to swap addresses mid-execution. The proposed framework addresses these via an Atomic Shadow-Copy design pattern, requiring all SMC arguments to be unmarshaled into EL3 registers/memory once before validation. The 3-part prototype and migration guide are available for review on Gerrit: Framework Hardening (Core Logic): https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/47441 Architectural Guidance (Documentation): https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/47465 Arm Platform Demonstration (Migration Guide): https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/47466 I look forward to the community's feedback on this architectural shift. Best regards, Kenneth Kabogo

1 month, 3 weeks

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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 3 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 3 of 3 defect(s) ** CID 501374: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 308 in mhu_send_signal_poll_loop() _____________________________________________________________________________________________ *** CID 501374: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 308 in mhu_send_signal_poll_loop() 302 mhu_get_num_mhu_channels(mhu_recv_device, type); 303 uint32_t mhu_err; 304 uint32_t send_signal; 305 uint32_t recv_signal; 306 307 /* Signal using the last channel */ >>> CID 501374: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "send_num_channels - 1U", where "send_num_channels" is known to be equal to 0, underflows the type of "send_num_channels - 1U", which is type "unsigned int". 308 mhu_err = mhu_channel_send(mhu_send_device, send_num_channels - 1, 309 MHU_NOTIFY_VALUE, type); 310 if (mhu_err != 0) { 311 return mhu_err; 312 } 313 ** CID 501373: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 379 in mhu_message_is_available() _____________________________________________________________________________________________ *** CID 501373: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 379 in mhu_message_is_available() 373 { 374 const uint32_t num_channels = 375 mhu_get_num_mhu_channels(mhu_recv_device, type); 376 uint32_t mhu_err; 377 uint32_t value; 378 >>> CID 501373: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "num_channels - 1U", where "num_channels" is known to be equal to 0, underflows the type of "num_channels - 1U", which is type "unsigned int". 379 mhu_err = mhu_channel_receive_device_receive( 380 mhu_recv_device, num_channels - 1, &value, type); 381 if (mhu_err != 0) { 382 return mhu_err; 383 } 384 ** CID 501372: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 359 in mhu_recv_signal_poll_loop() _____________________________________________________________________________________________ *** CID 501372: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 359 in mhu_recv_signal_poll_loop() 353 return mhu_err; 354 } 355 } 356 357 /* Wait for next sender transfer */ 358 do { >>> CID 501372: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "recv_num_channels - 1U", where "recv_num_channels" is known to be equal to 0, underflows the type of "recv_num_channels - 1U", which is type "unsigned int". 359 mhu_err = mhu_channel_receive_device_receive( 360 mhu_recv_device, recv_num_channels - 1, &recv_signal, 361 type); 362 if (mhu_err != 0) { 363 return mhu_err; 364 } ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

1 month, 3 weeks

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Trusted Firmware-A LTS v2.10.28 Release Announcement

by svc_openci_enginfra＠arm.com

2 months

1
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