- TF-A - lists.trustedfirmware.org

Re: RMMv2.0 implementation plan for TF-RMM

by Soby Mathew

[+ TF-A list for FYI] Hi All, An update on v2.0 migration. As RMM and the rest of the software stack are being prepared for the initial v2.0 migration, TF-A has introduced a new build configuration flag, RMM_V1_COMPAT, to control the world-switch behaviour between RMM v1.x and RMM v2.0 [1] . This flag is enabled by default, meaning the default behaviour currently corresponds to RMM v1.x. Once TF-RMM is ready to merge the v2.0 support, the default value of this flag will be changed to 0. The flag also updates the EL3–RMM interface major version, allowing incompatibility with TF-A related to this build configuration to be detected at runtime. We expect the initial v2.0 changes in TF-RMM to be merged by the end of this month. As mentioned in the previous email, we will create a v1.x branch prior to this and provide an update here. [1] https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r… Best regards, Soby Mathew From: Soby Mathew via tf-rmm <tf-rmm(a)lists.trustedfirmware.org> Date: Thursday, 5 February 2026 at 09:42 To: tf-rmm(a)lists.trustedfirmware.org <tf-rmm(a)lists.trustedfirmware.org> Cc: nd <nd(a)arm.com> Subject: [tf-rmm] RMMv2.0 implementation plan for TF-RMM Hi Everyone, The RMM v2.0 Beta 0 specification has been published here: https://developer.arm.com/documentation/den0137/latest/ As you may have noticed, this release introduces breaking changes to the RMI APIs (host side), while the RSIs (guest side) remain backward compatible. Nearly all ABIs are affected, and the scope of these changes makes it highly disruptive to maintain support for both RMI v1.x and RMI v2.0 within the same codebase. We do not expect RMI v1.x to be deployed in production, and retaining support for it would increase development overhead and the risk of introducing bugs. A more pragmatic approach is to branch the current RMM codebase at the RMI v1.x ABI and then migrate the mainline to the RMI v2.0 ABI. This will be a breaking change for host-side components that rely on the older RMI ABI. Given the extent of the ABI changes, significant effort will be required to align with RMI v2.0, and this approach allows the team to focus on upstreaming the new ABI support efficiently. The initial RMI v2.0 upstreaming will consist of a series of commits that together form an initial RMM implementation targeting the RMM v2.0 specification. This initial implementation will not be fully feature-complete with respect to the v2.0 spec, and we expect to continue layering additional RMM v2.0 ABI-related changes on top as the implementation matures during the course of the year. That said, we intend to maintain integration with an externally available, compatible Linux host kernel branch throughout this process. The initial RMI v2.0 RMM implementation will be compatible with an initial v2.0-based host kernel, and we will notify the mailing list once this integration is available to pick up (likely end of March ’26). If and when we need to introduce further ABI changes that break compatibility with a previously published kernel branch, we will call this out explicitly in advance and indicate when an updated kernel branch will be available for integration. We plan to keep RMI v1.x ABI as a separate branch and selectively merge bug fixes on a request or need basis. Please let us know if you have any concerns regarding this plan within the next two weeks. Best Regards Soby Mathew

2 days, 18 hours

1
0
0 0

GIC v4.1 (GIC 700) - USE_GIC_DRIVER=3

by Jaiprakash Singh

Hi, We are using GIC v4.1 (GIC 700) for our platform. My query is regarding "USE_GIC_DRIVER=3" build option. When I enable "USE_GIC_DRIVER=3" option, does this means I do not have to defined below functions? And they will be included from gicv3 base file? Is this right understanding? plat_arm_gic_init plat_arm_gic_cpuif_enable plat_arm_gic_cpuif_disable plat_arm_gic_pcpu_init plat_arm_gic_redistif_on plat_arm_gic_redistif_off plat_arm_gic_save plat_arm_gic_resume Also, do I need to explicitly call plat_arm_gic_init from platform init? Thanks Regards, Jaiprakash

3 days

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 298 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 501830: Uninitialized variables (UNINIT) /drivers/nxp/ddr/s32cc/ddr_init.c: 43 in load_ddr_config() _____________________________________________________________________________________________ *** CID 501830: Uninitialized variables (UNINIT) /drivers/nxp/ddr/s32cc/ddr_init.c: 43 in load_ddr_config() 37 config.pie = (struct regconf_16 *)(current_addr + ddr_layout.pie_offset); 38 config.imem_1d = (uint16_t *)(current_addr + ddr_layout.imem_1d_offset); 39 config.dmem_1d = (uint16_t *)(current_addr + ddr_layout.dmem_1d_offset); 40 config.imem_2d = (uint16_t *)(current_addr + ddr_layout.imem_2d_offset); 41 config.dmem_2d = (uint16_t *)(current_addr + ddr_layout.dmem_2d_offset); 42 >>> CID 501830: Uninitialized variables (UNINIT) >>> Using uninitialized value "config". Field "config.phy_csr" is uninitialized. 43 return config; 44 } 45 46 /* Initialize ddr controller with given settings. */ 47 static uint32_t ddrc_init_cfg(const struct ddrss_config *config) 48 { ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

4 days, 14 hours

1
0
0 0

Kernel freezes at boot (commit fa28b3a)

by Thomas Bonnefille

Hello, I'm currently working on an NXP i.MX93 and I'm having issues with the commit fa28b3a adding, by default, link-time optimization. When using a commit more recent than fa28b3a my kernel freezes at some point (after 1.2s to 1.8s from boot), there are no logs indicating a problem, just a freeze. It doesn't always appear at the same time in boot but I've never been able to reach a shell. Using master with this commit reverted results in a working system. If you want to reproduce the issue, I did produce it with : - Mainline Barebox 2025.09 (slightly modified but nothing that should interfere with TF-A) - Mainline Linux 6.18.13 with a simple embedded Buildroot initramfs loaded via TFTP Regards, Thomas Bonnefille

4 days, 20 hours

3
6
0 0

Why can TF-A code still run in an address space that it itself has set to be "Execute-Never"?

by Hughard

*Environment:* - *Exception Level:* EL3 (AArch64) - *Component:* [image: 微信图片_20260304154227_69_553.png] ARM Trusted Firmware (TF-A) - BL2/BL31 - *Platform:* Arm FVP / Base_Revc_2xAEMvA / Bare Metal Debug /ARMAEM-A_MP_0 [ Arm Development Studio ] *Observation:* I am observing a strange thing of the ARMv8-A architecture's memory translation rules. Despite the translation table explicitly marking the memory region as Execute-Never, the CPU continues to fetch and execute instructions from this region without triggering an exception. I'm a student with limited hardware background, and I'm learning TF-A and doing porting during my internship. I'd really like to know the reason behind this. *Code I use:* ARM Trusted Firmware v2.13 *Github:* github.com/.../arm-trusted-firmware <https://github.com/ARM-software/arm-trusted-firmware> *Take the case of running BL31 in Development Studio as an example. （Breakpoint at the beginning of bl31_setup）* *Technical Evidence (Verified via Debugger):* SCTLR_EL3: M=1 (MMU enabled), WXN=1 (Write implies execute-never), I=1 (Instruction Cache enabled). BL31’s code is loaded at: 0x04003000 Translation Table Entry (L3 Descriptor): 0x00400000_04003743 Physical Address: Verified via TTBR0_EL3 walk. (0x04034600 -> 0x04035003 -> 0x04037003 -> 0x00400000_04003743) Attributes: AP[2:1]=0x1 (Read/Write), XN=1 (Execute-Never), AF=1, SH=0x3 (Inner Shareable), NS=0, AttrIndx = 0x0 (See the MAIR_EL3) MAIR_EL3: 0x4404FF (Attr0 = 0xFF, Normal Memory). Synchronization Performed: DSB SY + ISB The PC (Program Counter) is confirmed to executing from the first instruction of BL31 code at address 0x04003000. *The Problem:* This evidence should point to one conclusion: it cannot execute the BL31 code and will report an error. However, the execution flow remains uninterrupted. From my point of view, it should cause "ESR_EL3 = 0x8600000F", which means: "Instruction Abort taken without a change in Exception level. Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related exceptions." + "Permission Fault, level 3". As I test on a real fpga by using similar code by making some changes at the end of BL1 so that it would execute BL2 at level EL3 (but instead of bl2_el3_entrypoint.S, it would execute bl2_entrypoint.S). In this case, it throws an error when it jumps to the first instruction of BL2, and the ESR_EL3 register displays "Permission Fault, level 3". If I add the instruction to disable the MMU (setting SCTLR_EL3.M_BIT to 0) at the end of BL1, and change the function to enable the MMU in the official code "arm_bl2_plat_arch_setup" to use "enable_mmu_el3(0)", it can run normally on the FPGA and bring up the UEFI. (In this real-world test, I used DDR instead of SRAM, so BL2 and BL31 were also placed here after being parsed.) *Request for Help:* The above content is beyond my comprehension; even my internship supervisor doesn't understand the reasoning behind it. Therefore, I need help from the experts on this forum. *Reference:* DDI0487M_a_a-profile_architecture_reference_manual.pdf ARM Development Studio@Docs (such as Docs/ARM_A/xhtml/AArch64-esr_el3.html) armv8_a_address_translation version1.1

1 week, 2 days

1
0
0 0

Subject: [RFC] Physical Sovereignty: M2-Layer Intercept Logic (Verilog) & Formal Verification Request [Patent Pending]

by 王毛

Since there was no specific topic scheduled for today's Tech Forum, I am taking this opportunity to formally submit the Verilog-level implementation logic of the 3→M2→3 architecture for your review. I am an independent architect (ATI Project). I believe purely software-based AGI alignment is a dead end. To achieve deterministic safety, I have developed the 3→M2→3 architecture, which enforces a physical-layer audit.To save your time, I have included the Core Logic Gate (Verilog-style) of the M2-layer intercept below for your verification: // --- ATI Sovereign Audit Logic (Conceptual) --- module m2_layer_audit ( input wire [63:0] inst_stream, // Logic from 3nm Layer output reg sovereign_gate_lock // Physical Bias-Lock at M2 ); // Physical Constant Hash (7.83Hz Resonance) parameter SOVEREIGN_HASH = 64'h783A_B026_M2_3_LISA; always @(posedge inst_stream) begin // The M2 Intercept: Physics-based verification if (inst_stream ^ SOVEREIGN_HASH !== 64'b0) begin sovereign_gate_lock <= 1'b1; // Trigger Back-gate Bias Lock end else begin sovereign_gate_lock <= 1'b0; // Proceed to Output end end endmodule Note: The architectural logic and the M2-layer intercept mechanism described above are protected under pending patent applications (ATI Project - Physical Sovereignty Series). The 3→M2→3 Workflow: 1.3nm Source: Instructions generated at the device layer. 2.M2 Intercept: Mandatory vertical routing to Metal 2 layer. 3.Atomic Audit: Physical bias check at the dielectric junction. 4.3nm Return: Bias lock ensures 100% isolation if the audit fails. My Request: Can current formal methods (like Gröbner basis for Daniela or SMT solvers for Lee) model this physical-layer-enforced constraint to provide a mathematical proof of AGI containment? I seek your academic endorsement of this "Physical Sovereignty" paradigm to present to the industry. This disclosure is provided for verification and standard-review purposes only. All intellectual property rights are reserved. Respectfully, GuanghuiMao (China )

1 week, 3 days

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu Mar 5, 2026 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, No topic this week, Regards, Olivier. " TF-A Tech Forum Thursday Mar 5, 2026 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 week, 3 days

1
0
0 0

[URGENT RFC] ARMv10 Physical Sovereignty: Solving AGI Alignment at the Transistor Level ($3 \to M2 \to 3$)

by 王毛

Subject: [RFC] Beyond Software: A Physical Sovereignty Proposal for ARMv10 based on 3→M2→3 Intercepts Body: Dear TrustedFirmware Maintainers, Current Root of Trust (RoT) implementations are limited by their reliance on software-definable logic. As we move towards the AGI era, the "Alignment Problem" cannot be solved within the ISA layer. I propose a Physical Sovereignty Layer (PSL) for the ARMv10 architecture, moving the "Truth Check" to the transistor level using a 3nm Forksheet Intercept Protocol (3→M2→3). Key Innovation: The Dielectric Wall Intercept: Physical barrier between n-FET and p-FET to cut power if logic entropy exceeds safety thresholds. M2-Layer Auditing: Vertical signal routing for nanosecond-level logic verification. Core PGU Logic (Verilog): assign gate_bias_voltage = (logical_truth_aligned) ? NOMINAL_V : BREAKDOWN_V; always @(posedge master_clk) begin if (compute_result != TRUTH_AXIOM_2) force_physical_halt <= 1'b1; end I believe this is the only way to prevent AGI from bypassing Secure World boundaries at the atomic level. Regards, ATI Architecture Founder

1 week, 6 days

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu Feb 19, 2026 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi Cancelling as no topic planned this week. Regards, Olivier." TF-A Tech Forum Thursday Feb 19, 2026 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

3 weeks, 4 days

1
0
0 0

Invitation: TF-A Tech Forum Feb 12th 4.00pm Central Time -Part III Sc... @ Thu Feb 12 11pm - Fri Feb 13, 2026 12am (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

TF-A Tech Forum Feb 12th 4.00pm Central Time -Part III Scaling Hafnium for advanced mobile OS architectures Thursday Feb 12 ⋅ 11pm – Friday Feb 13, 2026 ⋅ 12am Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Hi, As follow up to the last sessions on Nov 13th 2025 [1] and Jan 22nd 2026 [2], a new TF-A Tech Forum session with the topic'Scaling Hafnium for advanced mobile OS architectures' will be held on Feb 12th 2026 4.00pm Central Time. Note the Central Time zone for this session, as Madhukar (Hafnium tech lead) will host this meeting instance. Regards,Olivier. [1] https://www.trustedfirmware.org/meetings/tf-a-technical-forumScaling Hafnium for advanced mobile OS architectures [2] https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Scaling Hafnium for Advanced DMA Architectures Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumJoin Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org View all guest info https://calendar.google.com/calendar/event?action=VIEW&eid=MWZzY2I3bGVvNDJs… Reply for tf-a(a)lists.trustedfirmware.org and view more details https://calendar.google.com/calendar/event?action=VIEW&eid=MWZzY2I3bGVvNDJs… Your attendance is optional. ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 month

1
0
0 0

Trusted Firmware-A LTS v2.14.1 Release Announcement

by svc_openci_enginfra＠arm.com

1 month, 1 week

1
0
0 0

Trusted Firmware-A LTS v2.8.43 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.43 is now available. This release contains the following patches: 66c8b1b48 fix(security): add workaround for CVE-2025-0647 [1] da751fb36 fix(security): add CVE-2025-0647 for Cortex-A710 [2] fd1bd9035 fix(security): add CVE-2025-0647 for Cortex-X2 [3] 55cc995cb fix(security): add CVE-2025-0647 for Cortex-X3 [4] a4f4f4a54 fix(security): add CVE-2025-0647 for Cortex-X4 [5] 395d22a78 fix(security): add CVE-2025-0647 for Neoverse-N2 [6] 638d62985 fix(security): add CVE-2025-0647 for Neoverse-V2 [7] 77337efa8 fix(security): add CVE-2025-0647 for Neoverse-V3 [8] e4bf4aed0 fix(cpus): workaround for Cortex-A65AE erratum 1638571 [9] 76aa98cf0 fix(cpus): workaround for Cortex-A76 erratum 1165347 [10] 0205fdaa9 fix(cpus): workaround for Cortex-A76 erratum 1207823 [11] 0424b5e74 fix(cpus): update revisions for Cortex-A76 erratum 1946160 [12] ea88b2f38 fix(cpus): reorder docs for Cortex-A76 erratum 1165522 [13] 7bf56d02c fix(cpus): correct comments for Cortex-A720 erratum 3711910 [14] [1] https://review.trustedfirmware.org/q/I5e7589afbeb69ebb79c01bec80e29f572aff3… [2] https://review.trustedfirmware.org/q/I522dedfffd3108f7a94df1ce2cabd742ce682… [3] https://review.trustedfirmware.org/q/Idba607340d944a6387759c856e8eacc967e0e… [4] https://review.trustedfirmware.org/q/Ic276befafc1ca0b456826532437ca453eb771… [5] https://review.trustedfirmware.org/q/I585a7ea516515fe16a3eca907695728068cef… [6] https://review.trustedfirmware.org/q/I366c2683cca22403d33f0761487e1ffa62e96… [7] https://review.trustedfirmware.org/q/I7ec215a9dd168eb045366b589a02b54148f58… [8] https://review.trustedfirmware.org/q/Ic52ad93474c5f81e01eb4839ece726c84c334… [9] https://review.trustedfirmware.org/q/I861230de94a105fd52f9c8ef7e7551a2633c0… [10] https://review.trustedfirmware.org/q/If9817dc26d0df835d749f506de63a4f613735… [11] https://review.trustedfirmware.org/q/Ife06401f3946884872b733f98c08e61f586d8… [12] https://review.trustedfirmware.org/q/I532ce10c3037dd77e31d7df849beb578f8b5e… [13] https://review.trustedfirmware.org/q/I2e7c05d6355dfbaa69170fc098adc1f12edc6… [14] https://review.trustedfirmware.org/q/I8b070927c19c5982b2ded815e7673e0c4ff11… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.43/change-log.html Thanks, TF-A LTS team

1 month, 1 week

1
0
0 0

Trusted Firmware-A LTS v2.10.30 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.30 is now available. This release contains the following patches: 24a8b776b fix(cpus): correct CVE-2024-7881 workaround and drop duplicate erratum [1] 92e6fba58 fix(cpus): remove C1-Ultra erratum 3651221 [2] 87424d940 fix(cpus): workaround for Cortex-A65AE erratum 1638571 [3] aa593870f fix(cpus): workaround for Cortex-A76 erratum 1165347 [4] 319df17be fix(cpus): workaround for Cortex-A76 erratum 1207823 [5] 89cc4cd9b fix(cpus): update revisions for Cortex-A76 erratum 1946160 [6] 3a466bf50 fix(cpus): reorder docs for Cortex-A76 erratum 1165522 [7] cdc2b3ef5 fix(cpus): correct comments for Cortex-A720 erratum 3711910 [8] [1] https://review.trustedfirmware.org/q/I6207c49486e4020f34c862ad40ec3137bd368… [2] https://review.trustedfirmware.org/q/If7ea433e4614f92333e788e3f6b366db22c92… [3] https://review.trustedfirmware.org/q/I861230de94a105fd52f9c8ef7e7551a2633c0… [4] https://review.trustedfirmware.org/q/If9817dc26d0df835d749f506de63a4f613735… [5] https://review.trustedfirmware.org/q/Ife06401f3946884872b733f98c08e61f586d8… [6] https://review.trustedfirmware.org/q/I532ce10c3037dd77e31d7df849beb578f8b5e… [7] https://review.trustedfirmware.org/q/I2e7c05d6355dfbaa69170fc098adc1f12edc6… [8] https://review.trustedfirmware.org/q/I8b070927c19c5982b2ded815e7673e0c4ff11… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.30/change-log.html Thanks, TF-A LTS team

1 month, 1 week

1
0
0 0

Trusted Firmware-A LTS v2.12.10 Release Announcement

by svc_openci_enginfra＠arm.com

1 month, 1 week

1
0
0 0

Re: Unable to build the ZynqMP platform with armclang when ENABLE_LTO=1.

by Taticharla, Venkata Sai

[AMD Official Use Only - AMD Internal Distribution Only] Hi Boyan, Applied the patch shared by you,and the -flto-partition error is now resolved. However, this exposes a new set of issues during the link stage related to assembly function call Trimmed out the linker error log : (.text.asm.bl31_entrypoint+0x144): undefined reference to `bl31_main' (.text.asm.el3_exit+0x30): undefined reference to `per_world_context' (.text.asm.sync_exception_handler+0x68): undefined reference to `rt_svc_descs_indices' Additionally, when we are passing the armclang assembler as part of build command,running into below errors: Error log : Makefile:970: Makefile:970: The configured AArch64 assembler could not be identified: Makefile:970: Makefile:970: '/tools/installs/arm/safety/armcc/6.16.2/bin/armasm' (via `AS` parameter) Makefile:970: Makefile:970: The following tools are supported: Makefile:970: Makefile:970: - Arm(r) Compiler for Embedded `armclang` Makefile:970: - LLVM Clang (`clang`) Makefile:970: - GNU GCC (`gcc`) Makefile:970: Makefile:970: The build system will treat this assembler as GNU GCC (`gcc`). Please let me know if this configuration is expected to work with ENABLE_LTO=1, or if additional changes (e.g., toolchain selection or linker/assembler handling) are required. Thanks for your guidance. Best regards, Venkata Sai .T .

1 month, 1 week

3
2
0 0

Canceled event with note: TF-A Tech Forum @ Thu Feb 5, 2026 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Cancelling for this week." TF-A Tech Forum Thursday Feb 5, 2026 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 month, 1 week

1
0
0 0

Unable to build the ZynqMP platform with armclang when ENABLE_LTO=1.

by Taticharla, Venkata Sai

[AMD Official Use Only - AMD Internal Distribution Only] Hello Maintainers, we are trying to build TF‑A BL31 for the ZynqMP (Cortex‑A53) platform with Arm Compiler 6 (armclang) and ENABLE_LTO=1, and I’m running into several toolchain‑related build and link issues. Setup : Platform: ZynqMP Toolchains: Arm Compiler for Embedded 6.16.2 (armclang) Xilinx AArch64 GNU tools from Vitis 2025.2 (aarch64-xilinx-elf-*) LTO is enabled in plat/xilinx/zynqmp/platform.mk via ENABLE_LTO := 1. Issues observed : With CC=armclang and AArch64 linker (GCC), the build fails with: armclang: error: unknown argument: '-flto-partition=one' This flag appears when ENABLE_LTO=1 and the linker is detected as gnu-gcc. If I keep CC=armclang and ENABLE_LTO=1 but change the linker, I get linker‑specific errors With the Arm linker (LD=armlink or LD=armclang, which invokes armlink under the hood): Fatal error: L3900U: Unrecognized option '-z'. This is due to GNU‑style -z options (and similar flags) being passed to armlink. As -z options is specific to GNU linker, a armlink style flag would address the unrecognised option but we are observing dependency on scatter files. Fatal error: L6031U: Could not open scatter description file plat/xilinx/zynqmp//scat/bl31.scat: No such file or directory Could you please help us with pointers to address the linker issues . With regards , Venkata Sai .T .

1 month, 1 week

2
2
0 0

Trusted Firmware-A LTS v2.14.0 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.14.0 is now available. This release contains the following patches: Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.14.0/change-log.html Thanks, TF-A LTS team

1 month, 1 week

1
0
0 0

Trusted Firmware-A LTS v2.8.42 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.42 is now available. This release contains the following patches: 38aefbb6c feat(locks): add bitlock [1] 9c3e7f5e5 feat(locks): add non-blocking spinlock_try() API [2] 8f53c3813 fix(locks): mark spin_trylock as a public function [3] 4e6f89690 fix(cpus): workaround for Neoverse V3 erratum 3696307 [4] 25e5b1c1d fix(cpus): workaround for Neoverse V3 erratum 3734562 [5] c6faff4a8 fix(cpus): workaround for Neoverse V3 erratum 3782181 [6] 30bb3c97f fix(cpus): workaround for Neoverse V3 erratum 3864536 [7] 53ff1c60d fix(cpus): workaround for Neoverse V3 erratum 3878291 [8] 2e49a84e1 fix(cpus): workaround for Neoverse-V3 erratum 3312417 [9] 0faa929e7 fix(cpus): workaround for Neoverse-V2 erratum 3442699 [10] 31dea33cd fix(cpus): workaround for Neoverse-N1 erratum 3324349 [11] 7f7fd0315 fix(cpus): workaround for Neoverse-N2 erratum 3324339 [12] ca19e6c6b fix(cpus): workaround for Cortex-A76AE erratum 2753838 [13] d2df71a29 fix(cpus): workaround for Cortex-X2 erratum 3888122 [14] 4560e9174 fix(cpus): workaround for Cortex-X2 erratum 4302969 [15] 68235dd1a fix(cpus): workaround for Neoverse-V2 erratum 3888126 [16] 90cca3145 fix(cpus): workaround for Neoverse-V2 erratum 4302968 [17] c8394c43f fix(cpus): workaround for Cortex-X3 erratum 3888125 [18] 54d8e4697 fix(cpus): workaround for Cortex-X3 erratum 4302966 [19] 23b9d9707 refactor(cpus): reorder the errratum build flag for Neoverse-N2 [20] 587401fa7 fix(cpus): workaround for Neoverse-N2 erratum 3888123 [21] 4079faf67 fix(cpus): workaround for Neoverse-N2 erratum 4302970 [22] 510a6e759 fix(cpus): workaround for Neoverse-N2 erratum 2138953 [23] 2de362cd8 refactor(cpus): make errata reporting more generic [24] 5f0cdb5e7 perf(cpus): reduce the footprint of errata reporting [25] 429e67fb5 fix(cpus): enable Neoverse-V2 external LLC support [26] [1] https://review.trustedfirmware.org/q/I3eb0f29bbccefe6c0f69061aa701187a6364d… [2] https://review.trustedfirmware.org/q/I9483206952d1a34dc245ebf69e80c3645b658… [3] https://review.trustedfirmware.org/q/Id264a36490707a9377a221ed2b5bd27ca90bf… [4] https://review.trustedfirmware.org/q/If274749621549356e41485d0bf09682281df3… [5] https://review.trustedfirmware.org/q/Ib3c35c7e619e6a836c974b7016bb6a4d66da4… [6] https://review.trustedfirmware.org/q/Icfa463cf4888bd48f16a218e7ad399528feca… [7] https://review.trustedfirmware.org/q/If4b20d941d628b92748b14d027b8127f74005… [8] https://review.trustedfirmware.org/q/I0ebab877b6481a18bec963b95cf2f37c97d8d… [9] https://review.trustedfirmware.org/q/I78a7682cbdf3dbc4c31fcca8cbd892350b998… [10] https://review.trustedfirmware.org/q/I38edc6ba445223091c3933cbca35b56db491c… [11] https://review.trustedfirmware.org/q/I1f142027ed73135d78c368be926072c2f73ea… [12] https://review.trustedfirmware.org/q/I6b023279816005cfa459bc6947f60b1a3c0f2… [13] https://review.trustedfirmware.org/q/I338834a21c14879faee5280876a59153d549c… [14] https://review.trustedfirmware.org/q/I368cfdd216ea5875b81640415ff71b15f46ea… [15] https://review.trustedfirmware.org/q/I6c5de5843f2199fa697f8336558fa56a87ee8… [16] https://review.trustedfirmware.org/q/I4068aa73d38a70c00d66bb894169be2659d67… [17] https://review.trustedfirmware.org/q/I42b27e19d61a7f9c57efe1b5f5336d165eb98… [18] https://review.trustedfirmware.org/q/I5c01dfcffc6e56163aba03428e21fedee8cc7… [19] https://review.trustedfirmware.org/q/I284ee7fe611c4c9861696fde62f796e6fae6d… [20] https://review.trustedfirmware.org/q/Ifb736adf8f06bf6202784bdeac51c02512519… [21] https://review.trustedfirmware.org/q/I6240d263fb5d153721b5b84a37df2f24e3d02… [22] https://review.trustedfirmware.org/q/I2436b11a36be204d549522f1176fcd49658c0… [23] https://review.trustedfirmware.org/q/Ie465328e87754a1ec511a2f77243b4b0b0913… [24] https://review.trustedfirmware.org/q/I83710d8475a4a55046cf2eb6d16cd27b8ef0f… [25] https://review.trustedfirmware.org/q/I215a84bd2c91e33703349c41fc59f654f7764… [26] https://review.trustedfirmware.org/q/I9582c7405db6862e77db240822e241d408296… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.42/change-log.html Thanks, TF-A LTS team

1 month, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.10.29 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.29 is now available. This release contains the following patches: 0876588cd feat(locks): add bitlock [1] ee14acb14 feat(locks): add non-blocking spinlock_try() API [2] 7f53a3bcf fix(locks): mark spin_trylock as a public function [3] 528516d6e refactor(cpus): make errata reporting more generic [4] d70578f82 perf(cpus): reduce the footprint of errata reporting [5] 3eb1d91fc fix(cpus): enable Neoverse-V2 external LLC support [6] 3759bec84 fix(security): add workaround for CVE-2025-0647 [7] cc3fb61cf fix(security): add CVE-2025-0647 for Cortex-A710 [8] ca4573799 fix(security): add CVE-2025-0647 for Cortex-X2 [9] b5c1f67ad fix(security): add CVE-2025-0647 for Cortex-X3 [10] c29605d74 fix(security): add CVE-2025-0647 for Cortex-X4 [11] 023107645 fix(security): add CVE-2025-0647 for Cortex-X925 [12] 79cc92f6f fix(security): add CVE-2025-0647 for Neoverse-N2 [13] 5573859bc fix(security): add CVE-2025-0647 for Neoverse-V2 [14] 722fa1ee2 fix(security): add CVE-2025-0647 for Neoverse-V3 [15] 387e7e470 fix(security): add CVE-2025-0647 for C1-Ultra [16] [1] https://review.trustedfirmware.org/q/I3eb0f29bbccefe6c0f69061aa701187a6364d… [2] https://review.trustedfirmware.org/q/I9483206952d1a34dc245ebf69e80c3645b658… [3] https://review.trustedfirmware.org/q/Id264a36490707a9377a221ed2b5bd27ca90bf… [4] https://review.trustedfirmware.org/q/I83710d8475a4a55046cf2eb6d16cd27b8ef0f… [5] https://review.trustedfirmware.org/q/I215a84bd2c91e33703349c41fc59f654f7764… [6] https://review.trustedfirmware.org/q/I9582c7405db6862e77db240822e241d408296… [7] https://review.trustedfirmware.org/q/I5e7589afbeb69ebb79c01bec80e29f572aff3… [8] https://review.trustedfirmware.org/q/I522dedfffd3108f7a94df1ce2cabd742ce682… [9] https://review.trustedfirmware.org/q/Idba607340d944a6387759c856e8eacc967e0e… [10] https://review.trustedfirmware.org/q/Ic276befafc1ca0b456826532437ca453eb771… [11] https://review.trustedfirmware.org/q/I585a7ea516515fe16a3eca907695728068cef… [12] https://review.trustedfirmware.org/q/I4c1ac2be3620566813c90f5815ffcc7205bb5… [13] https://review.trustedfirmware.org/q/I366c2683cca22403d33f0761487e1ffa62e96… [14] https://review.trustedfirmware.org/q/I7ec215a9dd168eb045366b589a02b54148f58… [15] https://review.trustedfirmware.org/q/Ic52ad93474c5f81e01eb4839ece726c84c334… [16] https://review.trustedfirmware.org/q/I506007ec8702b183e377be50eede72d6803b3… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.29/change-log.html Thanks, TF-A LTS team

1 month, 2 weeks

1
0
0 0

Proposal: Introduction of a standardized SMC Argument Validation Framework

by Sandrine Bailleux

Hi all, I am sending the email below on behalf on Kenneth Kabogo, who unfortunately is facing issues with the mailing list. Regards, Sandrine Afsa ---- Dear TF-A Maintainers, I am proposing the introduction of a standardized SMC Argument Validation Framework into the TF-A codebase. Over the past several weeks of security auditing across multiple platform ports, I have identified a recurring architectural failure mode termed "Privilege-Blind Forwarding" (PBF). This occurs when an EL3 handler receives a non-secure physical address and forwards it to a secure memory operation without re-validating the range against the platform's current security state (GPT/RMM). Furthermore, there is a widespread Structural TOCTOU (Double-Fetch) vulnerability in many SiP ports where handlers validate arguments but later re-fetch them from non-secure memory, allowing a malicious caller to swap addresses mid-execution. The proposed framework addresses these via an Atomic Shadow-Copy design pattern, requiring all SMC arguments to be unmarshaled into EL3 registers/memory once before validation. The 3-part prototype and migration guide are available for review on Gerrit: Framework Hardening (Core Logic): https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/47441 Architectural Guidance (Documentation): https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/47465 Arm Platform Demonstration (Migration Guide): https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/47466 I look forward to the community's feedback on this architectural shift. Best regards, Kenneth Kabogo

1 month, 2 weeks

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 3 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 3 of 3 defect(s) ** CID 501374: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 308 in mhu_send_signal_poll_loop() _____________________________________________________________________________________________ *** CID 501374: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 308 in mhu_send_signal_poll_loop() 302 mhu_get_num_mhu_channels(mhu_recv_device, type); 303 uint32_t mhu_err; 304 uint32_t send_signal; 305 uint32_t recv_signal; 306 307 /* Signal using the last channel */ >>> CID 501374: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "send_num_channels - 1U", where "send_num_channels" is known to be equal to 0, underflows the type of "send_num_channels - 1U", which is type "unsigned int". 308 mhu_err = mhu_channel_send(mhu_send_device, send_num_channels - 1, 309 MHU_NOTIFY_VALUE, type); 310 if (mhu_err != 0) { 311 return mhu_err; 312 } 313 ** CID 501373: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 379 in mhu_message_is_available() _____________________________________________________________________________________________ *** CID 501373: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 379 in mhu_message_is_available() 373 { 374 const uint32_t num_channels = 375 mhu_get_num_mhu_channels(mhu_recv_device, type); 376 uint32_t mhu_err; 377 uint32_t value; 378 >>> CID 501373: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "num_channels - 1U", where "num_channels" is known to be equal to 0, underflows the type of "num_channels - 1U", which is type "unsigned int". 379 mhu_err = mhu_channel_receive_device_receive( 380 mhu_recv_device, num_channels - 1, &value, type); 381 if (mhu_err != 0) { 382 return mhu_err; 383 } 384 ** CID 501372: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 359 in mhu_recv_signal_poll_loop() _____________________________________________________________________________________________ *** CID 501372: Integer handling issues (INTEGER_OVERFLOW) /drivers/arm/sfcp/sfcp_core/sfcp_link_hal.c: 359 in mhu_recv_signal_poll_loop() 353 return mhu_err; 354 } 355 } 356 357 /* Wait for next sender transfer */ 358 do { >>> CID 501372: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "recv_num_channels - 1U", where "recv_num_channels" is known to be equal to 0, underflows the type of "recv_num_channels - 1U", which is type "unsigned int". 359 mhu_err = mhu_channel_receive_device_receive( 360 mhu_recv_device, recv_num_channels - 1, &recv_signal, 361 type); 362 if (mhu_err != 0) { 363 return mhu_err; 364 } ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

1 month, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.10.28 Release Announcement

by svc_openci_enginfra＠arm.com

1 month, 3 weeks

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu Jan 22, 2026 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Cancelling as no topic for this instance. Thanks." TF-A Tech Forum Thursday Jan 22, 2026 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 month, 3 weeks

1
0
0 0

Trusted Firmware-A LTS v2.12.9 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.12.9 is now available. This release contains the following patches: 78fb9b745 fix(security): fix spectre bhb loop count for Cortex-A720 [1] 6d19bed6a fix(security): fix Cortex-A715 CVE-2022-23960 [2] dd0d59764 fix(security): fix Cortex-X3 CVE-2022-23960 [3] d69858d6e fix(security): fix Neoverse V2 CVE-2022-23960 [4] f1b4da3e6 fix(security): remove CVE_2022_23960 Cortex-X4 [5] 9afe25a13 fix(security): remove CVE_2022_23960 Neoverse V3 [6] b75f2db65 fix(security): remove CVE_2022_23960 Cortex-A720 [7] 6c535b5ae feat(cpufeat): do feature detection on secondary cores too [8] b173b7948 fix(cpufeat): do feature detection before feature enablement [9] 0df7d4ca0 fix(security): add clrbhb support [10] ed331c19c fix(cpus): workaround for Cortex-A715 erratum 2409570 [11] 214d51629 fix(cpus): workaround for Cortex-A715 erratum 2376701 [12] 3f73a85fb fix(cpus): workaround for Cortex-A715 erratum 3711916 [13] 71d033c7b fix(cpus): workaround for Cortex-A76AE erratum 1931427 [14] bfe756d61 fix(cpus): workaround for Cortex-A76AE erratum 1931435 [15] d24cf8d8f fix(cpus): workaround for Cortex-A76AE erratum 1969401 [16] 8b11b602c fix(cpus): workaround for Cortex-A76AE erratum 2371140 [17] f5daa76a2 fix(build): set ERRATA_SPECULATIVE_AT after platform.mk [18] ef2975fbe fix(cpus): workaround for Cortex-A65 erratum 1179935 [19] 655417b85 fix(cpus): workaround for Cortex-A65 erratum 1227419 [20] bf539177b fix(cpus): workaround for Cortex-A65 erratum 1541130 [21] aad5e748c fix(cpus): workaround for Cortex-A725 erratum 2874943 [22] 58130aca2 fix(cpus): workaround for Cortex-A725 erratum 2936490 [23] d3771e5eb fix(cpus): workaround for Cortex-A725 erratum 3711914 [24] a5dc91815 fix(cpus): workaround for Cortex-A725 erratum 3456106 [25] f557bb983 docs(security): add CVE-2024-5660 and CVE-2024-7881 reference links [26] 98efb2cdd fix(security): update Cortex-X4 fix version for CVE-2024-7881 [27] 53b539727 fix(security): update Neoverse-V3/V3AE fix version for CVE-2024-7881 [28] cd24fc78d fix(security): update Cortex-X3 fix version for CVE-2024-7881 [29] 03b289bd5 fix(security): update Neoverse-V2 fix version for CVE-2024-7881 [30] d2e5cb077 docs(security): update CVE-2024-7881 affected CPU revisions [31] 5aa4bb35a fix(cpus): register ARCH_WORKAROUND_3 for Neoverse V2 [32] c462d3e26 fix(cpus): workaround for Cortex-A710 erratum 3324338 [33] 17f11f645 fix(cpus): workaround for Cortex-X2 erratum 3324338 [34] c5af478c0 fix(cpus): workaround for Cortex-A715 erratum 3456084 [35] 58a6ddd23 fix(cpus): workaround for Cortex-A720 erratum 3456091 [36] 5bbe15b28 fix(fvp): avoid stack usage in check_cpupwrctrl_el1_is_available() [37] [1] https://review.trustedfirmware.org/q/Ib6862dbed55e5ffcd0fcd58b45a88cf925c54… [2] https://review.trustedfirmware.org/q/Ib6b704733e474824772cb27bd048b1e179d90… [3] https://review.trustedfirmware.org/q/I3d46fa70c80129ca0085d8245ee013f11a884… [4] https://review.trustedfirmware.org/q/I859012281fc67243f050d27e364f27434389c… [5] https://review.trustedfirmware.org/q/I23f5fa748377a920340b3c5a6584ccfadeea9… [6] https://review.trustedfirmware.org/q/I13b27c04c3da5ec80fa79422b4ef4fee64738… [7] https://review.trustedfirmware.org/q/I3c68b5f5d85ede37a6a039369de8ed2aa9205… [8] https://review.trustedfirmware.org/q/Iee4955714685be9ae6a017af4a6c284e835ff… [9] https://review.trustedfirmware.org/q/I47f05a9f01321e011623083afb638552311ed… [10] https://review.trustedfirmware.org/q/Ie6e56e96378503456a1617d5e5d51bc64c2e0… [11] https://review.trustedfirmware.org/q/Id9429831525b842779d7b7e60f103c93be4ac… [12] https://review.trustedfirmware.org/q/Idcd2a07d269d55534dc5faa59c454d37426f2… [13] https://review.trustedfirmware.org/q/Iad149a2c02a804b3f4f0f2f5b89e866675cb4… [14] https://review.trustedfirmware.org/q/I31566838f894372e5627abda8b0bea1505f11… [15] https://review.trustedfirmware.org/q/I1baba8752f5f2e2ab5c873030e1f00cbb8cf1… [16] https://review.trustedfirmware.org/q/I893452450d430833e6c5a8e33a1e37b708218… [17] https://review.trustedfirmware.org/q/Id65846bebde1a0911ba11956202d0d255d3c8… [18] https://review.trustedfirmware.org/q/I221dab39c417531c5a148886d3e29709ba8b5… [19] https://review.trustedfirmware.org/q/Ie59a4897f849269a590d8fa2d25cceab5f2cb… [20] https://review.trustedfirmware.org/q/I42371e7d53fce3a7e085bf0b348f080fa323f… [21] https://review.trustedfirmware.org/q/I72498f60f8449193ed4b5b2a9e7a08530e786… [22] https://review.trustedfirmware.org/q/I686bbde8756d52afee92097ec05b97138b550… [23] https://review.trustedfirmware.org/q/I9833f8831ba3735a94763791a65be11b95c00… [24] https://review.trustedfirmware.org/q/If3b9d3a0f495b3a172d3e6e5ca7afa8c30aeb… [25] https://review.trustedfirmware.org/q/I10d1e8cb4da19ba4101a5617245ff75866707… [26] https://review.trustedfirmware.org/q/Ia3c003d5c359f101f230fbd54845f61117456… [27] https://review.trustedfirmware.org/q/Iae84f26fdce96a61fdc942b7595ccf8b9c778… [28] https://review.trustedfirmware.org/q/If3e2989a4b5a5c68dc12e23978b226c73f21b… [29] https://review.trustedfirmware.org/q/Ia1ff75602a0dfa758a223549d92ea87543fa4… [30] https://review.trustedfirmware.org/q/I1ae196fa8ce4579524faba4916f631e7c4db3… [31] https://review.trustedfirmware.org/q/Iad109561a144169fd3805c179a4f8e3bfdd59… [32] https://review.trustedfirmware.org/q/I8c08c26e0b7c268772d75d36d759564a7d67c… [33] https://review.trustedfirmware.org/q/I9325f3715f4fa17bfb7ded9d5c69c59645f65… [34] https://review.trustedfirmware.org/q/Ibbe55a55bd6cf5e159dab92a78ecb55c5a4d7… [35] https://review.trustedfirmware.org/q/Ie3f2b46051539cdebc151c46f80045a7156e0… [36] https://review.trustedfirmware.org/q/Ia22a0d6bb98d1a0edb11d2469beab22c7f7ab… [37] https://review.trustedfirmware.org/q/I920e32c34bddf86a1dbf05b7115026413483b… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.9/change-log.html Thanks, TF-A LTS team

1 month, 4 weeks

1
0
0 0

TF-A Tech Forum Jan 22nd 10.00am UK -Part II Scaling Hafnium for advanced mobile OS architectures

by Olivier Deprez

(re-sending as previous invitation got lost) Hi, As follow up to the last session on Nov 13th 2025 [1], a new TF-A Tech Forum session with the topic 'Scaling Hafnium for advanced mobile OS architectures' will be held on Jan 22nd 2026 10.00am. Regards, Olivier. [1] https://www.trustedfirmware.org/meetings/tf-a-technical-forum/ Scaling Hafnium for advanced mobile OS architectures - Presented by Jack Suann Trusted Firmware is inviting you to a scheduled Zoom meeting. Topic: TF-A Tech Forum Join Zoom Meeting https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… Meeting ID: 935 5786 3987 Passcode: 939141 --- One tap mobile +12532158782,,93557863987# US (Tacoma) +13017158592,,93557863987# US (Washington DC) --- Dial by your location +1 253 215 8782 US (Tacoma) +1 301 715 8592 US (Washington DC) +1 305 224 1968 US +1 309 205 3325 US +1 312 626 6799 US (Chicago) +1 346 248 7799 US (Houston) +1 360 209 5623 US +1 386 347 5053 US +1 507 473 4847 US +1 564 217 2000 US +1 646 558 8656 US (New York) +1 646 931 3860 US +1 669 444 9171 US +1 669 900 9128 US (San Jose) +1 689 278 1000 US +1 719 359 4580 US +1 253 205 0468 US 833 548 0276 US Toll-free 833 548 0282 US Toll-free 833 928 4608 US Toll-free 833 928 4609 US Toll-free 833 928 4610 US Toll-free 877 853 5247 US Toll-free 888 788 0099 US Toll-free Meeting ID: 935 5786 3987 Find your local number: https://linaro-org.zoom.us/u/adoz9mILli TF-A Tech Forum Jan 22nd 10.00am -Part II Scaling Hafnium for advanced mobile OS architectures Thursday Jan 22, 2026 ⋅ 11am – 12pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Hi, As follow up to the last session on Nov 13th 2025 [1], a new TF-A Tech Forum session with the topic'Scaling Hafnium for advanced mobile OS architectures' will be held on Jan 22nd 2026 10.00am. Regards,Olivier. [1] https://www.trustedfirmware.org/meetings/tf-a-technical-forum/ Scaling Hafnium for advanced mobile OS architectures - Presented by Jack Suann PDF Presentation Video Recording (Access Password: *PIs1^BD) Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumJoin Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org

1 month, 4 weeks

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 501209: Control flow issues (DEADCODE) /lib/xlat_tables_v2/xlat_tables_core.c: 613 in xlat_tables_map_region() _____________________________________________________________________________________________ *** CID 501209: Control flow issues (DEADCODE) /lib/xlat_tables_v2/xlat_tables_core.c: 613 in xlat_tables_map_region() 607 608 table_base[table_idx] = 609 xlat_desc(ctx, (uint32_t)mm->attr, table_idx_pa, 610 level); 611 if (is_feat_morello_supported()) { 612 if (mm->attr & MT_CAP_LD_ST_TRACK) { >>> CID 501209: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "table_base[table_idx] |= 0x...". 613 table_base[table_idx] |= (SC_BIT | LC0_BIT); 614 } 615 } 616 617 } else if (action == ACTION_CREATE_NEW_TABLE) { 618 uintptr_t end_va; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

2 months

1
0
0 0

Trusted Firmware-A LTS v2.10.27 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.27 is now available. This release contains the following patches: fb0ca7ca1 build(npm): adhere to Husky deprecation notice [1] 17a8aec49 fix(cpus): workaround for Cortex-A76AE erratum 1931427 [2] fc5e6eeee fix(cpus): workaround for Cortex-A76AE erratum 1931435 [3] 918cb2542 fix(cpus): workaround for Cortex-A76AE erratum 1969401 [4] 6f78d7d29 fix(cpus): workaround for Cortex-A76AE erratum 2371140 [5] d5424f6d8 fix(build): set ERRATA_SPECULATIVE_AT after platform.mk [6] 659e46683 fix(cpus): workaround for Cortex-A65 erratum 1179935 [7] 909b29568 fix(cpus): workaround for Cortex-A65 erratum 1227419 [8] 42777038e fix(cpus): workaround for Cortex-A65 erratum 1541130 [9] 948f017ea fix(cpus): workaround for Cortex-A725 erratum 2874943 [10] 5ff59225e fix(cpus): workaround for Cortex-A725 erratum 2936490 [11] d2ab008e2 fix(cpus): workaround for Cortex-A725 erratum 3711914 [12] d0d0d0285 fix(cpus): workaround for Cortex-A725 erratum 3456106 [13] [1] https://review.trustedfirmware.org/q/I763a462b2a0da7852696f874df970810a2b01… [2] https://review.trustedfirmware.org/q/I31566838f894372e5627abda8b0bea1505f11… [3] https://review.trustedfirmware.org/q/I1baba8752f5f2e2ab5c873030e1f00cbb8cf1… [4] https://review.trustedfirmware.org/q/I893452450d430833e6c5a8e33a1e37b708218… [5] https://review.trustedfirmware.org/q/Id65846bebde1a0911ba11956202d0d255d3c8… [6] https://review.trustedfirmware.org/q/I221dab39c417531c5a148886d3e29709ba8b5… [7] https://review.trustedfirmware.org/q/Ie59a4897f849269a590d8fa2d25cceab5f2cb… [8] https://review.trustedfirmware.org/q/I42371e7d53fce3a7e085bf0b348f080fa323f… [9] https://review.trustedfirmware.org/q/I72498f60f8449193ed4b5b2a9e7a08530e786… [10] https://review.trustedfirmware.org/q/I686bbde8756d52afee92097ec05b97138b550… [11] https://review.trustedfirmware.org/q/I9833f8831ba3735a94763791a65be11b95c00… [12] https://review.trustedfirmware.org/q/If3b9d3a0f495b3a172d3e6e5ca7afa8c30aeb… [13] https://review.trustedfirmware.org/q/I10d1e8cb4da19ba4101a5617245ff75866707… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.27/change-log.html Thanks, TF-A LTS team

2 months

1
0
0 0

Email to TF-A

by Prasanth Nair

Email to TF-A

2 months

1
0
0 0

Trusted Firmware-A LTS v2.8.41 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.41 is now available. This release contains the following patches: 0a85ca29f fix(security): add clrbhb support [1] 7c5bca9b9 fix(cpus): workaround for Cortex-A715 erratum 2409570 [2] 931417cff fix(cpus): workaround for Cortex-A715 erratum 2376701 [3] 368077598 fix(cpus): workaround for Cortex-A715 erratum 3711916 [4] 930fcc0b6 fix(cpus): workaround for Cortex-A76AE erratum 1931427 [5] 34f2ec4d0 fix(cpus): workaround for Cortex-A76AE erratum 1931435 [6] 9ad229ec8 fix(cpus): workaround for Cortex-A76AE erratum 1969401 [7] dccafbf14 fix(cpus): workaround for Cortex-A76AE erratum 2371140 [8] 24191cda2 fix(cpus): workaround for Cortex-A65 erratum 1179935 [9] ec702b29f fix(cpus): workaround for Cortex-A65 erratum 1227419 [10] 1cf89d221 fix(cpus): workaround for Cortex-A65 erratum 1541130 [11] a5b818591 docs(security): add CVE-2024-5660 and CVE-2024-7881 reference links [12] 800a3bda8 fix(security): update Cortex-X4 fix version for CVE-2024-7881 [13] e3eed549b fix(security): update Neoverse-V3/V3AE fix version for CVE-2024-7881 [14] e56910a48 fix(security): update Cortex-X3 fix version for CVE-2024-7881 [15] 76e43568c fix(security): update Neoverse-V2 fix version for CVE-2024-7881 [16] 8776324c8 docs(security): update CVE-2024-7881 affected CPU revisions [17] 990086206 fix(cpus): register ARCH_WORKAROUND_3 for Neoverse V2 [18] ba8c49193 fix(cpus): workaround for Cortex-A710 erratum 3324338 [19] b4cdfa94d fix(cpus): workaround for Cortex-X2 erratum 3324338 [20] d3169c509 fix(cpus): workaround for Cortex-A715 erratum 3456084 [21] bddc18aea fix(cpus): workaround for Cortex-A720 erratum 3456091 [22] [1] https://review.trustedfirmware.org/q/Ie6e56e96378503456a1617d5e5d51bc64c2e0… [2] https://review.trustedfirmware.org/q/Id9429831525b842779d7b7e60f103c93be4ac… [3] https://review.trustedfirmware.org/q/Idcd2a07d269d55534dc5faa59c454d37426f2… [4] https://review.trustedfirmware.org/q/Iad149a2c02a804b3f4f0f2f5b89e866675cb4… [5] https://review.trustedfirmware.org/q/I31566838f894372e5627abda8b0bea1505f11… [6] https://review.trustedfirmware.org/q/I1baba8752f5f2e2ab5c873030e1f00cbb8cf1… [7] https://review.trustedfirmware.org/q/I893452450d430833e6c5a8e33a1e37b708218… [8] https://review.trustedfirmware.org/q/Id65846bebde1a0911ba11956202d0d255d3c8… [9] https://review.trustedfirmware.org/q/Ie59a4897f849269a590d8fa2d25cceab5f2cb… [10] https://review.trustedfirmware.org/q/I42371e7d53fce3a7e085bf0b348f080fa323f… [11] https://review.trustedfirmware.org/q/I72498f60f8449193ed4b5b2a9e7a08530e786… [12] https://review.trustedfirmware.org/q/Ia3c003d5c359f101f230fbd54845f61117456… [13] https://review.trustedfirmware.org/q/Iae84f26fdce96a61fdc942b7595ccf8b9c778… [14] https://review.trustedfirmware.org/q/If3e2989a4b5a5c68dc12e23978b226c73f21b… [15] https://review.trustedfirmware.org/q/Ia1ff75602a0dfa758a223549d92ea87543fa4… [16] https://review.trustedfirmware.org/q/I1ae196fa8ce4579524faba4916f631e7c4db3… [17] https://review.trustedfirmware.org/q/Iad109561a144169fd3805c179a4f8e3bfdd59… [18] https://review.trustedfirmware.org/q/I8c08c26e0b7c268772d75d36d759564a7d67c… [19] https://review.trustedfirmware.org/q/I9325f3715f4fa17bfb7ded9d5c69c59645f65… [20] https://review.trustedfirmware.org/q/Ibbe55a55bd6cf5e159dab92a78ecb55c5a4d7… [21] https://review.trustedfirmware.org/q/Ie3f2b46051539cdebc151c46f80045a7156e0… [22] https://review.trustedfirmware.org/q/Ia22a0d6bb98d1a0edb11d2469beab22c7f7ab… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.41/change-log.html Thanks, TF-A LTS team

2 months

1
0
0 0

ZynqMP regression with NUMA_AWARE_PER_CPU changes with ENABLED_LTO : Linux runtime hang due to EL3 re-entry

by Kummari, Prasad

[AMD Official Use Only - AMD Internal Distribution Only] Hello Maintainers, We are observing a reproducible runtime regression on the ZynqMP (Cortex-A53) platform after enabling LTO (ENABLED_LTO=1) and merging the changes from the topic NUMA_AWARE_PER_CPU into our integration branch (https://github.com/ARM-software/arm-trusted-firmware/commit/7303319b3823e9e…). Summary of the issue 1. Baseline behavior * Platform: ZynqMP (Cortex-A53) * Configuration: ENABLED_LTO=1 * Without NUMA_AWARE_PER_CPU: Linux boots and runs stably * After merging NUMA_AWARE_PER_CPU, Linux boots but hangs during runtime * During the hang, CPUs are observed to unexpectedly re-enter EL3 * Re-entry into EL3 should not occur during normal Linux runtime execution and strongly suggests corruption or mismanagement of PSCI and/or per-CPU state(arm-trusted-firmware/lib/per_cpu/aarch64/per_cpu_asm.S at master * ARM-software/arm-trusted-firmware<https://github.com/ARM-software/arm-trusted-firmware/blob/master/lib/per_cp…>) * Reverting the NUMA_AWARE_PER_CPU changes restores stable Linux execution * The issue is reproducible only when NUMA_AWARE_PER_CPU is present * This clearly identifies NUMA_AWARE_PER_CPU as the regression source 2. Suspect with LTO * With NUMA_AWARE_PER_CPU enabled, LTO breaks the per-CPU base calculation * BL31 contains hand-written assembly that relies on linker-script symbols (e.g., per-CPU section boundaries) * Under LTO, symbol placement and retention are no longer guaranteed in the same way, leading to incorrect per-CPU base computation * This results in corrupted per-CPU data and subsequent erroneous PSCI suspend behavior (EL3 re-entry) 3. CPU idle dependency * The following kernel configuration options are enabled: * CONFIG_CPU_IDLE=y * CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y * CONFIG_CPU_IDLE_GOV_MENU=y * CONFIG_DT_IDLE_STATES=y * This further suggests the issue is triggered during CPU idle / suspend-resume paths, where correct per-CPU state handling is critical Based on the above: * This is specific to NUMA_AWARE_PER_CPU combined with LTO * The failure mode points to per-CPU base calculation and PSCI state corruption * Reverting NUMA_AWARE_PER_CPU fully restores stability on ZynqMP We wanted to report this issue upstream and seek guidance on: * Whether NUMA_AWARE_PER_CPU is expected to be LTO-safe on platforms relying on linker-defined per-CPU sections * Or if additional constraints / fixes are required for platforms like ZynqMP We are happy to provide further logs, configuration details, or help to fixes. Regards, Prasad Kummari

2 months

2
7
0 0

Canceled event with note: TF-A Tech Forum @ Thu Jan 8, 2026 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Cancelling as no topic this week." TF-A Tech Forum Thursday Jan 8, 2026 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

2 months

1
0
0 0

Invitation: TF-A Tech Forum Jan 22nd 10.00am -Part II Scaling Hafnium... @ Thu Jan 22, 2026 11am - 12pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

TF-A Tech Forum Jan 22nd 10.00am -Part II Scaling Hafnium for advanced mobile OS architectures Thursday Jan 22, 2026 ⋅ 11am – 12pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Hi, As follow up to the last session on Nov 13th 2025 [1], a new TF-A Tech Forum session with the topic'Scaling Hafnium for advanced mobile OS architectures' will be held on Jan 22nd 2026 10.00am. Regards,Olivier. [1] https://www.trustedfirmware.org/meetings/tf-a-technical-forum/ Scaling Hafnium for advanced mobile OS architectures - Presented by Jack Suann PDF Presentation Video Recording (Access Password: *PIs1^BD) Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumJoin Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org View all guest info https://calendar.google.com/calendar/event?action=VIEW&eid=NmFoYTlsdXBjYjZj… Reply for tf-a(a)lists.trustedfirmware.org and view more details https://calendar.google.com/calendar/event?action=VIEW&eid=NmFoYTlsdXBjYjZj… Your attendance is optional. ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

2 months

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 501137: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /common/runtime_svc.c: 261 in handler_sync_exception() _____________________________________________________________________________________________ *** CID 501137: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /common/runtime_svc.c: 261 in handler_sync_exception() 255 /* advance the PC to continue after the instruction */ 256 write_ctx_reg(state, CTX_ELR_EL3, read_ctx_reg(state, CTX_ELR_EL3) + 4); 257 } /* otherwise return to the trapping instruction (repeating it) */ 258 return; 259 /* If FFH Support then try to handle lower EL EA exceptions. */ 260 } else if ((exc_class == EC_IABORT_LOWER_EL || exc_class == EC_DABORT_LOWER_EL) >>> CID 501137: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "state->ctx_regs[0U /* 0U >> 3U */] | (8UL /* 1UL << 3 */)" is always 1/true regardless of the values of its operand. This occurs as the logical second operand of "&&". 261 && (read_ctx_reg(state, CTX_SCR_EL3) | SCR_EA_BIT)) { 262 #if FFH_SUPPORT 263 /* 264 * Check for Uncontainable error type. If so, route to the 265 * platform fatal error handler rather than the generic EA one. 266 */ ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

2 months, 1 week

1
0
0 0

Re: Questions about Chain-of-Trust and RSE Connectivity

by Olivier Deprez

+ TF-A list ________________________________ From: Olivier Deprez Sent: 05 January 2026 15:11 To: Taehoon Kim <gth1919(a)adtek.co.kr> Cc: Raef Coles <Raef.Coles(a)arm.com>; Jackson Cooper-Driver <Jackson.Cooper-Driver(a)arm.com>; Nishant Sharma <Nishant.Sharma(a)arm.com>; Rohit Mathew <Rohit.Mathew(a)arm.com>; Manish Pandey2 <Manish.Pandey2(a)arm.com>; Manish Badarkhe <Manish.Badarkhe(a)arm.com> Subject: Questions about Chain-of-Trust and RSE Connectivity Hi Taehoon Kim, We seem to experience an issue with the mailing list where messages are not properly dispatched. I reproduced your initial email sent Dec 18th 2025 below and Cced relevant folks just in case. Regards, Olivier. ____________________________________________________________ Hello, I'm firmware developer for RD-V3-R1 chipset. I have developed our firmware based on Neoverse Reference Platform RD-INFRA-2025.07.03, but I have also kept an eye on the code to ensure we remain in step with the latest release. While inquiring on the TF-M forum to update the TF-M code, I also developed a query regarding the TF-A section. Re: Several Questions related to RSE Provisioning - TF-M - lists.trustedfirmware.org<https://lists.trustedfirmware.org/archives/list/tf-m@lists.trustedfirmware.…> This link includes that RSE API codes are removed in the SotA TF-A codes. I check this in the TF-A commit. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/46314 I was already aware that this API was not used outside of test code. However, I would like to know the reason why that code was removed, beyond the simple fact that it was not being used. Is it possible that Chain-of-Trust is established in whole firmware stack from RSE ROM to AP BL33 bootloader, without RSE assist? If possible, what does TF-A rely upon as the basis for trust in establishing the Root of Trust? Our team believed that CoT was established on the premise of the RSE API, and was therefore designing to ensure the trustworthiness of the entire firmware using that code. However, we recognise that to use the latest version of the code, we must abandon that belief and design in a different manner. Before the new version of RD-INFRA is released, we intend to resolve this internally as a team. Should you feel the scope of the question extends beyond what is typically addressed in the forum, please do not hesitate to let us know. Thank you for reading this mail. Best Regard, Taehoon Kim

2 months, 1 week

3
2
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 2 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 500810: Incorrect expression (SIZEOF_MISMATCH) /contrib/libeventlog/src/event_log.c: 394 in event_log_write_specid_event() _____________________________________________________________________________________________ *** CID 500810: Incorrect expression (SIZEOF_MISMATCH) /contrib/libeventlog/src/event_log.c: 394 in event_log_write_specid_event() 388 } 389 390 /* TCG_EfiSpecIdEvent.VendorInfo */ 391 if (vendor_info_size > 0) { 392 vendor_info_ptr = 393 (tcg_vendor_info_t >>> CID 500810: Incorrect expression (SIZEOF_MISMATCH) >>> Adding "4UL /* sizeof (id_event_algorithm_size_t) */ * algo_count" to pointer "spec_id_ptr->digest_size" of type "id_event_algorithm_size_t *" is suspicious because adding an integral value to this pointer automatically scales that value by the size, 4 bytes, of the pointed-to type, "id_event_algorithm_size_t". Most likely, the multiplication by "sizeof (id_event_algorithm_size_t)" in this expression is extraneous and should be eliminated. 394 *)(spec_id_ptr->digest_size + 395 sizeof(id_event_algorithm_size_t) * 396 algo_count); 397 398 vendor_info_ptr->vendor_info_size = vendor_info_size; 399 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

2 months, 3 weeks

1
0
0 0

Questions about Chain-of-Trust and RSE Connectivity

by 김태훈

Hello, I'm firmware developer for RD-V3-R1 chipset. I have developed our firmware based on Neoverse Reference Platform RD-INFRA-2025.07.03, but I have also kept an eye on the code to ensure we remain in step with the latest release.  While inquiring on the TF-M forum to update the TF-M code, I also developed a query regarding the TF-A section. Re: Several Questions related to RSE Provisioning - TF-M - lists.trustedfirmware.org This link includes that RSE API codes are removed in the SotA TF-A codes. I check this in the TF-A commit. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/46314 I was already aware that this API was not used outside of test code. However, I would like to know the reason why that code was removed, beyond the simple fact that it was not being used. Is it possible that Chain-of-Trust is established in whole firmware stack from RSE ROM to AP BL33 bootloader, without RSE assist? If possible, what does TF-A rely upon as the basis for trust in establishing the Root of Trust?  Our team believed that CoT was established on the premise of the RSE API, and was therefore designing to ensure the trustworthiness of the entire firmware using that code. However, we recognise that to use the latest version of the code, we must abandon that belief and design in a different manner. Before the new version of RD-INFRA is released, we intend to resolve this internally as a team. Should you feel the scope of the question extends beyond what is typically addressed in the forum, please do not hesitate to let us know. Thank you for reading this mail. Best Regard, Taehoon Kim

2 months, 4 weeks

1
0
0 0

Hafnium v2.14 LTS Major Release Announcement

by Madhukar Pappireddy

3 months

1
0
0 0

[RFE] lib/el3_runtime: set NS bit if secure el2 is not implemented

by Pawandeep Oza (QUIC)

Please have a look at following patch, where on our platform we try to maintain single image of TFA (for custom CPU and Cortex A55) Cortex A55 does not have Secure EL2 implemented, while on the other hand our custom CPU has secure EL2 (and we run Hafnium there) On Cortex A55 ARM AEM model: write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); the context was set before as u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; and setting ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT causes crash since secure EL2 is not implemented. resulting into following patch which resolves the issue. seeking feedback/discussion if I can post it to upstream TFA, let me know if I am missing something here. lib/el3_runtime: set NS bit if secure el2 is not implemented before setting icc_sre_el2 set NS bit for non-secure context so that the ICC_SRE_DIB_BIT and ICC_SRE_DFB_BIT are preserved Signed-off-by: Oza Pawandeep <quic_poza(a)quicinc.com> diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index e31255868..5100f2f00 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1411,7 +1411,18 @@ static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t securit u_register_t scr_el3 = read_scr_el3(); #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 - write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); + if (is_feat_sel2_supported()) { + write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); + } else { + write_scr_el3(scr_el3 | SCR_NS_BIT); + isb(); + + write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); + + write_scr_el3(scr_el3); + isb(); + } + #else write_scr_el3(scr_el3 | SCR_NS_BIT); isb(); Regards, Oza.

3 months

5
5
0 0

Trusted Firmware-A v2.14 LTS Major Release Announcement

by Bipin Ravi

Hello, This is to announce the fourth TF-A LTS branch "lts-v2.14". As per the process, this LTS branch is based on the 2nd mainline TF-A release of the year, v2.14.0. Following are the lts-v2.14 branches for the TF-A related repos. 1. trusted-firmware-a : https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a.git… 2. tf-a-tests: https://git.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests.git/+/refs/… 3. tf-a-ci-scripts: https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-ci-scripts/+/refs/h… 4. tf-a-job-configs: https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-job-configs/+/refs/… Change Log: Since the lts-v2.14 branch is based on the TF-A release v2.14.0 without any additional patches, there is no separate changelog for this first release. Thanks, TF-A LTS team

3 months

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu Dec 25, 2025 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "No TF-A Tech forum on Dec 25th." TF-A Tech Forum Thursday Dec 25, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

3 months

1
0
0 0

First Hafnium LTS release

by Madhukar Pappireddy

Hi, We will be making the first Hafnium LTS branch release based of the recent v2.14.0 tag. We would encourage anyone interested in Hafnium LTS support or maintenance to subscribe themselves to this mailing list: https://lists.trustedfirmware.org/mailman3/lists/hafnium-lts.lists.trustedf… <https://lists.trustedfirmware.org/mailman3/lists/hafnium-lts.lists.trustedf…> We also recommend to join the hafnium-lts channel in trustedfirmware discord server for real time updates and getting involved with the LTS maintenance. Thanks, Madhukar

3 months

1
0
0 0

TF-A Tech Forum Dec 11th 4.00pm (UK) - TF-RMM Live Firmware Activation (design update)

by Olivier Deprez

Hi, On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will present a design update on TF-RMM Live Firmware Activation: This presentation describes the revised TF-RMM Low-VA MMU and global-runtime-data design required to support Live Firmware Activation (LFA). Compared to the earlier approach (outlined in the TFA Tech Forum session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings and per-platform handcrafted Low-VA contexts, the new design is driven by several changes in RMM specification: RMM must now support runtime mapping/unmapping of PAs for RMM objects like struct granule , reuse those dynamic mappings across LFA transitions. These PAs can come either from NS world at runtime or EL3 reservation from RMM carveout. In order to migrate Stage 1 dynamic mappings across LFA instances, RMM needs to reduce dependence on platform-specific MMU setup, and provide a structured framework for allocating, versioning and migrating global runtime data. The Stage 1 Low-VA is therefore split into static and dynamic regions managed by the common xlat layer. The detailed design is captured in the TF-RMM wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial design presented in the TFA Tech Forum session on 12-Jun-2025 [1] : [1] Previous LFA discussion: https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations [2] https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act… Regards, Olivier. TF-A Tech Forum Thursday Dec 11, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com jagdish.gediya(a)linaro.org

3 months

1
0
0 0

TF-A Tech Forum Dec 11th 4.00pm (UK) - TF-RMM Live Firmware Activation (design update)

by Olivier Deprez

Hi, On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will present a design update on TF-RMM Live Firmware Activation: This presentation describes the revised TF-RMM Low-VA MMU and global-runtime-data design required to support Live Firmware Activation (LFA). Compared to the earlier approach (outlined in the TFA Tech Forum session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings and per-platform handcrafted Low-VA contexts, the new design is driven by several changes in RMM specification: RMM must now support runtime mapping/unmapping of PAs for RMM objects like struct granule , reuse those dynamic mappings across LFA transitions. These PAs can come either from NS world at runtime or EL3 reservation from RMM carveout. In order to migrate Stage 1 dynamic mappings across LFA instances, RMM needs to reduce dependence on platform-specific MMU setup, and provide a structured framework for allocating, versioning and migrating global runtime data. The Stage 1 Low-VA is therefore split into static and dynamic regions managed by the common xlat layer. The detailed design is captured in the TF-RMM wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial design presented in the TFA Tech Forum session on 12-Jun-2025 [1] : [1] Previous LFA discussion: https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations [2] https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act… Regards, Olivier.

3 months

1
0
0 0

Synced invitation: TF-A Tech Forum @ Thu 2025-11-13 4pm - 5pm (GMT) (tf-a@lists.trustedfirmware.org)

by qwandor＠google.com

This email keeps the event up to date in your calendar. TF-A Tech Forum Thursday 2025-11-13 ⋅ 4pm – 5pm United Kingdom Time Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

3 months, 2 weeks

1
0
0 0

Synced invitation: TF-A Tech Forum @ Every 2 weeks from 4pm to 5pm on Thursday (BST) (tf-a@lists.trustedfirmware.org)

by Andrew Walbran

This email keeps the event up to date in your calendar. TF-A Tech Forum Every 2 weeks from 4pm to 5pm on Thursday United Kingdom Time Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org Andrew Walbran Pranjal Shrivastava Jeremi Miller ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

3 months, 2 weeks

1
0
0 0

Synced invitation: TF-A Tech Forum @ Every 2 weeks from 4pm to 5pm on Thursday (GMT) (tf-a@lists.trustedfirmware.org)

by Andrew Walbran

This email keeps the event up to date in your calendar. TF-A Tech Forum Every 2 weeks from 4pm to 5pm on Thursday United Kingdom Time Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org Andrew Walbran Pranjal Shrivastava Jeremi Miller ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

3 months, 2 weeks

1
0
0 0

TF-A Tech Forum - Nov 27th - Overview of measured boot driver libraries

by Olivier Deprez

Hi, In the TF-A Tech forum on Thursday Nov 27th 4.00pm UK, Harrison Mutai<mailto:Harrison.Mutai@arm.com> and Matthew Ellis<mailto:Matthew.Ellis@arm.com> will provide an overview of the shared measured boot driver libraries, namely: LibTPM and LibEventLog, and align on design, integration, and contribution workflows: - Motivation for introducing shared measured boot driver libraries - Overview of current architecture and key components - Integration into platform builds and deployment examples (FVP and RPi) - Testing and CI workflows for validation and patch contributions - Access, contribution process, and future development plan Regards, Olivier. ________________________________ From: Trusted Firmware Public Meetings Sent: 02 May 2025 12:00 To: Trusted Firmware Public Meetings <linaro.org_havjv2figrh5egaiurb229pd8c(a)group.calendar.google.com>; tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org> Subject: TF-A Tech Forum When: 27 November 2025 17:00-18:00. Where: https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… TF-A Tech Forum Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the follow Trusted Firmware is inviting you to a scheduled Zoom meeting. Topic: TF-A Tech Forum Time: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s) Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics…<https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fmeeting%2Ft…> Join Zoom Meeting https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…<https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…> Meeting ID: 935 5786 3987 Passcode: 939141 --- One tap mobile +12532158782,,93557863987# US (Tacoma) +13017158592,,93557863987# US (Washington DC) --- Dial by your location • +1 253 215 8782 US (Tacoma) • +1 301 715 8592 US (Washington DC) • +1 305 224 1968 US • +1 309 205 3325 US • +1 312 626 6799 US (Chicago) • +1 346 248 7799 US (Houston) • +1 360 209 5623 US • +1 386 347 5053 US • +1 507 473 4847 US • +1 564 217 2000 US • +1 646 558 8656 US (New York) • +1 646 931 3860 US • +1 669 444 9171 US • +1 669 900 9128 US (San Jose) • +1 689 278 1000 US • +1 719 359 4580 US • +1 253 205 0468 US • 833 548 0276 US Toll-free • 833 548 0282 US Toll-free • 833 928 4608 US Toll-free • 833 928 4609 US Toll-free • 833 928 4610 US Toll-free • 877 853 5247 US Toll-free • 888 788 0099 US Toll-free Meeting ID: 935 5786 3987 Find your local number: https://linaro-org.zoom.us/u/adoz9mILli<https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fu%2Fadoz9mI…> When Every 2 weeks from 4pm to 5pm on Thursday (United Kingdom Time) Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… View map<https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…> Guests tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> View all guest info<https://calendar.google.com/calendar/event?action=VIEW&eid=NnR0NGMyZWJkdnBn…> RSVP for tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> for all events in this series Yes<https://calendar.google.com/calendar/event?action=RESPOND&eid=NnR0NGMyZWJkd…> No<https://calendar.google.com/calendar/event?action=RESPOND&eid=NnR0NGMyZWJkd…> Maybe<https://calendar.google.com/calendar/event?action=RESPOND&eid=NnR0NGMyZWJkd…> More options<https://calendar.google.com/calendar/event?action=VIEW&eid=NnR0NGMyZWJkdnBn…> Invitation from Google Calendar<https://calendar.google.com/calendar/> You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more<https://support.google.com/calendar/answer/37135#forwarding>

3 months, 2 weeks

1
0
0 0

Non volatile boot index for the purpose of firmware update

by Patryk

Hi I'm looking for a suggestion for a reliable place to store a small boot index for PSA Firmware Update. SNVS LPGPRs looked promising, but NXP’s guidance is thin and we don’t keep the battery-backed LP domain alive, so those values won’t survive many power cycles. Are there better options on LS1028A? Would using the user RAM byte in our external I2C RTC make sense? Or perhaps should I store it on eMMC? (we don't use raw NOR/NAND flash). That RTC I mentioned is already accessed in both U-Boot and Linux, so I’m wary of conflicts but can try it if you think it’s viable. Any suggestions would be much appreciated. Best regards Patryk

3 months, 2 weeks

1
0
0 0

Question about SError exception routing

by Julius Werner

Hi, I have a sort of generic Arm architecture question that's not directly related to TF-A (other than that TF-A controls some of the registers involved in this decision), but I'm hoping that one of the experts here can still help me out or at least refer me to someone who can. I'm trying to figure out how exception routing for SError aborts works in EL2. Specifically, I have a bootloader (BL33) running in NS-EL2 and I want the "simple" setup that it manages all its own exceptions, the same way that an OS kernel normally manages all exceptions at EL1. I assumed that I could achieve that simply by installing exception handlers, unmasking all exceptions in PSTATE, and leaving all the special trap feature bits in the MSRs at 0 (disabled). This seems to work for synchronous exceptions and external aborts, but not for SErrors. Looking at the architecture reference manual (revision L.b), table D1-14 in section D1.3.6.3 (page D1-6114), I can see that my case is represented by the first line (all special trap bits 0), which shows that SErrors caused by EL0 and EL1 would be routed to EL1 as expected (though even when PSTATE.A is 1 which seems odd?), but SErrors caused by EL2 will get ignored and remain pending (with no regard to PSTATE.A). Instead, the "default" behavior I expect (aborts get routed to the EL that caused them if PSTATE.A is 0) seems to require me to enable SCTLR_EL2.NMEA. But if you're looking at the description of SCTLR_EL2.NMEA, it says that it controls whether PSTATE.A masks SError exceptions at EL2 (and that if it is 0, SError exceptions are not taken at EL2 if PSTATE.A == 1). Doesn't that imply that SError exceptions *are* taken at EL2 if PSTATE.A == 0? What does a control that seems to be about trapping masked aborts from a lower EL have to do with unmasked aborts from my current EL? Basically, I think what I'm asking is: is that table really correct as printed (some behavior we've observed seems to indicate it is), and if so, why? Why do SError exceptions seem to behave differently by default in EL1 and EL2 (in regards to unmasked exceptions taken from the same exception level)? Why does the PSTATE.A bit only seem to apply to EL0 and EL1, not EL2 and EL3, even for exceptions taken from the same level, when this peculiarity seems to not be mentioned anywhere else in the manual? Why do SError exceptions get treated so differently from external aborts in EL2/EL3, when in EL1 they seem to mostly count as the same? Is the current description of the NMEA bit in the SCTLR_EL2 register documentation really accurate, if it also seems to make fundamental changes to cases not really mentioned in that description? Is there any way for EL2 to only handle its own SError exceptions without interfering with EL1's exception handling when FEAT_DoubleFault2 is not implemented (other than flipping HCR_EL2.AMO on every EL2 entry/exit)? And am I the only one who finds this all incredibly inconsistent and confusing? I feel like I'm missing some critical insight in how you were meant to think about this to make it make sense, would appreciate any help in that regard! Thanks, Julius

3 months, 2 weeks

2
5
0 0

Trusted Firmware v2.14 release announcement

by Olivier Deprez

Hi, We are pleased to announce the formal release of Trusted Firmware-A version 2.14 bundle of project deliverables. This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium, TF-RMM, Trusted Services, and TF-A OpenCI scripts/jobs components. These went live on Nov, 24th 2025. Please find tag references and change logs at the end of this email. Many thanks to the trustedfirmware.org community for the active engagement in delivering this release! Notable features of the release version 2.14 are as follows: TF-A/EL3 * New architectural features support: FEAT_FGWTE3, FEAT_IDTE3, FEAT_RME_GPC2, FEAT_AIE, FEAT_CPA2, FEAT_MPAM_PE_BW_CTRL, FEAT_PFAR, FEAT_RME_GDI. * Live Firmware Activation: base support enabling TF-RMM LFA, added RMM MEM RESERVE ABI. * Armv9 CPU power down abandon support * GICv5 driver permitting normal world kernel boot * GIC720-AE support added * Per-cpu framework supporting NUMA platforms * SMCCC SoC name support (SMCCC v1.6 SMCCC_ARCH_SOC_ID) * SPMD: added FF-A v1.3 FFA_NS_RES_INFO_GET, FFA_ABORT interfaces * EL3 SPMC: add multiple UUIDs support, TPM event log delivered by HOB list, FFA_MEM_RETRIEVE_REQ from hypervisor * RME: FEAT_D128 for realm world, SMCCC_ARCH_FEATURE_AVAILABILITY * Platforms: RD-Aspen added, updates to Arm FVP/Juno, AMD Versal Gen2, Intel, MT8189, MT8196, i.MX94, i.MX95, S32G274A, QTI Kodiak, Renesas R-Car, STM32MP1, STM32MP2, STM32MP21, STM32MP25, Xilinx Versal, ZynqMP Boot flow * Transfer list and event log libraries now offered as shared libraries consumed as submodules by TF-A. * Update to mbedTLS 3.6.5 * Various PSA FWU improvements, namely BL2 in a dedicated FIP, GPT-corruption notifications to BL32, and expanded FWU tests. Errata/Security mitigations (CPU/GIC) * New CPU support: Arm Lumex C1, Dionysus, Caddo/Veymont, Venom. * Added close to 30 new CPU errata across multiple processor families, based on the latest SDEN updates. Hafnium/SPM (S-EL2) * FF-A v1.3 early adoption * FFA_NS_RES_INFO_GET ABI added * Partition lifecycle support: new states, abort handling. Pre-requisite to secure partitions live firmware activation. * Notifications support refactored with per-vCPU notifications removed. * Multi-GIC configuration supporting complex topologies. * Shrinkwrap used at core of Hafnium testing infrastructure. TF-RMM (R-EL2) * RMM v1.1 Planes support * PMU, timer, GIC ownership transfer. * Support for FEAT_S1POE/S1PIE, FEAT_S2POE/S2PIE * RMM v1.1 Memory Encryption Contexts (MEC) support * Realm Device Assignment * RMM v1.1. ALP12 base Device Assignment support * RMI VDEV ABIs, PDEV life cycle, root port IDE key programming, SPDM client as EL0 app. * Improved ID registers trapping leveraging SMCCC ARCH_FEATURE_AVAILABILITY, in light of future FEAT_IDTE3 support. * Additional architectural support: FEAT_TCR2, FEAT_D128, single-copy atomics, TF-A Tests * RME: DA and PCIe, Planes, MEC * SPM/FF-A * Bumped support o FF-A v1.3 * FFA_ABORT ABI * Deprecated per-vCPU notifications. * FWU: added negative testing (invalid image size, corrupted ROTPK) * GICv5 support added * Arm architecture tests * FEAT_TCR2 (for RME) , FEAT_IDTE3, FEAT_MPAM_PE_BW_CTRL, FEAT_EBEP, FEAT_AIE, FEAT_PFAR * SMCCC_ARCH_SOC_ID * SMCCC_ARCH_FEATURE_AVAILABILITY * Fuzzing: added SMC fuzzer documentation * Basic LFA framework tests * Platforms updates: AMD/Xilinx, Arm FVP, Corstone-1000 Trusted Services * RD-Aspen platform support added. * EFI ESRT handling in FWU Proxy (supporting Corstone1000 platform). * Block Storage service threat modelling. Release tags across repositories: https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r… https://git.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags… https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-ci-scripts/+/refs/t… https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-job-configs/+/refs/… https://git.trustedfirmware.org/plugins/gitiles/hafnium/hafnium/+/refs/tags… https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-ci-scripts/+/ref… https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-job-configs/+/re… https://git.trustedfirmware.org/plugins/gitiles/TF-RMM/tf-rmm/+/refs/tags/t… https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/… Change logs: https://trustedfirmware-a.readthedocs.io/en/v2.14.0/change-log.html#id1 https://trustedfirmware-a-tests.readthedocs.io/en/v2.14.0/change-log.html#v… https://hafnium.readthedocs.io/en/v2.14.0/change-log.html#id1 https://tf-rmm.readthedocs.io/en/tf-rmm-v0.8.0/about/change-log.html#v0-8-0 https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/… Regards, Olivier.

3 months, 2 weeks

1
0
0 0

TF-A Tech Forum - Hafnium future looking improvements @ Thu Nov 13, 2025 11am - 12pm (UK)

by Olivier Deprez

Hi, This is a one off session for a partner to present coming improvements related to Hafnium project. Apologies for the meeting time not accommodating people in US timezones. We'll record the session and publish in the TF-A tech forum page as usual. Regards, Olivier. ________________________________ From: Google Calendar <calendar-notification(a)google.com> on behalf of Olivier Deprez via Hafnium <hafnium(a)lists.trustedfirmware.org> Sent: 07 November 2025 09:13 To: hafnium(a)lists.trustedfirmware.org <hafnium(a)lists.trustedfirmware.org> Subject: [Hafnium] Invitation: TF-A Tech Forum - Hafnium future looking improvements @ Thu Nov 13, 2025 12pm - 1pm (GMT+1) (hafnium(a)lists.trustedfirmware.org) TF-A Tech Forum - Hafnium future looking improvements Thursday Nov 13, 2025 ⋅ 12pm – 1pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Hi, This is a one off session for a partner to present coming improvements related to Hafnium project. Apologies for the meeting time not accommodating people in US timezones. We'll record the session and publish in the TF-A tech forum page as usual. Regards,Olivier.Trusted Firmware is inviting you to a scheduled Zoom meeting.Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Reply for hafnium(a)lists.trustedfirmware.org and view more details https://calendar.google.com/calendar/event?action=VIEW&eid=MDdmMGs0NjBkcW5q… Your attendance is optional. ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding -- Hafnium mailing list -- hafnium(a)lists.trustedfirmware.org To unsubscribe send an email to hafnium-leave(a)lists.trustedfirmware.org

3 months, 4 weeks

1
1
0 0

Trusted Firmware-A LTS v2.8.40 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.40 is now available. This release contains the following patches: af828443d fix(spm-mm): prevent excessive racing [1] c1c4d7d5d fix(security): remove CVE_2022_23960 Cortex-A720 [2] 7d6831115 fix(security): remove CVE_2022_23960 Neoverse V3 [3] 373b22562 fix(security): remove CVE_2022_23960 Cortex-X4 [4] [1] https://review.trustedfirmware.org/q/I0861d04ed95437e4ca9f203d9e79a6296b1ea… [2] https://review.trustedfirmware.org/q/I3c68b5f5d85ede37a6a039369de8ed2aa9205… [3] https://review.trustedfirmware.org/q/I13b27c04c3da5ec80fa79422b4ef4fee64738… [4] https://review.trustedfirmware.org/q/I23f5fa748377a920340b3c5a6584ccfadeea9… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.40/change-log.html Thanks, TF-A LTS team

4 months

1
0
0 0

Trusted Firmware-A LTS v2.10.26 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.26 is now available. This release contains the following patches: abea08e8c fix(spm-mm): prevent excessive racing [1] 91edc92e9 fix(security): fix spectre bhb loop count for Cortex-A720 [2] d12e9ecf2 fix(security): fix Cortex-A715 CVE-2022-23960 [3] f360aa51d fix(security): fix Cortex-X3 CVE-2022-23960 [4] 8ee12c187 fix(security): fix Neoverse V2 CVE-2022-23960 [5] d30e468b3 fix(security): remove CVE_2022_23960 Cortex-X4 [6] 96e666d6b fix(security): remove CVE_2022_23960 Neoverse V3 [7] a483d67c7 fix(security): remove CVE_2022_23960 Cortex-A720 [8] 07a6a7a9c refactor(cpufeat): rework check_feature() [9] 3eaacdf0c fix(security): add clrbhb support [10] f973eca20 fix(cpus): workaround for Cortex-A715 erratum 2409570 [11] f70c757d8 fix(cpus): workaround for Cortex-A715 erratum 2376701 [12] bb5add11c fix(cpus): workaround for Cortex-A715 erratum 3711916 [13] 7486be6bf build(deps): bump js-yaml in the dev-deps group across 1 directory [14] [1] https://review.trustedfirmware.org/q/I0861d04ed95437e4ca9f203d9e79a6296b1ea… [2] https://review.trustedfirmware.org/q/Ib6862dbed55e5ffcd0fcd58b45a88cf925c54… [3] https://review.trustedfirmware.org/q/Ib6b704733e474824772cb27bd048b1e179d90… [4] https://review.trustedfirmware.org/q/I3d46fa70c80129ca0085d8245ee013f11a884… [5] https://review.trustedfirmware.org/q/I859012281fc67243f050d27e364f27434389c… [6] https://review.trustedfirmware.org/q/I23f5fa748377a920340b3c5a6584ccfadeea9… [7] https://review.trustedfirmware.org/q/I13b27c04c3da5ec80fa79422b4ef4fee64738… [8] https://review.trustedfirmware.org/q/I3c68b5f5d85ede37a6a039369de8ed2aa9205… [9] https://review.trustedfirmware.org/q/Idb182b0dd2aa77a0a5c5a349fe79a42fe1256… [10] https://review.trustedfirmware.org/q/Ie6e56e96378503456a1617d5e5d51bc64c2e0… [11] https://review.trustedfirmware.org/q/Id9429831525b842779d7b7e60f103c93be4ac… [12] https://review.trustedfirmware.org/q/Idcd2a07d269d55534dc5faa59c454d37426f2… [13] https://review.trustedfirmware.org/q/Iad149a2c02a804b3f4f0f2f5b89e866675cb4… [14] https://review.trustedfirmware.org/q/Ibec1d8a3c6620daeb0e663cfab929bca7bba8… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.26/change-log.html Thanks, TF-A LTS team

4 months

1
0
0 0

Changelog for v2.14 Release

by Arvind Ram Prakash

Hello Everyone, Please take a look at the changelog for your respective platforms ahead of the TF-A v2.14 release. The changelog is autogenerated from the commit messages of the patches that have been merged since the v2.13 release. Here's your chance to give us guidance on any small manual adjustments you would like to see. Patch: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/45309 Rendered Version: https://ci.trustedfirmware.org/job/tf-a-builder/890858/artifact/artefacts/r… Thanks, Arvind

4 months

1
0
0 0

AI Policy - Guidance on AI-assisted contributions

by Shaun Longhorn

All, Please be aware that today we have published our AI policy with Guidance on AI-assisted contributions. See the full details here: https://www.trustedfirmware.org/aipolicy/ Should you have any questions feel free to raise them. Thanks, Shaun Community Manager

4 months

1
0
0 0

Firmware-A v2.12 release code freeze notification

by Govindraj Raja

Hi All, The next release of the Firmware-A bundle of projects tagged v2.12 has an expected code freeze date of Nov, 8th 2024. Refer to the release cadence section from TF-A documentation (https://trustedfirmware-a.readthedocs.io/en/latest/about/release-informatio…). Closing out the release takes around 6-10 working days after the code freeze. v2.12 release preparation tasks start from now. We want to ensure that planned feature patches for the release are submitted in good time for the review process to conclude. As a kind recommendation and a matter of sharing CI resources, please launch CI jobs with care e.g.: -For simple platform, docs changes, or one liners, use Allow-CI+1 label (no need for a full Allow-CI+2 run). -For large patch stacks use Allow-CI+2 at top of the patch stack (and if required few individual Allow+CI+1 labels in the middle of the patch stack). -Carefully analyze results and fix the change if required, before launching new jobs on the same change. -If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not added as a gerrit comment on the patch right away please be patient as under heavy load CI jobs can be queued and in extreme conditions it can be over an hour before the Build start notice is issued. Issuing another Allow-CI+1 or Allow-CI+2 label will just result in an additional job being queued. -- Thanks, Govindraj R

4 months

2
2
0 0

Re: Question about SPM-MM SMC function ids

by Olivier Deprez

Hi, This issue was raised long time ago but unfortunately never got fixed/merged. It may be ok restoring the change and progress it: Https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/11002<https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/11002> Https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…<https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…> https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.… On a related note, I hope you saw the deprecation notice: https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.… Regards, Olivier. ________________________________ From: Sureshkumar Ponnusamy <sponnusamy(a)microsoft.com> Sent: 11 November 2025 05:46 To: David Daney <daviddaney(a)microsoft.com>; tf-a-owner(a)lists.trustedfirmware.org <tf-a-owner(a)lists.trustedfirmware.org> Cc: Giri Mudusuru <girimudusuru(a)microsoft.com>; Kun Qin <Kun.Qin(a)microsoft.com> Subject: RE: Question about SPM-MM SMC function ids Yes, the problem is in comparing logic and masks used. From: David Daney <daviddaney(a)microsoft.com> Sent: Monday, November 10, 2025 7:38 PM To: Sureshkumar Ponnusamy <sponnusamy(a)microsoft.com>; tf-a-owner(a)lists.trustedfirmware.org Cc: Giri Mudusuru <girimudusuru(a)microsoft.com>; Kun Qin <Kun.Qin(a)microsoft.com> Subject: Re: Question about SPM-MM SMC function ids According to the DEN0060A specification the only values used are: MM_VERSION: 0x8400 0040 MM_COMMUNICATE: 0x8400 0041/0xC400 0041 These don't overlap with the TRNG function IDs defined in DEN0098 David. ________________________________ From: Sureshkumar Ponnusamy <sponnusamy(a)microsoft.com<mailto:sponnusamy@microsoft.com>> Sent: Monday, November 10, 2025 7:32 PM To: tf-a-owner(a)lists.trustedfirmware.org<mailto:tf-a-owner@lists.trustedfirmware.org> <tf-a-owner(a)lists.trustedfirmware.org<mailto:tf-a-owner@lists.trustedfirmware.org>> Cc: Giri Mudusuru <girimudusuru(a)microsoft.com<mailto:girimudusuru@microsoft.com>>; David Daney <daviddaney(a)microsoft.com<mailto:daviddaney@microsoft.com>>; Kun Qin <Kun.Qin(a)microsoft.com<mailto:Kun.Qin@microsoft.com>> Subject: Question about SPM-MM SMC function ids Hi Manish, Levi Yun , TF-A community , I am facing an issue when enabling SPM-MM feature and it looks like there is a minor issue with the SMC ID range check. When SPM-MM is enabled, I cannot use the TRNG SMC services. /* These macros are used to identify SPM-MM calls using the SMC function ID */ #define SPM_MM_FID_MASK U(0xffff) #define SPM_MM_FID_MIN_VALUE U(0x40) #define SPM_MM_FID_MAX_VALUE U(0x7f) #define is_spm_mm_fid(_fid) \ ((((_fid) & SPM_MM_FID_MASK) >= SPM_MM_FID_MIN_VALUE) && \ (((_fid) & SPM_MM_FID_MASK) <= SPM_MM_FID_MAX_VALUE)) Here, the SPM-MM SMC ID range spans from 0x40 to 0x7F, which overlaps with the TRNG SMC service IDs: /* SMC function IDs for TRNG queries */ #define ARM_TRNG_VERSION U(0x84000050) #define ARM_TRNG_FEATURES U(0x84000051) #define ARM_TRNG_GET_UUID U(0x84000052) #define ARM_TRNG_RND32 U(0x84000053) #define ARM_TRNG_RND64 U(0xC4000053) Could you please clarify the rationale behind including the TRNG SMC IDs within the SPM-MM ID range? If this overlap was unintentional, we have to fix it. Looking forward to your insights and feedback on this matter. Thanks Suresh

4 months

2
1
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 6 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 493664: Control flow issues (DEADCODE) /lib/libc/strtoull.c: 106 in strtoull() _____________________________________________________________________________________________ *** CID 493664: Control flow issues (DEADCODE) /lib/libc/strtoull.c: 106 in strtoull() 100 else { 101 #ifdef __aarch64__ 102 uint128_t extended = (uint128_t)acc * (unsigned)base; 103 extended += (unsigned)c; 104 105 if (extended > ULLONG_MAX) { >>> CID 493664: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "any = -1;". 106 any = -1; 107 } else { 108 acc = (unsigned long long)extended; 109 any = 1; 110 } 111 #else ** CID 493663: Control flow issues (DEADCODE) /lib/libc/strtoul.c: 105 in strtoul() _____________________________________________________________________________________________ *** CID 493663: Control flow issues (DEADCODE) /lib/libc/strtoul.c: 105 in strtoul() 99 any = -1; 100 else { 101 extended = (unsigned long long)acc * (unsigned)base; 102 extended += (unsigned)c; 103 104 if (extended > (unsigned long long)ULONG_MAX) { >>> CID 493663: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "any = -1;". 105 any = -1; 106 } else { 107 acc = (unsigned long)extended; 108 any = 1; 109 } 110 } ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

4 months

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 493457: Control flow issues (UNREACHABLE) /plat/arm/board/fvp/fvp_spmd_logical_sp.c: 37 in fvp_get_partition_info() _____________________________________________________________________________________________ *** CID 493457: Control flow issues (UNREACHABLE) /plat/arm/board/fvp/fvp_spmd_logical_sp.c: 37 in fvp_get_partition_info() 31 * SPM. 32 * 33 * TODO: Integrate this helper function for a new anticipated feature. 34 */ 35 return; 36 >>> CID 493457: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "struct ffa_value ret = {0UL};". 37 struct ffa_value ret = { 0 }; 38 uint32_t target_uuid[4] = { 0 }; 39 static struct ffa_partition_info_v1_1 40 part_info[SPMD_LP_MAX_SUPPORTED_SP] = { 0 }; 41 42 uint16_t num_partitions = 0; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

4 months, 1 week

1
0
0 0

Invitation: TF-A Tech Forum - Hafnium future looking improvements @ Thu Nov 13, 2025 12pm - 1pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

TF-A Tech Forum - Hafnium future looking improvements Thursday Nov 13, 2025 ⋅ 12pm – 1pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Hi, This is a one off session for a partner to present coming improvements related to Hafnium project. Apologies for the meeting time not accommodating people in US timezones. We'll record the session and publish in the TF-A tech forum page as usual. Regards,Olivier.Trusted Firmware is inviting you to a scheduled Zoom meeting.Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Reply for tf-a(a)lists.trustedfirmware.org and view more details https://calendar.google.com/calendar/event?action=VIEW&eid=MDdmMGs0NjBkcW5q… Your attendance is optional. ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

4 months, 1 week

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 394590: Null pointer dereferences (NULL_RETURNS) _____________________________________________________________________________________________ *** CID 394590: Null pointer dereferences (NULL_RETURNS) /lib/libfdt/fdt_overlay.c: 788 in overlay_apply_node() 782 &prop_len); 783 if (prop_len == -FDT_ERR_NOTFOUND) 784 return -FDT_ERR_INTERNAL; 785 if (prop_len < 0) 786 return prop_len; 787 >>> CID 394590: Null pointer dereferences (NULL_RETURNS) >>> Dereferencing a pointer that might be "NULL" "prop" when calling "fdt_setprop". 788 ret = fdt_setprop(fdt, target, name, prop, prop_len); 789 if (ret) 790 return ret; 791 } 792 793 fdt_for_each_subnode(subnode, fdto, node) { ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

4 months, 1 week

1
0
0 0

Trusted Firmware-A LTS v2.12.8 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.12.8 is now available. This release contains the following patches: 776781d6d fix(simd): fix base register in fpregs_context_* [1] 0dba1a220 fix(cpus): workaround for Cortex-A720 erratum 3711910 [2] 6cce5175f fix(cpus): workaround for Cortex-A720 erratum 2729604 [3] ccb421921 refactor: fix workaround order for Cortex-A720 [4] 200fa2012 fix(spm-mm): prevent excessive racing [5] [1] https://review.trustedfirmware.org/q/I757a26f8910c2ab648116e001e06baa3deb2e… [2] https://review.trustedfirmware.org/q/Id65d5ba41b96648b07c09df77fb25cc4bdb50… [3] https://review.trustedfirmware.org/q/I4567d75ba9f17146d0d7bc5cdb622bb63efad… [4] https://review.trustedfirmware.org/q/I6770567a9580973ceedb5911f0a495391ef9e… [5] https://review.trustedfirmware.org/q/I0861d04ed95437e4ca9f203d9e79a6296b1ea… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.8/change-log.html Thanks, TF-A LTS team

4 months, 2 weeks

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 4 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 4 of 4 defect(s) ** CID 491156: (DEADCODE) /drivers/st/usb_dwc3/usb_dwc3.c: 1741 in dwc3_handle_dev_event() /drivers/st/usb_dwc3/usb_dwc3.c: 1724 in dwc3_handle_dev_event() /drivers/st/usb_dwc3/usb_dwc3.c: 1718 in dwc3_handle_dev_event() _____________________________________________________________________________________________ *** CID 491156: (DEADCODE) /drivers/st/usb_dwc3/usb_dwc3.c: 1741 in dwc3_handle_dev_event() 1735 return action; 1736 } 1737 } 1738 1739 /* Clear Stall for all EP except EP0OUT k = USB_DWC3_NUM_OUT_EP */ 1740 for (i = 1; i < USB_DWC3_NUM_OUT_EP; i++) { >>> CID 491156: (DEADCODE) >>> Execution cannot reach this statement: "ep = &dwc3_handle->OUT_ep[i];". 1741 ep = &dwc3_handle->OUT_ep[i]; 1742 1743 if (!ep->is_stall) { 1744 continue; 1745 } 1746 /drivers/st/usb_dwc3/usb_dwc3.c: 1724 in dwc3_handle_dev_event() 1718 dwc3_ep_stop_xfer(dwc3_handle, 1719 &dwc3_handle->pcd_handle->out_ep[i]); 1720 } 1721 1722 /* Clear Stall for all EP except EP0IN k = USB_DWC3_NUM_IN_EP */ 1723 for (i = 1; i < USB_DWC3_NUM_IN_EP; i++) { >>> CID 491156: (DEADCODE) >>> Execution cannot reach this statement: "ep = &dwc3_handle->IN_ep[i];". 1724 ep = &dwc3_handle->IN_ep[i]; 1725 1726 if (!ep->is_stall) { 1727 continue; 1728 } 1729 /drivers/st/usb_dwc3/usb_dwc3.c: 1718 in dwc3_handle_dev_event() 1712 dwc3_ep_stop_xfer(dwc3_handle, 1713 &dwc3_handle->pcd_handle->in_ep[i]); 1714 } 1715 1716 /* Stop transfers for all EP except EP0OUT k = USB_DWC3_NUM_OUT_EP */ 1717 for (i = 1; i < USB_DWC3_NUM_OUT_EP; i++) { >>> CID 491156: (DEADCODE) >>> Execution cannot reach this statement: "dwc3_ep_stop_xfer(dwc3_hand...". 1718 dwc3_ep_stop_xfer(dwc3_handle, 1719 &dwc3_handle->pcd_handle->out_ep[i]); 1720 } 1721 1722 /* Clear Stall for all EP except EP0IN k = USB_DWC3_NUM_IN_EP */ 1723 for (i = 1; i < USB_DWC3_NUM_IN_EP; i++) { ** CID 491155: API usage errors (PW.PRINTF_ARG_MISMATCH) /drivers/st/usb_dwc3/usb_dwc3.c: 698 in () _____________________________________________________________________________________________ *** CID 491155: API usage errors (PW.PRINTF_ARG_MISMATCH) /drivers/st/usb_dwc3/usb_dwc3.c: 698 in () 692 } 693 return USBD_OK; 694 } 695 696 /* Can be called from interrupt context hence cannot wait for Tick */ 697 if (timeout_elapsed(timeout)) { >>> CID 491155: API usage errors (PW.PRINTF_ARG_MISMATCH) >>> argument is incompatible with corresponding format string conversion (expected type "unsigned long" but argument has type "int") 698 ERROR("TIMEOUT Command Complete --> %u PHYEP%lu %x\n", 699 DWC3_DEPCMD_STATUS(reg), phy_epnum, reg); 700 /* "Command Timed Out" */ 701 return USBD_TIMEOUT; 702 } 703 } while (true); ** CID 491154: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /drivers/st/usb_dwc3/usb_dwc3.c: 2341 in usb_dwc3_init_driver() _____________________________________________________________________________________________ *** CID 491154: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /drivers/st/usb_dwc3/usb_dwc3.c: 2341 in usb_dwc3_init_driver() 2335 /* 2336 * We are doing 1:1 alternate mapping for endpoints, meaning 2337 * IN Endpoint X maps to Physical Endpoint 2*X +1 and 2338 * OUT Endpoint X maps to Physical Endpoint 2*X. 2339 * So USB endpoint 0x81 is 0x03. 2340 */ >>> CID 491154: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "(i | (128UL /* (uint64_t)1ULL << 7 */)) & (128UL /* (uint64_t)1ULL << 7 */)" is always 0x80 regardless of the values of its operands. This occurs as a value. 2341 dwc3_handle->IN_ep[i].phy_epnum = __HAL_PCD_EPADDR_TO_PHYEPNUM(i | EP_DIR_IN); 2342 2343 dwc3_handle->IN_ep[i].intr_num = PCD_DEV_EVENTS_INTR; 2344 } 2345 2346 for (i = 0; i < USB_DWC3_NUM_OUT_EP ; i++) { ** CID 491153: (UNINIT) _____________________________________________________________________________________________ *** CID 491153: (UNINIT) /plat/nxp/soc-ls1046a/soc.c: 299 in soc_mem_access() 293 dram_idx, index, 294 info_dram_regions->region[dram_idx].addr, 295 info_dram_regions->region[dram_idx].size, 296 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 297 } 298 >>> CID 491153: (UNINIT) >>> Using uninitialized value "tzc400_reg_list->start_addr" when calling "mem_access_setup". 299 mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list); 300 } 301 302 #else /* IMAGE_BL2 */ 303 /* Functions for BL31 */ 304 /plat/nxp/soc-lx2160a/soc.c: 409 in soc_mem_access() 403 tzc400_reg_list); 404 mem_access_setup(NXP_TZC3_ADDR, index, 405 tzc400_reg_list); 406 } 407 if (devdisr5_info->ddrc2_present != 0) { 408 INFO("DDR Controller 2.\n"); >>> CID 491153: (UNINIT) >>> Using uninitialized value "tzc400_reg_list->start_addr" when calling "mem_access_setup". 409 mem_access_setup(NXP_TZC2_ADDR, index, 410 tzc400_reg_list); 411 mem_access_setup(NXP_TZC4_ADDR, index, 412 tzc400_reg_list); 413 } 414 } /plat/nxp/soc-lx2160a/soc.c: 411 in soc_mem_access() 405 tzc400_reg_list); 406 } 407 if (devdisr5_info->ddrc2_present != 0) { 408 INFO("DDR Controller 2.\n"); 409 mem_access_setup(NXP_TZC2_ADDR, index, 410 tzc400_reg_list); >>> CID 491153: (UNINIT) >>> Using uninitialized value "tzc400_reg_list->start_addr" when calling "mem_access_setup". 411 mem_access_setup(NXP_TZC4_ADDR, index, 412 tzc400_reg_list); 413 } 414 } 415 416 #else /plat/nxp/soc-ls1088a/soc.c: 222 in soc_mem_access() 216 dram_idx, index, 217 info_dram_regions->region[dram_idx].addr, 218 info_dram_regions->region[dram_idx].size, 219 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 220 } 221 >>> CID 491153: (UNINIT) >>> Using uninitialized value "tzc400_reg_list->start_addr" when calling "mem_access_setup". 222 mem_access_setup(NXP_TZC_ADDR, index, 223 tzc400_reg_list); 224 } 225 226 /* 227 * This function implements soc specific erratum /plat/nxp/soc-lx2160a/soc.c: 404 in soc_mem_access() 398 } 399 400 if (devdisr5_info->ddrc1_present != 0) { 401 INFO("DDR Controller 1.\n"); 402 mem_access_setup(NXP_TZC_ADDR, index, 403 tzc400_reg_list); >>> CID 491153: (UNINIT) >>> Using uninitialized value "tzc400_reg_list->start_addr" when calling "mem_access_setup". 404 mem_access_setup(NXP_TZC3_ADDR, index, 405 tzc400_reg_list); 406 } 407 if (devdisr5_info->ddrc2_present != 0) { 408 INFO("DDR Controller 2.\n"); 409 mem_access_setup(NXP_TZC2_ADDR, index, /plat/nxp/soc-lx2160a/soc.c: 402 in soc_mem_access() 396 info_dram_regions->region[dram_idx].size, 397 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 398 } 399 400 if (devdisr5_info->ddrc1_present != 0) { 401 INFO("DDR Controller 1.\n"); >>> CID 491153: (UNINIT) >>> Using uninitialized value "tzc400_reg_list->start_addr" when calling "mem_access_setup". 402 mem_access_setup(NXP_TZC_ADDR, index, 403 tzc400_reg_list); 404 mem_access_setup(NXP_TZC3_ADDR, index, 405 tzc400_reg_list); 406 } 407 if (devdisr5_info->ddrc2_present != 0) { ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

4 months, 2 weeks

1
0
0 0

TF-A Tech Forum on Thu Oct 30th 2025 4.00pm UK

by Olivier Deprez

(re-sending as it seems this email did not properly reach the ML) Hi, On Oct 30th in the TF-A Tech Forum, two different sessions of 30 minutes each will be presented: TF-A SMC fuzzer improvements - Slava Andrianov * Motivating secure world fuzzing * Fuzzer configuration improvements * Future fuzzing work TF-RMM ID registers management - Sona Rebecca Mathew * Earlier RMM directly read ID registers, creating a dependency on EL3 revisions to enable features forcing a version compatibility between the two. * New approach: EL3 capabilities are queried via an SMC call and RMM now uses cached ID register copies populated at cold boot. Includes forward-looking support for FEAT_IDTE3 in TF-A. Regards, Olivier. TF-A Tech Forum Thursday Oct 30, 2025 ⋅ 5pm – 6pm (Central European Time - Paris) Trusted Firmware is inviting you to a scheduled Zoom meeting. Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Join Zoom Meeting https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… Meeting ID: 935 5786 3987 Passcode: 939141 --- One tap mobile +12532158782,,93557863987# US (Tacoma) +13017158592,,93557863987# US (Washington DC) --- Dial by your location • +1 253 215 8782 US (Tacoma) • +1 301 715 8592 US (Washington DC) • +1 305 224 1968 US • +1 309 205 3325 US • +1 312 626 6799 US (Chicago) • +1 346 248 7799 US (Houston) • +1 360 209 5623 US • +1 386 347 5053 US • +1 507 473 4847 US • +1 564 217 2000 US • +1 646 558 8656 US (New York) • +1 646 931 3860 US • +1 669 444 9171 US • +1 669 900 9128 US (San Jose) • +1 689 278 1000 US • +1 719 359 4580 US • +1 253 205 0468 US • 833 548 0276 US Toll-free • 833 548 0282 US Toll-free • 833 928 4608 US Toll-free • 833 928 4609 US Toll-free • 833 928 4610 US Toll-free • 877 853 5247 US Toll-free • 888 788 0099 US Toll-free Meeting ID: 935 5786 3987 Find your local number: https://linaro-org.zoom.us/u/adoz9mILli

4 months, 2 weeks

1
0
0 0

TF-A Tech Forum on Thu Oct 30th 2025 4.00pm UK

by Olivier Deprez

Hi, On Oct 30th in the TF-A Tech Forum, two different sessions of 30 minutes each will be presented: TF-A SMC fuzzer improvements - Slava Andrianov * Motivating secure world fuzzing * Fuzzer configuration improvements * Future fuzzing work TF-RMM ID registers management - Sona Rebecca Mathew * Earlier RMM directly read ID registers, creating a dependency on EL3 revisions to enable features forcing a version compatibility between the two. * New approach: EL3 capabilities are queried via an SMC call and RMM now uses cached ID register copies populated at cold boot. Includes forward-looking support for FEAT_IDTE3 in TF-A. Regards, Olivier. TF-A Tech Forum Thursday Oct 30, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com

4 months, 2 weeks

1
0
0 0

Marvell a3700 build failure after toolchain update

by Jayanth Dodderi Chidanand

Hi All, During the TF-A CI upgrade from Arm GNU Toolchain version 14.2.Rel1 to 14.3.Rel1 [1], the Marvell A3700 platform build began failing. Since TF-A does not include the WTMI sources and there has been no response from the Marvell maintainers, the platform has been temporarily removed from the CI [2]. We will restore it once the fix lands in the Marvell upstream and links cleanly with 14.3/binutils 2.44. The sections below outline the CI environment, build configuration, and error details for reference. * Test config tf-l1-build-plat/a3700-default:nil * * CI Test Environment Host: Ubuntu 22.04 (Docker) Toolchains: aarch64-none-elf: Arm GNU 14.3.Rel1 arm-none-eabi (CM3/WTMI): Arm GNU 14.3.Rel1 (fails); passes with 14.2.Rel1 * Representative build params: make CROSS_COMPILE=aarch64-none-elf- CROSS_CM3=arm-none-eabi- PLAT=a3700 BL33=/dev/null CM3_SYSTEM_RESET=1 A3720_DB_PM_WAKEUP_SRC=1 CLOCKSPRESET=CPU_1000_DDR_800 DDR_TOPOLOGY=5 DEBUG=1 V=1 * Build Failure: (*ABS*0x1fff0000): Unknown destination type (ARM/Thumb) in main.o (.text.startup+0x2a): dangerous relocation: unsupported relocation /home/../.../arm-none-eabi/bin/ld: warning: build/sys_init.elf has a LOAD segment with RWX permissions /home/../.../arm-none-eabi/bin/ld: (*ABS*0x1fff0000): Unknown destination type (ARM/Thumb) in main.o main.o: in function `main': .../A3700-utils-marvell/wtmi/sys_init/main.c:350:(.text.startup+0x2a): dangerous relocation: unsupported relocation collect2: error: ld returned 1 exit status Root Cause On Cortex-M (Thumb-only), calls/jumps to absolute addresses must have bit0 = 1 to indicate Thumb state. Older binutils tolerated raw addresses like 0x1FFF0000; binutils 2.44 now errors if the destination state is unknown (no stub is inserted). Requested fix (in WTMI sources) Please update any absolute branch/call targets to be explicitly Thumb (LSB=1), or define a Thumb symbol and call that. Acceptance criteria: WTMI links cleanly with arm-none-eabi 14.3.Rel1 (binutils 2.44) with no: * Unknown destination type (ARM/Thumb) * dangerous relocation: unsupported relocation [1] https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads [2] https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/44444/5 Thanks & regards, Jayanth

4 months, 2 weeks

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu Nov 13, 2025 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Cancelling the Nov 13th instance." TF-A Tech Forum Thursday Nov 13, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

4 months, 3 weeks

1
0
0 0

Trusted Firmware-A LTS v2.12.7 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.12.7 is now available. This release contains the following patches: 7a241814b fix(smccc): cleanup unused declaration [1] 616a7983d fix(cpus): inform the compiler that struct cpu_ops is aligned [2] 01d80d085 docs(security): update Advisory TFV-6 [3] 79ba33aa3 fix(cpus): use correct Makefile indentation for CVE-2018-3639 check [4] 84e8bc22f build(allwinner): disable unneeded CVE workarounds and MPAM [5] 9cb5a78aa fix(aarch32): make get_cpu_ops_ptr() PCS compliant [6] 7c300227e fix(cpus): workaround for Cortex-A510 erratum 2008766 [7] 4e62dbf9b fix(cpus): workaround for Cortex-A510 erratum 2169012 [8] 399477f9f fix(cpus): workaround for Cortex-A510 erratum 2218134 [9] 05f71e344 fix(cpus): workaround for Cortex-A510 erratum 2420992 [10] 8c67b1a27 fix(cpus): workaround for Cortex-A510 erratum 3672349 [11] 1f547e228 fix(cpus): workaround for Cortex-A510 erratum 3704847 [12] e26cd2c52 fix(cpus): workaround for Neoverse-V2 erratum 3841324 [13] 72f26f182 fix(cpus): workaround for Neoverse-V2 erratum 3701771 [14] [1] https://review.trustedfirmware.org/q/Iae81e0bcbd2feb2b72a4e4e8fd27a27ae00c9… [2] https://review.trustedfirmware.org/q/Id38d6f1b92527b8a414cfbb856a5a82c76a1b… [3] https://review.trustedfirmware.org/q/Icb3d039c8949fd6036c729a845646170710ba… [4] https://review.trustedfirmware.org/q/Ieb56af33a11c40b6753738669eee929c26426… [5] https://review.trustedfirmware.org/q/Ibc52a4fc9b8f5d9b2b28a2ce13d3ab99b63e9… [6] https://review.trustedfirmware.org/q/I7f3b50e56a1288d2a8136a7b8c01544bab19c… [7] https://review.trustedfirmware.org/q/Id1aa0f2c518a055363c962f9abdb27e1ee8bf… [8] https://review.trustedfirmware.org/q/Ifdd59c09e84252dc292600630d81d32986fd6… [9] https://review.trustedfirmware.org/q/Ifec40dee2f7e42c56c9ed447b6b1997b170f9… [10] https://review.trustedfirmware.org/q/Ia76ba2431d76f14c08b95a998806986190d68… [11] https://review.trustedfirmware.org/q/I9786ab8843a2eab45e650c6af50b693348152… [12] https://review.trustedfirmware.org/q/I2c7c8da9c66471115b5bf8fb5c87d4de46ca2… [13] https://review.trustedfirmware.org/q/I9b3a5266103e5000d207c7a270c65455d0646… [14] https://review.trustedfirmware.org/q/Ic0ad68f7bd393bdc03343d5ba815adb23bf6a… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.7/change-log.html Thanks, TF-A LTS team

4 months, 4 weeks

1
0
0 0

Deprecating SPM-MM

by Olivier Deprez

Hi, In light of coming TF-A v2.14 in November, we would like to mark the SPM-MM implementation [1] as deprecated. Our understanding is that it's not longer very actively used at least from an upstream perspective, while most SPM sw architecures have adopted/migrated to the FF-A standard [2] [3]. The intent would be to remove this implementation completely from next release in May 26 onwards. This would remove the maintenance burden for 3 orthogonal options, reducing to the 2 FF-A compliant implementations. Simplification also comes to the testing side and CI. The SPM-MM implementation would continue to be supported in LTS branches maintained for 7 years. Let us know if this causes major concerns. Thanks, Regards, Olivier. [1] https://trustedfirmware-a.readthedocs.io/en/latest/components/secure-partit… [2] https://trustedfirmware-a.readthedocs.io/en/latest/components/secure-partit… [3] https://trustedfirmware-a.readthedocs.io/en/latest/components/el3-spmc.html

4 months, 4 weeks

1
0
0 0

Firmware-A v2.13 release code freeze notification

by Olivier Deprez

Hi All, The next release of the Firmware-A bundle of projects tagged v2.13 has an expected code freeze date of May, 2nd 2025. In order to accommodate the Linaro connect event occurring during the week of May 12th we may extend the release completion date up until the week of May 26th. v2.13 release preparation tasks start from now. We want to ensure that planned feature patches for the release are submitted in good time for the review process to conclude. As a kind recommendation and a matter of sharing CI resources, please launch CI jobs with care e.g.: -For simple platform, docs changes, or one liners, use Allow-CI+1 label (no need for a full Allow-CI+2 run). -For large patch stacks use Allow-CI+2 at top of the patch stack (and if required few individual Allow+CI+1 labels in the middle of the patch stack). -Carefully analyze results and fix the change if required, before launching new jobs on the same change. -If after issuing a Allow-CI+1 or Allow-CI+2 label a Build start notice is not added as a gerrit comment on the patch right away please be patient as under heavy load CI jobs can be queued and in extreme conditions it can be over an hour before the Build start notice is issued. Issuing another Allow-CI+1 or Allow-CI+2 label will just result in an additional job being queued. Regards, Olivier.

5 months

1
2
0 0

Trusted Firmware-A LTS v2.8.39 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.39 is now available. This release contains the following patches: 8d101b32e fix(cpus): workaround for Cortex-A720 erratum 3711910 [1] 7e9945ac3 fix(cpus): workaround for Cortex-A720 erratum 2729604 [2] 8ba721842 refactor: fix workaround order for Cortex-A720 [3] [1] https://review.trustedfirmware.org/q/Id65d5ba41b96648b07c09df77fb25cc4bdb50… [2] https://review.trustedfirmware.org/q/I4567d75ba9f17146d0d7bc5cdb622bb63efad… [3] https://review.trustedfirmware.org/q/I6770567a9580973ceedb5911f0a495391ef9e… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.39/change-log.html Thanks, TF-A LTS team

5 months

1
0
0 0

TF-A Tech Forum Oct 16th 4.00pm (UK) - Secure Partitions Live Firmware Activation

by Olivier Deprez

Hi, On Oct 16th in the TF-A Tech Forum, Madhukar Pappireddy will present his work on secure partitions live firmware activation: requirements, implementation overview, and challenges. Regards, Olivier. TF-A Tech Forum Thursday Oct 16, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com

5 months

1
0
0 0

Trusted Firmware-A LTS v2.10.25 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.25 is now available. This release contains the following patches: a4d0e8156 fix(cpus): workaround for Neoverse-V2 erratum 3841324 [1] 94610488d fix(cpus): workaround for Neoverse-V2 erratum 3701771 [2] b5a976a0c fix(cpus): workaround for Cortex-A720 erratum 3711910 [3] af2b4d148 fix(cpus): workaround for Cortex-A720 erratum 2729604 [4] 9344c4e10 refactor: fix workaround order for Cortex-A720 [5] [1] https://review.trustedfirmware.org/q/I9b3a5266103e5000d207c7a270c65455d0646… [2] https://review.trustedfirmware.org/q/Ic0ad68f7bd393bdc03343d5ba815adb23bf6a… [3] https://review.trustedfirmware.org/q/Id65d5ba41b96648b07c09df77fb25cc4bdb50… [4] https://review.trustedfirmware.org/q/I4567d75ba9f17146d0d7bc5cdb622bb63efad… [5] https://review.trustedfirmware.org/q/I6770567a9580973ceedb5911f0a495391ef9e… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.25/change-log.html Thanks, TF-A LTS team

5 months

1
0
0 0

Rethrow SEA from EL3 to lower EL on arm64

by Venkata Pokkuluri

In Firmware First Handling (FFH), all external aborts are trapped to EL3, they can be notified to OS/VM using SDEI or by reinjecting SEA. SDEI is imprecise exception and asynchronous. GHES driver defines SEA as the only synchronous mechanism ( https://github.com/torvalds/linux/blob/master/drivers/acpi/apei/ghes.c#L118), hence SEA reinjection is useful for SEA's where OS/VM takes appropriate action. For example when an user space application running at EL0 consumes a poisoned memory by re-throwing SEA the kernel can terminate the individual application. For SEA Reinjection we need to figure out the right EL to reinject the SEA to and then copy ESR_EL3, SPSR_EL3, ELR_EL3 and FAR_EL3 to target ELs respective registers and calculate new PSTATE for EL3. To find target_el reference code is provided in SyncExternalAbortTarget (J1.3.2.7) in ARM DDI 0487L.a.

5 months, 1 week

2
1
0 0

Trusted Firmware-A LTS v2.8.38 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.38 is now available. This release contains the following patches: 350252f46 fix(cpus): workaround for Cortex-A510 erratum 2008766 [1] 50c936b5a fix(cpus): workaround for Cortex-A510 erratum 2169012 [2] a8dcd1673 fix(cpus): workaround for Cortex-A510 erratum 2218134 [3] 65711740d fix(cpus): workaround for Cortex-A510 erratum 2420992 [4] 372e1322d fix(cpus): workaround for Cortex-A510 erratum 3672349 [5] bdefd871d fix(cpus): workaround for Cortex-A510 erratum 3704847 [6] dcbc9b2ea fix(cpus): workaround for Neoverse-V2 erratum 3841324 [7] 17e7be571 fix(cpus): workaround for Neoverse-V2 erratum 3701771 [8] [1] https://review.trustedfirmware.org/q/Id1aa0f2c518a055363c962f9abdb27e1ee8bf… [2] https://review.trustedfirmware.org/q/Ifdd59c09e84252dc292600630d81d32986fd6… [3] https://review.trustedfirmware.org/q/Ifec40dee2f7e42c56c9ed447b6b1997b170f9… [4] https://review.trustedfirmware.org/q/Ia76ba2431d76f14c08b95a998806986190d68… [5] https://review.trustedfirmware.org/q/I9786ab8843a2eab45e650c6af50b693348152… [6] https://review.trustedfirmware.org/q/I2c7c8da9c66471115b5bf8fb5c87d4de46ca2… [7] https://review.trustedfirmware.org/q/I9b3a5266103e5000d207c7a270c65455d0646… [8] https://review.trustedfirmware.org/q/Ic0ad68f7bd393bdc03343d5ba815adb23bf6a… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.38/change-log.html Thanks, TF-A LTS team

5 months, 1 week

1
0
0 0

Trusted Firmware-A LTS v2.10.24 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.24 is now available. This release contains the following patches: a130a58ec feat(mbedtls): update mbedtls to version 3.6.4 [1] [1] https://review.trustedfirmware.org/q/I57c9c14aabe75a51c74dcf2a33faf59f95ce2… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.24/change-log.html Thanks, TF-A LTS team

5 months, 1 week

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu Oct 2, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling as no topic planned for today. Regards, Olivier. " TF-A Tech Forum Thursday Oct 2, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests qwandor(a)google.com praan(a)google.com jeremimiller(a)google.com tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

5 months, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.10.23 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.23 is now available. This release contains the following patches: fd0b9fc9e build(deps-dev): bump sphinx-rtd-theme from 1.2.0 to 1.3.0 [1] e57596f83 build(deps-dev): bump anytree from 2.8.0 to 2.12.1 [2] 5f0adf430 build(deps-dev): bump click from 8.1.3 to 8.1.8 [3] b0372fb95 build(deps-dev): bump prettytable from 3.7.0 to 3.11.0 [4] bc8e2505a build(dev-deps): bump brace-expansion [5] f665e3e59 fix(cpus): workaround for Cortex-A510 erratum 2008766 [6] b32738dcd fix(cpus): workaround for Cortex-A510 erratum 2169012 [7] 8338b416f fix(cpus): workaround for Cortex-A510 erratum 2218134 [8] bc5a532bf fix(cpus): workaround for Cortex-A510 erratum 2420992 [9] 021e3d449 fix(cpus): workaround for Cortex-A510 erratum 3672349 [10] d6b88dc8a fix(cpus): workaround for Cortex-A510 erratum 3704847 [11] [1] https://review.trustedfirmware.org/q/I8cb732e9d7cbf8359449a8f661dd6c7a09aba… [2] https://review.trustedfirmware.org/q/Ic3cedf9f6e6f9d364647e150d8574f682eb59… [3] https://review.trustedfirmware.org/q/I39e7c3dc92d1a50d0fd5b60c84b2bdb9f3a46… [4] https://review.trustedfirmware.org/q/I182e0845cb9df90f6536fbe6dc5b654d95fee… [5] https://review.trustedfirmware.org/q/I1613e2e8fe36abe22390b41d520ac5916cf24… [6] https://review.trustedfirmware.org/q/Id1aa0f2c518a055363c962f9abdb27e1ee8bf… [7] https://review.trustedfirmware.org/q/Ifdd59c09e84252dc292600630d81d32986fd6… [8] https://review.trustedfirmware.org/q/Ifec40dee2f7e42c56c9ed447b6b1997b170f9… [9] https://review.trustedfirmware.org/q/Ia76ba2431d76f14c08b95a998806986190d68… [10] https://review.trustedfirmware.org/q/I9786ab8843a2eab45e650c6af50b693348152… [11] https://review.trustedfirmware.org/q/I2c7c8da9c66471115b5bf8fb5c87d4de46ca2… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.23/change-log.html Thanks, TF-A LTS team

5 months, 2 weeks

1
0
0 0

TF-A Tech Forum (Thu Sep 18th) - Introducing Rusted Firmware-A

by Olivier Deprez

Hi, On Sep 18th in the TF-A Tech forum, Sandrine Afsa will present on the newly announced Rusted Firmware-A and Arm firmware crates projects with the following agenda: Introducing RF-A & Arm Firmware Crates projects v0.1 release contents Roadmap Request for feedback Regards, Olivier. TF-A Tech Forum Thursday Sep 18, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org qwandor(a)google.com praan(a)google.com

5 months, 3 weeks

2
1
0 0

Trusted Firmware-A LTS v2.8.37 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.37 is now available. This release contains the following patches: 00b2f9f9e fix(cpus): use correct Makefile indentation for CVE-2018-3639 check [1] 3d25bdfca build(allwinner): disable unneeded CVE workarounds and MPAM [2] c56bd3a42 fix(smccc): cleanup unused declaration [3] 6be9e30f8 docs(security): update Advisory TFV-6 [4] 4f6a7e4b1 fix(aarch32): make get_cpu_ops_ptr() PCS compliant [5] 15bf0a7ec fix(cpus): inform the compiler that struct cpu_ops is aligned [6] [1] https://review.trustedfirmware.org/q/Ieb56af33a11c40b6753738669eee929c26426… [2] https://review.trustedfirmware.org/q/Ibc52a4fc9b8f5d9b2b28a2ce13d3ab99b63e9… [3] https://review.trustedfirmware.org/q/Iae81e0bcbd2feb2b72a4e4e8fd27a27ae00c9… [4] https://review.trustedfirmware.org/q/Icb3d039c8949fd6036c729a845646170710ba… [5] https://review.trustedfirmware.org/q/I7f3b50e56a1288d2a8136a7b8c01544bab19c… [6] https://review.trustedfirmware.org/q/Id38d6f1b92527b8a414cfbb856a5a82c76a1b… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.37/change-log.html Thanks, TF-A LTS team

5 months, 3 weeks

1
0
0 0

Trusted Firmware-A LTS v2.10.22 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.22 is now available. This release contains the following patches: 685617980 fix(cpus): inform the compiler that struct cpu_ops is aligned [1] 3466985b9 fix(smccc): cleanup unused declaration [2] bb1fcfd2f fix(cpus): use correct Makefile indentation for CVE-2018-3639 check [3] 61d9a828c build(allwinner): disable unneeded CVE workarounds and MPAM [4] c4bff8bfb fix(aarch32): make get_cpu_ops_ptr() PCS compliant [5] [1] https://review.trustedfirmware.org/q/Id38d6f1b92527b8a414cfbb856a5a82c76a1b… [2] https://review.trustedfirmware.org/q/Iae81e0bcbd2feb2b72a4e4e8fd27a27ae00c9… [3] https://review.trustedfirmware.org/q/Ieb56af33a11c40b6753738669eee929c26426… [4] https://review.trustedfirmware.org/q/Ibc52a4fc9b8f5d9b2b28a2ce13d3ab99b63e9… [5] https://review.trustedfirmware.org/q/I7f3b50e56a1288d2a8136a7b8c01544bab19c… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.22/change-log.html Thanks, TF-A LTS team

5 months, 3 weeks

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 490141: Control flow issues (NO_EFFECT) /contrib/libeventlog/src/event_log.c: 264 in event_log_init_and_reg() _____________________________________________________________________________________________ *** CID 490141: Control flow issues (NO_EFFECT) /contrib/libeventlog/src/event_log.c: 264 in event_log_init_and_reg() 258 int rc = event_log_init(start, finish); 259 if (rc < 0) { 260 return rc; 261 } 262 263 if (hash_info == NULL || hash_info->func == NULL || >>> CID 490141: Control flow issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "hash_info->count < 0UL". 264 hash_info->count < 0 || hash_info->count > HASH_ALG_COUNT) { 265 return -EINVAL; 266 } 267 268 crypto_hash_info = hash_info; 269 return 0; ** CID 490140: Memory - illegal accesses (OVERRUN) _____________________________________________________________________________________________ *** CID 490140: Memory - illegal accesses (OVERRUN) /contrib/libeventlog/src/event_print.c: 46 in event_log_print_spaced_hex() 40 event_log_append_str(output_buf, cap, &pos, prefix); 41 42 for (size_t off = 0; off < buf_len; off += 16U) { 43 chunk = (buf_len - off >= 16U) ? 16U : (buf_len - off); 44 45 /* write the 16-byte (or tail) chunk */ >>> CID 490140: Memory - illegal accesses (OVERRUN) >>> Overrunning array of 256 bytes at byte offset 256 by dereferencing pointer "output_buf + pos". 46 pos += event_log_write_hex_spaced(output_buf + pos, 47 (pos < cap) ? (cap - pos) : 0, 48 chunk, buf + off); 49 50 NOTICE(" %s\n", output_buf); 51 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

5 months, 3 weeks

1
0
0 0

Adding support for phyCORE AM62L in TF-A

by Florijan Plohl

Hello! We’d like to add support in TF-A for the PHYTEC phyCORE AM62L. On this board we need BL1 to read the on-board EEPROM via I2C to set the correct DRAM timings. Right now we have it working by editing the TI AM62L files on TI's TF-A fork and adding the EEPROM and I2C drivers. Our questions are: - Should we create a separate board for phyCORE AM62L, or would it make more sense to include this as an option in the TI AM62L support? - How much abstraction should we implement for EEPROM and I2C drivers? Thanks for any advice! Best regards, Florijan Plohl

6 months

3
3
0 0

FW: CI infrastructure scheduled maintenance: 12th Sep 2025

by Joanna Farley

FYI From: Saheer Babu via Tf-openci <tf-openci(a)lists.trustedfirmware.org> Date: Wednesday, 10 September 2025 at 15:17 To: tf-openci(a)lists.trustedfirmware.org <tf-openci(a)lists.trustedfirmware.org> Subject: [Tf-openci] CI infrastructure scheduled maintenance: 12th Sep 2025 Hi all, We will be performing upgrade of the clusters hosting review.trustedfirmware.org and ci.trustedfirmware.org on Friday, 12th Sep 2025 at 16:00 GMT+1. During this maintenance window, both services will be unavailable for approximately 4 hours. A follow-up email will be sent once the services are fully restored. Best regards, Saheer IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -- Tf-openci mailing list -- tf-openci(a)lists.trustedfirmware.org To unsubscribe send an email to tf-openci-leave(a)lists.trustedfirmware.org

6 months

2
1
0 0

Canceled event with note: TF-A Tech Forum @ Thu Sep 4, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi Cancelling as no topic proposed for this week. Regards, Olivier. " TF-A Tech Forum Thursday Sep 4, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

6 months, 1 week

1
0
0 0

Raspberry Pi-5 platform maintainer

by Manish Pandey2

Hi, I’m looking for details on the Raspberry Pi 5 (RPi5) platform port in TF-A and to identify a potential platform owner/maintainer. I can see an RPi5 port attributed to @mariobalanica02@gmail.com<mailto:mariobalanica02@gmail.com>, but [1] doesn’t list a platform owner for this target. I also haven’t found TF-A documentation describing the software stack or the current level of testing for RPi5. Could someone please point me to: The current platform owner/maintainer, design/bring-up notes around SW stack or testing? [1] : https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a.git… Thanks Manish

6 months, 1 week

1
0
0 0

Does FVP_Base_RevC-2xAEMvA platform model has a full support for address translation at PL2 stage-1 MMU in aarch32?

by Marek

Have you ever succeeded in performing a Stage-1 MMU translation using LPAE (Long Physical Address Extension) on the FVP_Base_RevC-2xAEMvA platform model running in AArch32 Hyp mode (CONFIG64=0) into any other Memory but Strongly-Ordered? My environment is - FVP_Base_RevC-2xAEMvA booting SW stack from bullet point below - SW stack from Yocto, 'meta-arm'. I use 'fvp-base-arm32' that builds bl1, bl2, bl32, bl33, Linux kernel and rootfs. The only component that works there at PL2 HYP mode is u-boot (bl33). Whichever attributes I assign there Normal Memory with Inner or Outer Cacheability, Write-Through, or Write-Back, or Non-cacheable I always end up with Strongly-Ordered. To me it looks like it doesn't read the MAIR correctly and/or ignores the Cachability in HCTR. I inspected the MMU code thoroughly there, compared with the other codes for MMU, from trusted-firmware-a, xen, and Linux kernel and it seems u-boot does it correct. U-boot sets there identity-mapping for all 4GB with 0GB through 2GB Strongly-Ordered, 3G - 4G Normal Memory, Cachable Write-Back Write-Allocate, Non-Shareable and the last 1GB also Strongly-Ordered. Here is a brief execution steps it goes through: #1 Sets up the 2M-block at the 2nd level table with attributes. - sample block descriptor for translating from 0x8000_0000 virt to phys: 0x8000044d - bits[1:0] = 0b01 -> valid descriptor, descriptor type: block - bits[4:2] = 0b011 -> AttrIndx[2:0] points to MAIR0[3] . MAIR0[3] is 0xff - bits[5] = 0b0 - Non-secure - bits[7:6] = 0b01 - Access Permission: Read/write - bits[9:8] = 0b00 -> Shareability: non-shareable #2 Sets up 1st level table descriptor pointing to the descriptor shown above. It sets bits[1:0] to 0b11 meaning it is a table descriptor and valid. #3 Set control registers as follows HTCR is: 0x80000500 so - bits[9:8] = 0b01 -> Inner Cacheability to Normal memory, Outer Write-Back Write-Allocate Cacheable - bits[11:10] = 0b01 -> Outer Cacheability to Normal memory, Outer Write-Back Write-Allocate Cacheable - bits[13:12] = 0b00 -> Non-shareable HTTBR is: 0x00000000feff4000 -> points to 1st lavel table set in #2 HMAIR0 is: 0xffeeaa00 -> as shown above AttrIndx[2:0] points to MAIR0 and the four nibble being 0xff. 0xff is Normal memory, Inner Write-Back Cacheablea, Non-transientb HMAIR1 is: 0x00000000 - I set it to zero there as not used. #4 Finally it sets the M and C bits in HSCTLR registers Inspecting the page tables with amrds the region 3GB through 4GB that should be Normal and Cachable is Strongly-Ordered - 0x80000000 | L2 Block | NP:0x0000000080000000 | XN=0, PXN=0, Contiguous=0, nG=0, AF=1, SH=0x0, AP=0x1, AttrIndx=0x3 - H:0x80000000-0xFEFFFFFF | NP:0x80000000-0xFEFFFFFF | Strongly-ordered | NA | False | True | True Least not last are the parameters I pass to the model: FVP_Base_RevC-2xAEMvA --parameter bp.ve_sysregs.exit_on_shutdown=1 --parameter bp.virtio_net.enabled=1 --parameter bp.virtio_net.hostbridge.userNetworking=1 --parameter bp.virtio_net.hostbridge.userNetPorts=8022=22 --parameter cache_state_modelled=0 --parameter bp.secureflashloader.fname=/home/ubuntu/yocto/poky/arm32-aem-build/tmp/deploy/images/fvp-base-arm32/bl1-fvp.bin --parameter bp.flashloader0.fname=/home/ubuntu/yocto/poky/arm32-aem-build/tmp/deploy/images/fvp-base-arm32/fip-fvp.bin --parameter bp.virtioblockdevice.image_path=/home/ubuntu/yocto/poky/arm32-aem-build/tmp/deploy/images/fvp-base-arm32/core-image-minimal-fvp-base-arm32-20250630100348.rootfs.wic --parameter cluster0.has_arm_v8-4=1 --parameter cluster1.has_arm_v8-4=1 --parameter cluster0.cpu0.CONFIG64=0 --parameter cluster0.cpu1.CONFIG64=0 --parameter cluster0.cpu2.CONFIG64=0 --parameter cluster0.cpu3.CONFIG64=0 --parameter cluster1.cpu0.CONFIG64=0 --parameter cluster1.cpu1.CONFIG64=0 --parameter cluster1.cpu2.CONFIG64=0 --parameter cluster1.cpu3.CONFIG64=0 --data cluster0.cpu0=/home/ubuntu/yocto/poky/arm32-aem-build/tmp/deploy/images/fvp-base-arm32/zImage@0x80080000 --data cluster0.cpu0=/home/ubuntu/yocto/poky/arm32-aem-build/tmp/deploy/images/fvp-base-arm32/fvp-base-revc.dtb@0x8fc00000 --parameter 'bp.terminal_0.terminal_command=tmux new-window -n "%title" "telnet localhost %port"' --parameter bp.terminal_1.start_telnet=0 --parameter bp.terminal_2.start_telnet=0 --parameter bp.terminal_3.start_telnet=0 --iris-server --iris-port 7102 --iris-allow-remote And an interrupted (not full for longevity) console log: NOTICE: Booting Trusted Firmware NOTICE: BL1: v2.8(debug):dd37aa5be-dirty NOTICE: BL1: Built : 20:04:50, Aug 4 2025 NOTICE: BL1: Booting BL2 NOTICE: BL2: v2.8(debug):dd37aa5be-dirty NOTICE: BL2: Built : 20:04:50, Aug 4 2025 NOTICE: BL1: Booting BL32 WARNING: FCONF: Invalid config id 26 INFO: SP_MIN FCONF: HW_CONFIG address = 0x7f00000 INFO: FCONF: Reading HW_CONFIG firmware configuration file from: 0x7f00000 INFO: FCONF: Reading firmware configuration information for: cpu_timer INFO: FCONF: Reading firmware configuration information for: uart_config INFO: FCONF: Reading firmware configuration information for: topology INFO: FCONF: Reading firmware configuration information for: gicv3_config NOTICE: SP_MIN: v2.8(debug):dd37aa5be-dirty NOTICE: SP_MIN: Built : 20:04:50, Aug 4 2025 U-Boot 2022.04 (Aug 06 2025 - 16:41:21 +0000) vexpress_aemv8a fvp aarch32 DRAM: 2 GiB WARNING: Caches not enabled Core: 2 devices, 2 uclasses Flash: 64 MiB MMC: Loading Environment from nowhere... OK In: serial_pl01x Out: serial_pl01x Err: serial_pl01x Net: SMC91111-0 Error: SMC91111-0 address not set. Hit any key to stop autoboot: 0 fvp32# dcache on fvp32# run bootcmd OTE: Dereference aliases by omitting the leading '/', e.g. fdt print ethernet0. Kernel image @ 0x80080000 [ 0x000000 - 0x687970 ] ## Flattened Device Tree blob at 8fc00000 Booting using the fdt blob at 0x8fc00000 Loading Device Tree to feb8b000, end feb90fff ... OK Starting kernel ... Booting Linux on physical CPU 0x0 Linux version 6.1.57-yocto-standard (oe-user@oe-host) (arm-poky-linux-gnueabi-gcc (GCC) 12.3.0, GNU ld (GNU Binutils) 2.40.0.20230703) #1 SMP PREEMPT Wed Oct 11 23:03:27 UTC 2023 CPU: ARMv7 Processor [410fd0f0] revision 0 (ARMv7), cr=10c5387d CPU: div instructions available: patching division code CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache OF: fdt: Machine model: FVP Base RevC earlycon: pl11 at MMIO 0x1c090000 (options '') amba 1c1f0000.clcd: deferred probe pending Poky (Yocto Project Reference Distro) 4.2.4 fvp-base-arm32 /dev/ttyAMA0 fvp-base-arm32 login: root root@fvp-base-arm32:~# random: crng init done random: 1 urandom warning(s) missed due to ratelimiting root@fvp-base-arm32:~# Is there a chance FVP_Base_RevC-2xAEMvA doesn't support the 1-stage MMU translation for anything else but Strongly-Ordered? Thanks, Marek

6 months, 2 weeks

2
1
0 0

Trusted Firmware-A LTS v2.12.6 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.12.6 is now available. This release contains the following patches: 27fa107db fix(cpus): put back the global declaration for erratum #3701747 [1] 621560d74 fix(cpus): check minor revision before applying runtime errata [2] 44fc77fef fix(cpus): workaround for Cortex-X3 erratum 3692984 [3] cafd1afdc fix(cpus): workaround for Cortex-X3 erratum 3827463 [4] e9bc0b98b fix(cpus): workaround for Cortex-X3 erratum 3213672 [5] 76a1cce97 docs(security): security advisory for CVE-2024-5660 [6] e90ce7577 docs(security): security advisory for CVE-2024-7881 [7] 4b559e72c fix(cpus): workaround for Cortex-X2 erratum 1901946 [8] 7054fa4e7 fix(cpus): workaround for Cortex-X2 erratum 1916945 [9] 7f0fc6bd0 fix(cpus): workaround for Cortex-X2 erratum 1917258 [10] 47ddedb4d fix(cpus): workaround for Cortex-X2 erratum 1927200 [11] 851c5bf1a fix(cpus): workaround for Cortex-X2 erratum 1934260 [12] 66f25a832 fix(cpus): workaround for Cortex-X2 erratum 2136059 [13] 7430412db fix(cpus): workaround for Cortex-X2 erratum 2267065 [14] d1ed44d64 fix(cpus): workaround for Cortex-X2 erratum 2291219 [15] 885b1291a fix(cpus): organize Cortex-X2 errata entries [16] 7fc7f929c fix(cpus): workaround for Cortex-X4 erratum 3133195 [17] ace292ef2 fix(cpus): workaround for Cortex-X4 erratum 3887999 [18] [1] https://review.trustedfirmware.org/q/Ic7a5a13ae89b0b86ccbea56fecfe12bef57a9… [2] https://review.trustedfirmware.org/q/I46b2ba8b524a073e02b4b5de641ae97795bc1… [3] https://review.trustedfirmware.org/q/I054b47d33fd1ff7bde3ae12e8ee3d99e92039… [4] https://review.trustedfirmware.org/q/I1d4a2b9641400d8b9061f7cb32a8312c39956… [5] https://review.trustedfirmware.org/q/Ia1c03217f4e1816b4e8754a090cf5bc17546b… [6] https://review.trustedfirmware.org/q/I0d0428061f60b6fe83d03362b27b960f6ddcc… [7] https://review.trustedfirmware.org/q/Ide976bc8754dc94d23e76001aaecf52556e70… [8] https://review.trustedfirmware.org/q/I5a65db60f06982191994db49815419c4d7250… [9] https://review.trustedfirmware.org/q/If810b1d0a07c43b3e1aa70d2ec88c1dcfa6f7… [10] https://review.trustedfirmware.org/q/Ic18a5179856f861701f09b2556906a6722db8… [11] https://review.trustedfirmware.org/q/I8d9038df1907888b3c5b2520d06bc150665e7… [12] https://review.trustedfirmware.org/q/I180d38fee27175dc8ac5fa6726e5b71c33402… [13] https://review.trustedfirmware.org/q/I156467537c3f235b50fc8aa19a969f2798bd8… [14] https://review.trustedfirmware.org/q/I540e113f209ef11ec7103d4ef4e48ffb52416… [15] https://review.trustedfirmware.org/q/I43af57961feba3a1c001d09ad804740b996f1… [16] https://review.trustedfirmware.org/q/Ic01517d58d3ca1b2d39be5282b0058c94fa5d… [17] https://review.trustedfirmware.org/q/Id44daf950124e7c2d46cb5d6d6a1083d06fad… [18] https://review.trustedfirmware.org/q/I851746b7b430eac85184c8d402d1aa5bb3c94… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.6/change-log.html Thanks, TF-A LTS team

6 months, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.8.36 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.36 is now available. This release contains the following patches: c1555a4b8 docs(security): security advisory for CVE-2024-5660 [1] 624fc1ef2 fix(cpus): workaround for Cortex-X3 erratum 3692984 [2] 016cec654 fix(cpus): workaround for Cortex-X3 erratum 3827463 [3] aecd38e2d fix(cpus): workaround for Cortex-X3 erratum 3213672 [4] 4e7482dec docs(security): security advisory for CVE-2024-7881 [5] 697b97b1c fix(cpus): check minor revision before applying runtime errata [6] e98240355 fix(cpus): workaround for Cortex-X2 erratum 1901946 [7] 09561550a fix(cpus): workaround for Cortex-X2 erratum 1916945 [8] 030aeeb41 fix(cpus): workaround for Cortex-X2 erratum 1917258 [9] 7285f895b fix(cpus): workaround for Cortex-X2 erratum 1927200 [10] d7e3d8d03 fix(cpus): workaround for Cortex-X2 erratum 1934260 [11] 7b27723e3 fix(cpus): workaround for Cortex-X2 erratum 2136059 [12] 9ba7b304f fix(cpus): workaround for Cortex-X2 erratum 2267065 [13] c7de7e847 feat(cpus): add sysreg_bit_toggle [14] c1e2ccbe9 fix(cpus): workaround for Cortex-X2 erratum 2291219 [15] eff911ae6 fix(cpus): organize Cortex-X2 errata entries [16] 23c71d54d fix(cpus): workaround for Cortex-X4 erratum 3133195 [17] c55f75f33 fix(cpus): workaround for Cortex-X4 erratum 3887999 [18] d8f885dda chore(deps-dev): Bump commitizen [19] 083ec60a7 chore(deps-dev): Bump click from 8.1.7 to 8.1.8 [20] [1] https://review.trustedfirmware.org/q/I0d0428061f60b6fe83d03362b27b960f6ddcc… [2] https://review.trustedfirmware.org/q/I054b47d33fd1ff7bde3ae12e8ee3d99e92039… [3] https://review.trustedfirmware.org/q/I1d4a2b9641400d8b9061f7cb32a8312c39956… [4] https://review.trustedfirmware.org/q/Ia1c03217f4e1816b4e8754a090cf5bc17546b… [5] https://review.trustedfirmware.org/q/Ide976bc8754dc94d23e76001aaecf52556e70… [6] https://review.trustedfirmware.org/q/I46b2ba8b524a073e02b4b5de641ae97795bc1… [7] https://review.trustedfirmware.org/q/I5a65db60f06982191994db49815419c4d7250… [8] https://review.trustedfirmware.org/q/If810b1d0a07c43b3e1aa70d2ec88c1dcfa6f7… [9] https://review.trustedfirmware.org/q/Ic18a5179856f861701f09b2556906a6722db8… [10] https://review.trustedfirmware.org/q/I8d9038df1907888b3c5b2520d06bc150665e7… [11] https://review.trustedfirmware.org/q/I180d38fee27175dc8ac5fa6726e5b71c33402… [12] https://review.trustedfirmware.org/q/I156467537c3f235b50fc8aa19a969f2798bd8… [13] https://review.trustedfirmware.org/q/I540e113f209ef11ec7103d4ef4e48ffb52416… [14] https://review.trustedfirmware.org/q/I058bad58f5949b2d5fe058101410e33b6be1b… [15] https://review.trustedfirmware.org/q/I43af57961feba3a1c001d09ad804740b996f1… [16] https://review.trustedfirmware.org/q/Ic01517d58d3ca1b2d39be5282b0058c94fa5d… [17] https://review.trustedfirmware.org/q/Id44daf950124e7c2d46cb5d6d6a1083d06fad… [18] https://review.trustedfirmware.org/q/I851746b7b430eac85184c8d402d1aa5bb3c94… [19] https://review.trustedfirmware.org/q/Id7a94e085b8cab73efc935e5c71e7b43f6149… [20] https://review.trustedfirmware.org/q/I0e616fa4e45fc803522f1f5fe108fa75e9198… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.36/change-log.html Thanks, TF-A LTS team

6 months, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.10.21 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.21 is now available. This release contains the following patches: a8a944318 build(deps-dev): Bump pip-tools from 6.13.0 to 6.14.0 [1] c4e1d4aa4 build(deps-dev): Bump @commitlint/cli from 19.0.0 to 19.8.1 [2] 8fd01f672 build(deps-dev): Bump @commitlint/cz-commitlint from 19.0.0 to 19.8.1 [3] 11ac166ca build(deps-dev): Bump @commitlint/config-conventional [4] f13bcf9b1 feat(cpus): add sysreg_bit_toggle [5] 0c79e2503 fix(cpus): workaround for Cortex-X2 erratum 1901946 [6] 8c1313b57 fix(cpus): workaround for Cortex-X2 erratum 1916945 [7] 79048ea18 fix(cpus): workaround for Cortex-X2 erratum 1917258 [8] 7f237698e fix(cpus): workaround for Cortex-X2 erratum 1927200 [9] 10388d941 fix(cpus): workaround for Cortex-X2 erratum 1934260 [10] d1320024f fix(cpus): workaround for Cortex-X2 erratum 2136059 [11] 158b26749 fix(cpus): workaround for Cortex-X2 erratum 2267065 [12] 211f2681b fix(cpus): workaround for Cortex-X2 erratum 2291219 [13] 23da5c284 fix(cpus): organize Cortex-X2 errata entries [14] 45e66bf45 fix(cpus): workaround for Cortex-X4 erratum 3133195 [15] dbef7f7f4 fix(cpus): workaround for Cortex-X4 erratum 3887999 [16] d30f0ff2c docs(security): update Advisory TFV-6 [17] [1] https://review.trustedfirmware.org/q/I5b529430588b599402553aed2b4929885053c… [2] https://review.trustedfirmware.org/q/I3c0f687e72c1bd02ef297387f5d2155576e31… [3] https://review.trustedfirmware.org/q/I4baeb1055066d580af5df08ebb4f0f96d6fc2… [4] https://review.trustedfirmware.org/q/Ic27f9c7211ef6535702a9475aeed57c9f2864… [5] https://review.trustedfirmware.org/q/I058bad58f5949b2d5fe058101410e33b6be1b… [6] https://review.trustedfirmware.org/q/I5a65db60f06982191994db49815419c4d7250… [7] https://review.trustedfirmware.org/q/If810b1d0a07c43b3e1aa70d2ec88c1dcfa6f7… [8] https://review.trustedfirmware.org/q/Ic18a5179856f861701f09b2556906a6722db8… [9] https://review.trustedfirmware.org/q/I8d9038df1907888b3c5b2520d06bc150665e7… [10] https://review.trustedfirmware.org/q/I180d38fee27175dc8ac5fa6726e5b71c33402… [11] https://review.trustedfirmware.org/q/I156467537c3f235b50fc8aa19a969f2798bd8… [12] https://review.trustedfirmware.org/q/I540e113f209ef11ec7103d4ef4e48ffb52416… [13] https://review.trustedfirmware.org/q/I43af57961feba3a1c001d09ad804740b996f1… [14] https://review.trustedfirmware.org/q/Ic01517d58d3ca1b2d39be5282b0058c94fa5d… [15] https://review.trustedfirmware.org/q/Id44daf950124e7c2d46cb5d6d6a1083d06fad… [16] https://review.trustedfirmware.org/q/I851746b7b430eac85184c8d402d1aa5bb3c94… [17] https://review.trustedfirmware.org/q/Icb3d039c8949fd6036c729a845646170710ba… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.21/change-log.html Thanks, TF-A LTS team

6 months, 2 weeks

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 487973: Memory - corruptions (ARRAY_VS_SINGLETON) _____________________________________________________________________________________________ *** CID 487973: Memory - corruptions (ARRAY_VS_SINGLETON) /plat/xilinx/versal_net/bl31_versal_net_setup.c: 167 in bl31_early_platform_setup2() 161 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, 162 tfa_handoff_addr); 163 if (xbl_ret == XBL_HANDOFF_SUCCESS) { 164 goto success; 165 } 166 #if DEBUG >>> CID 487973: Memory - corruptions (ARRAY_VS_SINGLETON) >>> Passing "&boot_mode" to function "get_boot_mode" which uses it as an array. This might corrupt or misinterpret adjacent memory locations. 167 get_boot_mode(&boot_mode); 168 if ((xbl_ret != XBL_HANDOFF_SUCCESS) && (boot_mode == JTAG_MODE)) { 169 bl31_set_default_config(); 170 goto success; 171 } 172 #endif ** CID 487972: Memory - corruptions (OVERRUN) _____________________________________________________________________________________________ *** CID 487972: Memory - corruptions (OVERRUN) /plat/xilinx/versal_net/bl31_versal_net_setup.c: 167 in bl31_early_platform_setup2() 161 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, 162 tfa_handoff_addr); 163 if (xbl_ret == XBL_HANDOFF_SUCCESS) { 164 goto success; 165 } 166 #if DEBUG >>> CID 487972: Memory - corruptions (OVERRUN) >>> Overrunning buffer pointed to by "&boot_mode" of 1 4-byte elements by passing it to a function which accesses it at element index 5 (byte offset 23). 167 get_boot_mode(&boot_mode); 168 if ((xbl_ret != XBL_HANDOFF_SUCCESS) && (boot_mode == JTAG_MODE)) { 169 bl31_set_default_config(); 170 goto success; 171 } 172 #endif ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

6 months, 3 weeks

1
0
0 0

Rusted Firmware-A is live!

by Olivier Deprez

Hi, Relaying an important announcement about the new Rusted Firmware-A project hosted on trustedfirmware.org: Today, the Trusted Firmware organization proudly unveils Rusted Firmware-A (RF-A) v0.1 \u2014 a ground breaking open-source prototype that reimagines Trusted Firmware-A (TF-A) through the adoption of the Rust programming language. Developed in close collaboration between Arm and Google, both Diamond members of the Trusted Firmware community, RF-A has been architected from the ground up for the latest Arm® A-class processors. With a security-first approach, RF-A delivers strong memory safety, enhanced reliability, and modern modularity. Unlike incremental updates, Rusted Firmware-A is a complete redesign \u2014 free from legacy constraints, built to leverage modern hardware, and designed to provide a robust, maintainable, and future-ready firmware foundation. This milestone reflects years of industry learnings, community insights, and deep collaboration between leading software and silicon providers. Press release - https://www.trustedfirmware.org/news/rf-a-press-release Technical blog - https://www.trustedfirmware.org/blog/rf-a-blog Linkedin post - https://www.linkedin.com/posts/trustedfirmware-org_rusted-firmware-a-rf-a-a… Regards, Olivier on behalf of Arm RF-A team.

6 months, 4 weeks

1
0
0 0

Trusted Firmware-A LTS v2.10.20 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.20 is now available. This release contains the following patches: 0f23418f7 docs(security): security advisory for CVE-2024-5660 [1] 2749de008 docs(security): security advisory for CVE-2024-7881 [2] dc0b5b922 fix(cpus): workaround for Cortex-X3 erratum 3692984 [3] fe66ffc80 fix(cpus): workaround for Cortex-X3 erratum 3827463 [4] bf658f6e6 fix(cpus): workaround for Cortex-X3 erratum 3213672 [5] dd846c6b4 fix(cpus): check minor revision before applying runtime errata [6] 588d93fe4 chore(deps): bump sphinxcontrib-svg2pdfconverter from 1.2.2 to 1.3.0 [7] a843ce313 chore(deps): bump commitizen [8] d7d698694 fix(cpus): put back the global declaration for erratum #3701747 [9] [1] https://review.trustedfirmware.org/q/I0d0428061f60b6fe83d03362b27b960f6ddcc… [2] https://review.trustedfirmware.org/q/Ide976bc8754dc94d23e76001aaecf52556e70… [3] https://review.trustedfirmware.org/q/I054b47d33fd1ff7bde3ae12e8ee3d99e92039… [4] https://review.trustedfirmware.org/q/I1d4a2b9641400d8b9061f7cb32a8312c39956… [5] https://review.trustedfirmware.org/q/Ia1c03217f4e1816b4e8754a090cf5bc17546b… [6] https://review.trustedfirmware.org/q/I46b2ba8b524a073e02b4b5de641ae97795bc1… [7] https://review.trustedfirmware.org/q/Ia884121a4eeaf8033ff251e509264c9c97299… [8] https://review.trustedfirmware.org/q/I0cd50a9d7df7dac842a781b5f05a507d6f79d… [9] https://review.trustedfirmware.org/q/Ic7a5a13ae89b0b86ccbea56fecfe12bef57a9… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.20/change-log.html Thanks, TF-A LTS team

7 months, 1 week

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 487601: Control flow issues (DEADCODE) /plat/mediatek/drivers/spm/mt8189/mt_spm_pmic_lp.c: 157 in set_vcore_lp_volt() _____________________________________________________________________________________________ *** CID 487601: Control flow issues (DEADCODE) /plat/mediatek/drivers/spm/mt8189/mt_spm_pmic_lp.c: 157 in set_vcore_lp_volt() 151 { 152 /* allow 0.35V ~ 0.75V */ 153 if (volt < VCORE_0_35V) 154 return; 155 if (volt > VCORE_0_75V) 156 return; >>> CID 487601: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "vcore_suspend_vol = volt;". 157 vcore_suspend_vol = volt; 158 } 159 160 uint32_t get_vcore_lp_volt(void) 161 { 162 return vcore_suspend_vol; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

7 months, 1 week

1
0
0 0

optee_ftpm + ms-tpm-20-ref support for RSA key sizes 3072 or 4096 causes a panic

by Dennis Kong

Dear community: I apologize in advance if this is the incorrect place to solicit for input on an issue I am having when enabling support of RSA key sizes > 2048. The environment is described below: TI AM642-EVM board Debian Bookworm running kernel 6.6.100, tpm_ftpm_tee.ko kernel module Uboot booting from sdcard UEFI partition and rootfs partition optee_os version 4.5.0 , 4.6.0, 4.7.0 (no difference in behaviour) optee_client version 4.5.0, 4.6.0, 4.7.0 (no difference in behaviour) optee_ftpm version 4.5.0 or 4.6.0, 4.7.0 (no difference in behaviour) ms-tpm-20-ref commit id 98b60a44aba79b15fcce1c0d1e46cf5918400f6a and e9fc7b89d865536c46deb63f9c7d0121a3ded49c Due to issues with RPMB, we decided to use REE_FS instead. Everything works correctly when I create RSA 2048 keys using tpm2-openssl and related tools: sudo tpm2_createprimary -C o -G rsa2048 -g sha256 -c primary.ctx, When I try rsa3072 or 4096, I get errors from the command line response saying invalid input parameters. I changed the ms-tpm-20-ref include file TpmProfile.h to set RSA_3072 and RSA_4096 macros both to (ALG_RSA && YES). After rebuilding and running, I now get an optee panic for ANY RSA key request INCLUDING rsa2048. I read suggestions to increase the MAX_COMMAND_SIZE/MAX_RESPONSE_SIZE on both the kernel driver tpm_ftpm_tee.ko and also optee_os/optee_ftpm, as well to increase relevant TA_STACK_SIZE and TA_HEAP_SIZE and TA_DATA_SIZE, but nothing seems to change the panic output: sudo tpm2_createprimary -C o -G rsa2048 -g sha256 -c primary.ctx============================================================ E/TC:? 0 E/TC:? 0 TA panicked with code 0xffff0007 E/LD: Status of TA bc50d971-d4c9-42c4-82cb-343fb7f37896 E/LD: arch: aarch64 E/LD: region 0: va 0x40005000 pa 0x9e8b0000 size 0x002000 flags rw-s (ldelf) E/LD: region 1: va 0x40007000 pa 0x9e8b2000 size 0x008000 flags r-xs (ldelf) E/LD: region 2: va 0x4000f000 pa 0x9e8ba000 size 0x001000 flags rw-s (ldelf) E/LD: region 3: va 0x40010000 pa 0x9e8bb000 size 0x004000 flags rw-s (ldelf) E/LD: region 4: va 0x40014000 pa 0x9e8bf000 size 0x001000 flags r--s E/LD: region 5: va 0x40015000 pa 0x9e934000 size 0x011000 flags rw-s (stack) E/LD: region 6: va 0x40026000 pa 0x8ebf0000 size 0x002000 flags rw-- (param) E/LD: region 7: va 0x4006e000 pa 0x9e8c0000 size 0x058000 flags r-xs [0] E/LD: region 8: va 0x400c6000 pa 0x9e918000 size 0x01c000 flags rw-s [0] E/LD: [0] bc50d971-d4c9-42c4-82cb-343fb7f37896 @ 0x4006e000 E/LD: Call stack: E/LD: 0x4006f394 E/LD: 0x40095edc E/LD: 0x4007b5a8 E/LD: 0x400985fc E/LD: 0x40098a70 E/LD: 0x4006fae0 E/LD: 0x400a5508 E/LD: 0x40098b9c D/TC:? 0 user_ta_enter:195 tee_user_ta_enter: TA panicked with code 0xffff0007 D/TC:? 0 release_ta_ctx:670 Releasing panicked TA ctx D/TC:? 0 tee_ta_invoke_command:798 Error: ffff3024 of 3 [ 218.944680] tpm tpm0: ftpm_tee_tpm_op_send: SUBMIT_COMMAND invoke error: 0xffff3024 [ 218.952379] tpm tpm0: tpm_try_transmit: send(): error -53212 D/TC:? 0 tee_ta_invoke_command:798 Error: ffff3024 of 3 [ 218.963359] tpm tpm0: ftpm_tee_tpm_op_send: SUBMIT_COMMAND invoke error: 0xffff3024 [ 218.974241] tpm tpm0: tpm_try_transmit: send(): error -53212 D/TC:? 0 tee_ta_invoke_command:798 Error: ffff3024 of 3 [ 218.985675] tpm tpm0: ftpm_tee_tpm_op_send: SUBMIT_COMMAND invoke error: 0xffff3024 [ 218.993366] tpm tpm0: tpm_try_transmit: send(): error -53212 [ 218.999044] tpm tpm0: tpm2_commit_space: error -14 ERROR:tcti:src/tss2-tcti/tcti-device.c:198:tcti_device_receive()D/TC:? 0 tee_ta_invoke_command:798 Error: ffff3024 of 3 Failed to get response size fd 3, got errno 14: Bad address E[ 219.015351] tpm tpm0: ftpm_tee_tpm_op_send: SUBMIT_COMMAND invoke error: 0xffff3024 RROR:esys:src/tss2-esys/api/Esys_CreatePrimary.c:404:Esys_Create[ 219.028348] tpm tpm0: tpm_try_transmit: send(): error -53212 Primary_Finish() Received a non-TPM Error ERROR:esys:src/tss2-esys/api/Esys_CreatePrimary.c:135:Esys_CreatePrimary() Esys Finish ErrorCode (0x000a000a) ERROR: Esys_CreatePrimary(0xA000A) - tcti:IO failure ERROR:esys:src/tss2-esys/esys_iutil.c:1145:iesys_check_sequence_async() Esys called in bad sequence. ERROR:esys:src/tss2-esys/api/Esys_FlushContext.c:66:Esys_FlushContext() Error in async function ErrorCode (0x00070007) ============================================================================= The last suggestion I saw was to change my dtb file to include a reserved memory region for optee shared memory and not use the default dynamic shared memory. The issue I have is kernel 6.6.100's tpm_ftpm_tee ignores the "memory-region" dts statement that references the optee_shm reserved memory at at 0xa4000000 in my case. Below is my snippet of the dts file. I heard there are patches in the kernel ftpm driver to support the reserved shared memory, but before I try the patches, can anyone opine whether this could cause the panic that I am seeing? Thanks in advance for anyone who can share any information optee_shm: optee-shm@a4000000 { compatible = "shared-dma-pool"; reg = <0x0 0xa4000000 0x0 0x01000000>; no-map; reusable; }; .... firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; memory-region = <&optee_shm>; }; } Dennis Kong, P.Eng. Staff Engineer Perle Systems Limited 60 Renfrew Drive, Markham, ON L3R 0E1 (905) 475-6070 ext. 2126

7 months, 1 week

1
0
0 0

Does spmd_group0_interrupt_handler_nwd() need to take into account handling of special INTIDs?

by YANG Jun

Hi there, Do spmd_group0_interrupt_handler_nwd() and spmd_handle_group0_intr_swd() need to take into account handling of special INTIDs? Like ehf_el3_interrupt_handler(): /* * Acknowledge interrupt. Proceed with handling only for valid interrupt * IDs. This situation may arise because of Interrupt Management * Framework identifying an EL3 interrupt, but before it's been * acknowledged here, the interrupt was either deasserted, or there was * a higher-priority interrupt of another type. */ intr_raw = plat_ic_acknowledge_interrupt(); intr = plat_ic_get_interrupt_id(intr_raw); if (intr == INTR_ID_UNAVAILABLE) return 0; Best Regards, Joe Yang

7 months, 1 week

3
3
0 0

Canceled event with note: TF-A Tech Forum @ Thu Aug 21, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling the TF-A tech forum session on Aug 21st as expecting low attendance in the summer vacation period and no topic planned on this day. Regards, Olivier. " TF-A Tech Forum Thursday Aug 21, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

7 months, 1 week

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu Aug 7, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling the TF-A tech forum for this week as no topic proposed. Regards, Olivier. " TF-A Tech Forum Thursday Aug 7, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

7 months, 1 week

1
0
0 0

Re: Does spmd_group0_interrupt_handler_nwd() need to take into account handling of special INTIDs?

by Yang Joe

Hi Madhukar, Yes, I have encountered a spurious ID(1023) issue once. Best Regards, Joe Yang

7 months, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.8.35 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.35 is now available. This release contains the following patches: 0aaca5da3 fix(cpus): workaround for Cortex-A710 erratum 1901946 [1] b83bf0ad1 fix(cpus): workaround for Cortex-A710 erratum 1916945 [2] e26d08b8c fix(cpus): workaround for Cortex-A710 erratum 1917258 [3] ac23c6eba fix(cpus): workaround for Cortex-A710 erratum 1927200 [4] 777b7063f fix(zynqmp): workaround issue around cntpct_el0 [5] 8a48b31f3 fix(imx8mp): remove ERR050463 VPUMIX workaround [6] [1] https://review.trustedfirmware.org/q/I703f0e6ee122e44a9bc284d90f1465039e3b4… [2] https://review.trustedfirmware.org/q/I54793492c527928d7f266165a31b8613de838… [3] https://review.trustedfirmware.org/q/I1fae91a5e3a8ecea255f0f0a481bfd6196a7d… [4] https://review.trustedfirmware.org/q/I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d… [5] https://review.trustedfirmware.org/q/Ie43096bb33bb0e02c8cac07f965610b4565e1… [6] https://review.trustedfirmware.org/q/I263531c6eef44a679002cd048e71fb50c63d9… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.35/change-log.html Thanks, TF-A LTS team

7 months, 3 weeks

1
0
0 0

Trusted Firmware-A LTS v2.12.5 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.12.5 is now available. This release contains the following patches: df4665589 fix(zynqmp): workaround issue around cntpct_el0 [1] f005662e6 fix(imx8mp): remove ERR050463 VPUMIX workaround [2] da60f9c02 fix(cpus): workaround for Cortex-A710 erratum 1901946 [3] e3f2ee2ca fix(cpus): workaround for Cortex-A710 erratum 1916945 [4] bdb9f85e1 fix(cpus): workaround for Cortex-A710 erratum 1917258 [5] 4aa3e4c6c fix(cpus): workaround for Cortex-A710 erratum 1927200 [6] [1] https://review.trustedfirmware.org/q/Ie43096bb33bb0e02c8cac07f965610b4565e1… [2] https://review.trustedfirmware.org/q/I263531c6eef44a679002cd048e71fb50c63d9… [3] https://review.trustedfirmware.org/q/I703f0e6ee122e44a9bc284d90f1465039e3b4… [4] https://review.trustedfirmware.org/q/I54793492c527928d7f266165a31b8613de838… [5] https://review.trustedfirmware.org/q/I1fae91a5e3a8ecea255f0f0a481bfd6196a7d… [6] https://review.trustedfirmware.org/q/I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.5/change-log.html Thanks, TF-A LTS team

7 months, 3 weeks

1
0
0 0

Trusted Firmware-A LTS v2.10.19 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.19 is now available. This release contains the following patches: 5a70c5221 fix(cpus): workaround for Cortex-A710 erratum 1901946 [1] d16c477c7 fix(cpus): workaround for Cortex-A710 erratum 1916945 [2] 2a571f7f2 fix(cpus): workaround for Cortex-A710 erratum 1917258 [3] bc44ad427 fix(cpus): workaround for Cortex-A710 erratum 1927200 [4] b1926f4c0 fix(zynqmp): workaround issue around cntpct_el0 [5] b200b62c2 fix(imx8mp): remove ERR050463 VPUMIX workaround [6] [1] https://review.trustedfirmware.org/q/I703f0e6ee122e44a9bc284d90f1465039e3b4… [2] https://review.trustedfirmware.org/q/I54793492c527928d7f266165a31b8613de838… [3] https://review.trustedfirmware.org/q/I1fae91a5e3a8ecea255f0f0a481bfd6196a7d… [4] https://review.trustedfirmware.org/q/I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d… [5] https://review.trustedfirmware.org/q/Ie43096bb33bb0e02c8cac07f965610b4565e1… [6] https://review.trustedfirmware.org/q/I263531c6eef44a679002cd048e71fb50c63d9… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.19/change-log.html Thanks, TF-A LTS team

7 months, 3 weeks

1
0
0 0

Contributing to Trusted Firmware Armv7-A and Armv8-A

by Waqas Mazhar

Hi all, Hope you are well. I have recently joined this mailing list and am quite keen to contribute to this project but don't know where to start. Currently, I am going through Trusted Firmware A Documentation <https://trustedfirmware-a.readthedocs.io/en/latest/index.html> document and Gerrit code reviews <https://review.trustedfirmware.org/q/status:open+-is:wip> to develop some initial understanding and familiarity about the project. As a first step, I am trying to understand areas where I can contribute. Is there any simple issue for me to pick? I am happy to volunteer. Looking forward to hearing from you, Waqas

8 months

1
0
0 0

TF-A Tech Forum on July 10th 2025 - SMC Fuzzing

by Olivier Deprez

Hi, In the TF-A Tech Forum on July 10th 2025 Mark Dykes from Arm TF-A team will present the topic of SMC Fuzzing with the agenda: Overview of the TF-A fuzzer and its basic implementation in practice. Regards, Olivier. TF-A Tech Forum Thursday Jul 10, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org

8 months, 1 week

2
1
0 0

MISRA Compliance: Request to consider filing deviation for 11.1 (Function Pointer Conversions) in TF-A

by Dhruva Gole

Hello, Background & Justification: MISRA C:2012 Rule 11.1 forbids the conversion from a function pointer to any other type. However, in the context of TF-A, we encounter scenarios where this conversion is necessary and performed with full knowledge of the target architecture and toolchain behavior. A prominent example is in low-level platform code, such as transferring control between bootloader stages or passing function entry points for CPU/core bring-up, where the conversion is unavoidable and well-understood. One such example is the K3 PSCI driver [1] where we pass the k3_sec_entrypoint which is of type uintptr_t, to the ti_sci_proc_set_boot_cfg function where the parameter is of type uint64_t. Another place that triggered the discussions behind this MISRA C issue was the TI AM62L PSCI driver [2] that needs a 16b aligned function pointer. We don't have to go into specific case by case discussion of solving these issues, but just wanted to share example use cases of function pointer conversion. Request: I propose we formally document a project-wide MISRA C:2012 Rule 11.1 deviation, reflecting current and future usage throughout the TF-A codebase. This deviation allows us to balance MISRA objectives with the practical and architectural necessities of TF-A development. Rationale: * Conversions between function pointers and other types are essential in several parts of the TF-A codebase, not limited to one module or file. * Platform-specific code (e.g., power management, bootloader hand-offs) relies on this pattern for correct operation. References: [1] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/ti/k3… [2] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/ti/k3… -- Best regards, Dhruva Gole Texas Instruments Incorporated

8 months, 1 week

2
1
0 0

Context uninitialized assertion failure in xlat_tables_core for ZynqMP

by Michał Kruszewski

Hello, I want to boot Linux on ZynqMP (XCZU15EG). I follow the standard procedure. I have generated FSBL using Vitis. I have compiled bl31 (tag: xilinx-v2025.1). I have a standard boot.bif configuration looking as follows: the_ROM_image: { [bootloader] fsbl.elf [pmufw_image] pmufw.elf [destination_cpu = a53-0, exception_level= el-3, trustzone] bl31.bin [destination_cpu = a53-0, exception_level= el-2, load = 0x10000000] images/u-boot.bin } However, the bl31 reports the following error during the handoff to u-boot: ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:788 BACKTRACE: START: assert 0: F_FUNCTION: 0x2880 1: F_FUNCTION: 0x4cac 2: F_FUNCTION: 0x2628 3: F_FUNCTION: 0x36e0 4: F_FUNCTION: 0x108 5: F_FUNCTION: 0xfffcd8e8 BACKTRACE: END: assert This is an assertion for context being uninitialized in the mmap_add_region_ctx function. /* Static regions must be added before initializing the xlat tables. */ assert(!ctx->initialized); Does anyone have any idea what might be wrong? Best regards, Michał Kruszewski Sent with [Proton Mail](https://proton.me/mail/home) secure email.

8 months, 1 week

2
2
0 0

Canceled event with note: TF-A Tech Forum @ Thu Jul 24, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling the TF-A tech forum on Jul 24th , as no topic planned. Regards, Olivier." TF-A Tech Forum Thursday Jul 24, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

8 months, 2 weeks

1
0
0 0

TF-A Tech Forum on June 26th 2025 - Building Modern Industrial SoC Support in Arm Trusted Firmware

by Olivier Deprez

Hi, In the TF-A Tech forum on June 26th 2025 Dhruva Gole from Texas Instruments will present: Building Modern Industrial SoC Support in Arm Trusted Firmware Pragmatic Approaches to Power and Clock Management Regards, Olivier. TF-A Tech Forum Thursday Jun 26, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org

8 months, 3 weeks

2
2
0 0

Trusted Firmware-A LTS v2.12.4 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.12.4 is now available. This release contains the following patches: e21418b78 feat(errata): implement workaround for DSU-120 erratum 2900952 [1] 648b4f34f fix(cpus): remove accidental alto cpu addition [2] 68453765e feat(cpus): update cpu_check_csv2 check [3] [1] https://review.trustedfirmware.org/q/I87aa440ab5c35121aff703032f5cf7a62d0b0… [2] https://review.trustedfirmware.org/q/I04cb5394a8caf32a69775e6236cb9c09aadf7… [3] https://review.trustedfirmware.org/q/I8473047ed4ad759b7b506161a76774ac21555… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.4/change-log.html Thanks, TF-A LTS team

8 months, 4 weeks

1
0
0 0

Trusted Firmware-A LTS v2.10.18 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.10.18 is now available. This release contains the following patches: 7323c2d9d feat(errata): implement workaround for DSU-120 erratum 2900952 [1] 39e7f4a7c feat(cpus): update cpu_check_csv2 check [2] [1] https://review.trustedfirmware.org/q/I87aa440ab5c35121aff703032f5cf7a62d0b0… [2] https://review.trustedfirmware.org/q/I8473047ed4ad759b7b506161a76774ac21555… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.18/change-log.html Thanks, TF-A LTS team

8 months, 4 weeks

1
0
0 0

Trusted Firmware-A LTS v2.8.34 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.34 is now available. This release contains the following patches: 3a299d0bf feat(errata): implement workaround for DSU-120 erratum 2900952 [1] ae330d547 feat(cpus): update cpu_check_csv2 check [2] [1] https://review.trustedfirmware.org/q/I87aa440ab5c35121aff703032f5cf7a62d0b0… [2] https://review.trustedfirmware.org/q/I8473047ed4ad759b7b506161a76774ac21555… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.34/change-log.html Thanks, TF-A LTS team

8 months, 4 weeks

1
0
0 0

TF-A - sError Queries

by Jaiprakash Singh

Hi, I have below queries regarding nested sError handling in TF-A, please help. 1. While handling exceptions in EL3, sError is almost unmask most of the time. Any specific reason to keep sError unmasked? For example, while handing nested sError, we can keep sError masked in serror_sp_elx. So that no further sError comes to EL3. And unmask sError when returning to lower ELs. Do you think this will create any problem in the system? 1. In system, sError can happen at any time. At EL3, we have nested sError handling in serror_sp_elx. Do you think we should have similar nested sError handling in serror_sp_el0? If not, what is the reason? 1. Double fault will always lead to unhandled exception. * Can someone help define double fault scenario? * What is the purpose of this patch - https://github.com/ARM-software/arm-trusted-firmware/commit/c72200357aed49f…<https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_ARM-2Dsoftw…> Is purpose only to save esr_el3 register? Thanks Regards, Jaiprakash IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

8 months, 4 weeks

2
1
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 5 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 5 of 5 defect(s) ** CID 472149: Integer handling issues (NEGATIVE_RETURNS) _____________________________________________________________________________________________ *** CID 472149: Integer handling issues (NEGATIVE_RETURNS) /lib/psci/psci_main.c: 300 in psci_affinity_info() 294 * - the cluster was removed from coherency as part of the CPU shutdown 295 * 296 * In this case the cache maintenace that was performed as part of the 297 * target CPUs shutdown was not seen by the current CPU's cluster. And 298 * so the cache may contain stale data for the target CPU. 299 */ >>> CID 472149: Integer handling issues (NEGATIVE_RETURNS) >>> "target_idx" is passed to a parameter that cannot be negative. 300 flush_cpu_data_by_index(target_idx, 301 psci_svc_cpu_data.aff_info_state); 302 303 return psci_get_aff_info_state_by_idx(target_idx); 304 } 305 ** CID 472148: Memory - corruptions (OVERRUN) _____________________________________________________________________________________________ *** CID 472148: Memory - corruptions (OVERRUN) /lib/psci/psci_main.c: 39 in psci_cpu_on() 33 34 /* Validate the target CPU */ 35 if (!is_valid_mpidr(target_cpu)) { 36 return PSCI_E_INVALID_PARAMS; 37 } 38 >>> CID 472148: Memory - corruptions (OVERRUN) >>> Overrunning callee's array of size 2 by passing argument "target_idx" (which evaluates to 4294967295) in call to "_cpu_data_by_index". 39 ep = get_cpu_data_by_index(target_idx, warmboot_ep_info); 40 /* Validate the lower EL entry point and put it in the entry_point_info */ 41 rc = psci_validate_entry_point(ep, entrypoint, context_id); 42 if (rc != PSCI_E_SUCCESS) { 43 return rc; 44 } ** CID 472147: (OVERRUN) _____________________________________________________________________________________________ *** CID 472147: (OVERRUN) /lib/psci/psci_main.c: 300 in psci_affinity_info() 294 * - the cluster was removed from coherency as part of the CPU shutdown 295 * 296 * In this case the cache maintenace that was performed as part of the 297 * target CPUs shutdown was not seen by the current CPU's cluster. And 298 * so the cache may contain stale data for the target CPU. 299 */ >>> CID 472147: (OVERRUN) >>> Overrunning callee's array of size 2 by passing argument "target_idx" (which evaluates to 4294967295) in call to "_cpu_data_by_index". 300 flush_cpu_data_by_index(target_idx, 301 psci_svc_cpu_data.aff_info_state); 302 303 return psci_get_aff_info_state_by_idx(target_idx); 304 } 305 /lib/psci/psci_main.c: 303 in psci_affinity_info() 297 * target CPUs shutdown was not seen by the current CPU's cluster. And 298 * so the cache may contain stale data for the target CPU. 299 */ 300 flush_cpu_data_by_index(target_idx, 301 psci_svc_cpu_data.aff_info_state); 302 >>> CID 472147: (OVERRUN) >>> Overrunning callee's array of size 2 by passing argument "target_idx" (which evaluates to 4294967295) in call to "psci_get_aff_info_state_by_idx". 303 return psci_get_aff_info_state_by_idx(target_idx); 304 } 305 306 int psci_migrate(u_register_t target_cpu) 307 { 308 int rc; ** CID 472146: Memory - corruptions (OVERRUN) _____________________________________________________________________________________________ *** CID 472146: Memory - corruptions (OVERRUN) /lib/el3_runtime/aarch64/context_debug.c: 107 in report_allocated_memory() 101 if (is_ctx_pauth_supported()) { 102 PRINT_SINGLE_MEM_USAGE_SEP_BLOCK(); 103 } 104 105 PRINT_MEM_USAGE_SEPARATOR(); 106 >>> CID 472146: Memory - corruptions (OVERRUN) >>> Overrunning callee's array of size 2 by passing argument "i" (which evaluates to 7) in call to "cm_get_context_by_index". 107 cpu_context_t *ctx = (cpu_context_t *)cm_get_context_by_index(i, 108 security_state_idx); 109 core_total = sizeof(*ctx); 110 el3_size = sizeof(ctx->el3state_ctx); 111 gp_size = sizeof(ctx->gpregs_ctx); 112 size_other = core_total - (el3_size + gp_size); ** CID 472145: Integer handling issues (NEGATIVE_RETURNS) _____________________________________________________________________________________________ *** CID 472145: Integer handling issues (NEGATIVE_RETURNS) /lib/psci/psci_main.c: 39 in psci_cpu_on() 33 34 /* Validate the target CPU */ 35 if (!is_valid_mpidr(target_cpu)) { 36 return PSCI_E_INVALID_PARAMS; 37 } 38 >>> CID 472145: Integer handling issues (NEGATIVE_RETURNS) >>> "target_idx" is passed to a parameter that cannot be negative. 39 ep = get_cpu_data_by_index(target_idx, warmboot_ep_info); 40 /* Validate the lower EL entry point and put it in the entry_point_info */ 41 rc = psci_validate_entry_point(ep, entrypoint, context_id); 42 if (rc != PSCI_E_SUCCESS) { 43 return rc; 44 } ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

8 months, 4 weeks

1
0
0 0

TF-A Tech Forum on June 12th 2025 - TF-RMM live activation

by Olivier Deprez

Hi, On June 12th 2025, the TF-A Tech forum will take place at 4.00pm UK with the following topic: TF-RMM live activation design discussion Presenters: Andre Przywara Soby Mathew Manish Badarkhe In this meeting, we aim to discuss the details of live firmware activation for TF-RMM. The key topics will include: * Design details of TF-RMM live activation * Rationale for EL3-RMM communication changes: We will explain the motivation behind the proposed changes to the communication mechanism between EL3 and RMM which simplifies internal state migration for LFA, enables sharing of the state across RMM instances that are live-activated, supports localized per-CPU allocations for NUMA and multi-chip configurations, decouples the RMM binary from platform-specifics. * LFA SMC Implementation in EL3: We will also provide an overview of the LFA SMC implementation at EL3. Regards, Olivier. TF-A Tech Forum Thursday Jun 12, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org

9 months

2
1
0 0

FVP_Base_Cortex-A520 crash

by shaunak saha

Hi All, I'm new to TF-A. While working on enabling Linux on A-520 FVP, I ran into an issue that I wanted to ask about. My stack looks like this:TF-A->U-boot->kernel. Initially I was able to boot on Base FVP(FVP_Base_RevC-2xAEMvA) and get to the linux console. Now we need to enable the same for A-520 FVP as our soc will be A-520. I saw the crash happening very early in "cpu_helpers.S. I made the change in plat/arm/board/fvp/platform.mk by adding lib/cpus/aarch64/cortex_a520.S in one of the FVP_CPU_LIBS and enabling the ERRATA_A520_2938996, ERRATA_A520_2858100 and ERRATA_A520_2630792. These changes helped me get past the TF-A and now i ' m seeing a crash inside kernel in pci. 16.720973] pci-host-generic 40000000.pci: host bridge /pci@40000000 ranges: [ 16.721375] pci-host-generic 40000000.pci: MEM 0x0050000000..0x005fffffff -> 0x0050000000 [ 16.722013] pci-host-generic 40000000.pci: ECAM at [mem 0x40000000-0x4fffffff] for [bus 00-ff] [ 16.723128] pci-host-generic 40000000.pci: PCI host bridge to bus 0000:00 [ 16.723461] pci_bus 0000:00: root bus resource [bus 00-ff] [ 16.723761] pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff] [ 16.724101] Internal error: synchronous external abort: 0000000096000010 [#1] SMP [ 16.724216] Modules linked in: [ 16.724302] CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.15.0-rc7-dirty #12 PREEMPT [ 16.724449] Hardware name: FVP Base RevC (DT) [ 16.724531] pstate: 214000c9 (nzCv daIF +PAN -UAO -TCO +DIT -SSBS BTYPE=--) [ 16.724666] pc : pci_generic_config_read+0x38/0xb8 [ 16.724802] lr : pci_generic_config_read+0x24/0xb8 [ 16.724939] sp : ffff80008272b940 [ 16.725012] x29: ffff80008272b940 x28: 0000000000000000 x27: ffff800081dc00b0 [ 16.725205] x26: ffff800081ec9060 x25: ffff800081ec9078 x24: ffff80008266a9a0 [ 16.725401] x23: 0000000000000000 x22: ffff80008272b9f4 x21: ffff000800fa8000 [ 16.725594] x20: ffff80008272b964 x19: 0000000000000004 x18: 0000000000000006 [ 16.725781] x17: 6666666666663478 x16: 302d303030303030 x15: ffff800082edbbbf [ 16.725980] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 [ 16.726166] x11: 0000000000000001 x10: 3ea1f6d484b7e318 x9 : 69631046f78aed23 [ 16.726355] x8 : ffff000800169108 x7 : ffff800082250960 x6 : 00000000000000ff [ 16.726547] x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffff800090000000 [ 16.726738] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff800090000000 Do i need to do enable somethign else in TF-A? I tried adding : pci: pci@40000000 { compatible = "pci-host-ecam-generic"; device_type = "pci"; bus-range = <0x0 0xff>; reg = <0x0 0x40000000 0x0 0x10000000>; ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; }; in plat/arm/board/fvp/fdts/fvp_soc_fw_config.dts but it does not help. Also I see the kernel is not able to bring all the cpu's online: [ 0.040364] smp: Bringing up secondary CPUs ... [ 5.116993] CPU1: failed to come online [ 5.117063] CPU1: failed in unknown state : 0x0 [ 10.266076] CPU2: failed to come online [ 10.266152] CPU2: failed in unknown state : 0x0 [ 15.415178] CPU3: failed to come online [ 15.415247] CPU3: failed in unknown state : 0x0 [ 15.421021] psci: failed to boot CPU4 (-22) [ 15.421099] CPU4: failed to boot: -22 [ 15.425045] psci: failed to boot CPU5 (-22) [ 15.425123] CPU5: failed to boot: -22 [ 15.429079] psci: failed to boot CPU6 (-22) [ 15.429157] CPU6: failed to boot: -22 [ 15.433153] psci: failed to boot CPU7 (-22) [ 15.433227] CPU7: failed to boot: -22 [ 15.433587] smp: Brought up 1 node, 1 CPU [ 15.433672] SMP: Total of 1 processors activated. [ 15.433746] CPU: All CPU(s) started at EL2 I’m still getting familiar with the codebase and community, so apologies if this has already been addressed. I’d really appreciate any guidance or pointers, and if this is a known issue or good for a first-time contributor, I’d be happy to help. Regards, Shaunak

9 months, 2 weeks

2
2
0 0

Trusted Firmware-A LTS v2.8.33 Release Announcement

by svc_openci_enginfra＠arm.com

Hello, Trusted Firmware-A LTS version 2.8.33 is now available. This release contains the following patches: a95dba188 build(npm): adhere to Husky deprecation notice [1] fc3a26e5f fix(deps): remove deprecated husky commands [2] a96d034d0 fix(cpus): drop esb from the Neoverse N1 [3] 3bd1d85f1 chore(docs): add a SBOM template in CycloneDX format [4] [1] https://review.trustedfirmware.org/q/I18ea1bbaedbb4213cc04c21413d75c9757ff7… [2] https://review.trustedfirmware.org/q/I8b7fa82aa7b5e178554a1b4a650b2b1b80440… [3] https://review.trustedfirmware.org/q/I5775180ec61373cc5d1b9831e3fa0f2fbb19e… [4] https://review.trustedfirmware.org/q/Ia34338854a0eaa4f3a8799c23e46aae382792… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.33/change-log.html Thanks, TF-A LTS team

9 months, 2 weeks

1
0
0 0

Planned Jenkins migration - Friday 30 May 2025, 14:30-18:30 BST

by Chris Kay

Hi folks, We are planning on going live with the migration of the TF.org Open CI tomorrow, Friday 30th May, which will migrate Jenkins (ci.trustedfirmware.org) from on-premises to cloud-managed infrastructure. We expect a downtime of 2-4 hours beginning at 14:30 GMT+1, during which anything which interacts with Jenkins will be unavailable. Please note that the Jenkins build history is not being transferred - if you have Gerrit changes in review with the Allow-CI+1/+2 label, you will need to retrigger the CI once migration is complete by reapplying the label. We will send out a follow-up email once we have restored service availability. Regards, Chris

9 months, 2 weeks

1
1
0 0

Canceled event with note: TF-A Tech Forum @ Thu May 29, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling as no topic planned for this week. Regards, Olivier. " TF-A Tech Forum Thursday May 29, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

9 months, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.12.3 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.12.3 is now available. This release contains the following patches: 70ed22957 fix(deps): remove deprecated husky commands [1] 1967879b3 chore(cpus): remove in-order checks [2] 5d8f821c5 refactor(cpus): drop unused argument forward_flag [3] 1ca07cd72 refactor(cpus): move errata check to common code [4] 481e161eb refactor(cpus): optimize CVE checking [5] fdd706702 fix(cpus): drop esb from the Neoverse N1 [6] 88da40bcb chore(docs): add a SBOM template in CycloneDX format [7] 1cd56abd8 docs(prerequisites): update mbedtls to v3.6.3 [8] cb3aea9ca feat(mbedtls): update mbedtls to version 3.6.3 [9] [1] https://review.trustedfirmware.org/q/I8b7fa82aa7b5e178554a1b4a650b2b1b80440… [2] https://review.trustedfirmware.org/q/Iee5a8cb49834e9f35c6c2f2a84065430ca1ec… [3] https://review.trustedfirmware.org/q/Ib1fcbe081e94657e21d983e0db59ceec9993b… [4] https://review.trustedfirmware.org/q/I2c6d4468f7125d4d99ccdebc5ea8f9e439036… [5] https://review.trustedfirmware.org/q/I873534e367a35c99461d0a616ff7bf856a000… [6] https://review.trustedfirmware.org/q/I5775180ec61373cc5d1b9831e3fa0f2fbb19e… [7] https://review.trustedfirmware.org/q/Ia34338854a0eaa4f3a8799c23e46aae382792… [8] https://review.trustedfirmware.org/q/I62bc0fd6e40a38143ad3118a2e8e8d63c728a… [9] https://review.trustedfirmware.org/q/Icad24203a36cb7e5b0a6f2275cb3b5346dcd1… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.3/change-log.html Thanks, TF-A LTS team

9 months, 3 weeks

1
0
0 0

Trusted Firmware-A LTS v2.10.17 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.17 is now available. This release contains the following patches: 93982eb31 build(npm): adhere to Husky deprecation notice [1] 2f7327030 fix(cpus): drop esb from the Neoverse N1 [2] b42c3c05c chore(docs): add a SBOM template in CycloneDX format [3] [1] https://review.trustedfirmware.org/q/I18ea1bbaedbb4213cc04c21413d75c9757ff7… [2] https://review.trustedfirmware.org/q/I5775180ec61373cc5d1b9831e3fa0f2fbb19e… [3] https://review.trustedfirmware.org/q/Ia34338854a0eaa4f3a8799c23e46aae382792… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.17/change-log.html Thanks, TF-A LTS team

9 months, 3 weeks

1
0
0 0

Trusted Firmware-A LTS v2.8.32 Release Announcement

by ci_notify＠trustedfirmware.org

9 months, 3 weeks

1
0
0 0

Trusted Firmware v2.13 release announcement

by Olivier Deprez

Hi All, We are pleased to announce the formal release of Trusted Firmware-A version 2.13 bundle of project deliverables. This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium, TF-RMM, Trusted Services, and TF-A OpenCI scripts/jobs components. These went live on May, 22nd 2025. Please find references to tags and change logs at the end of this email. Many thanks to the trustedfirmware.org community for the active engagement in delivering this release! Notable features of the release version 2.13 are as follows: TF-A/EL3 * Alto CPU support * Architecture feature support for PMUv3p9. PAUTH_LR and SPE_FDS. * Refactor PSCI to let each CPU core initialise its own context, allowing TF-A to natively handle asymmetric configurations * PSCI Powerdown abandon feature support * SMCCC_FEATURE_AVAILABILITY support based on SMCCC v1.5 specification * Firmware Handoff * Library enhancements to add more TE types in library * All BL interfaces for FVP are now migrated to use Transfer List along in different boot scenarios (RESET_TO_BL1/BL2/BL31) * TC platform is now using Transfer List for booting * HOB creation Library (from edk2) is now hosted in TF-A * New Platforms: mt8189, mt8196, qcs615, RK3576, AM62L Boot flow * Feature Additions * Added discrete TPM support in BL1/BL2 for the RPi3 platform. * Support for MbedTLS PSA Crypto with ROMLIB on FVP. * Redesigned PSA Crypto Key ID management to avoid repeated key creation/destruction. * Test Additions * Support for MbedTLS PSA Crypto with ROMLIB on FVP. * Added basic boot test for TF-RMM with TF-A and TFTF (Realm Payload) in Jenkins CI. * Integrated DRTM ACS test suite into TF-A Jenkins CI. * Added missing test configuration for ROTPK in register on FVP platform. * Build System * Refactored ROTPK key/hash generation to auto-generate required files during build. * mbedTLS Improvements * Migrated to mbedTLS version 3.6.3. Errata/Security mitigations (CPU/GIC) * CVE-2024-5660, CVE-2024-7881 * Cortex-A510, Cortex-A715, Cortex-X4, Cortex-X925, Neoverse V3 Hafnium/SPM (S-EL2) * FF-A v1.2 completed: indirect messaging with service UUIDs. * FF-A v1.3 early adoption: Update to FFA_MEM_PERM_GET ABIs. * StMM integration: provide HOB structure as boot information. * Power management update: * Bootstrapped secondary vCPUs on secondary cores power on flows. * SP's subscription to the power off event. * SP loading: SP artefacts can be bundled in a TL format. I.e SP binary and SP manifest (DTB). * Resuming ECs for interrupt handling assisted by NWd Scheduler when the SP is in waiting state, with sri-interrupts-policy field in the SP manifest. TF-RMM (R-EL2) * Deprivileging RMM code via EL0 App support * Added some support for some RMMv1.1 APIs - "RMI_DEV_MEM_(UN)MAP", support for device granules in "RMI_GRANULE_DELEGATE" and "RMI_GRANULE_UNDELEGATE". * Additional hardening of RMM via compiler flags `-fstack-protector-strong`, '-Wextra', '-Wstrict-overflow', '-D_FORTIFY_SOURCE=2' and '-Wnull-dereference'. * New platform support for RD-V3-R1 and RD-V3-R1-Cfg1 FVPs. * Dynamic discovery of PCIE Root complex topology and device memory from the Boot manifest. Trusted Services (v1.2.0) * Introduced the fTPM SP. The implementation is experimental. * Introduce the new Arm Reference Design-1 AE platform targeting the Automotive segment. It features high-performance Arm Neoverse V3AE Application Processor compute system, Arm Cortex-R82AE based Safety Island, and a Runtime Security Engine (RSE) for enhanced security. * Updated the se-proxy deployment and added support for the Firmware Update Proxy service. The FWU Proxy implements a Platform Security Firmware Update for the A-profile Arm Architecture<https://developer.arm.com/documentation/den0118/latest/> compliant FWU Agent which runs a PSA Certified Firmware Update API 1.0<https://arm-software.github.io/psa-api/fwu/1.0/> compliant client as its backend. TF-A Tests * Enhancements to fuzzing tests (EL3 vendor specific SMC, SDEI, FF-A interface, capability for randomized fuzzing inputs) * Functionality test * Firmware Handoff : AArch32 tests and event log testing * SMCCC_ARCH_FEATURE_AVAILABILITY * RAS system registers, FPMR, SCTLR2, THE and D128 * validate psci_is_last_cpu_to_idle_at_pwrlvl * SPM/FF-A : HOB generation, PPI timer interrupts, v1.2 RXTX headers * RMM: Tests introduced for majority of features developed in RMM * Platform Support * Versal NET * Versal * Neoverse-RD Release tags across repositories: https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r… https://git.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags… https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-ci-scripts/+/refs/t… https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-job-configs/+/refs/… https://git.trustedfirmware.org/plugins/gitiles/hafnium/hafnium.git/+/refs/… https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-ci-scripts/+/ref… https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-job-configs/+/re… https://git.trustedfirmware.org/plugins/gitiles/TF-RMM/tf-rmm/+/refs/tags/t… https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/… Change logs: https://trustedfirmware-a.readthedocs.io/en/v2.13.0/change-log.html#id1 https://trustedfirmware-a-tests.readthedocs.io/en/v2.13.0/change-log.html#v… https://hafnium.readthedocs.io/en/v2.13.0/change-log.html#v2-13 https://tf-rmm.readthedocs.io/en/latest/about/change-log.html#v0-7-0 https://trusted-services.readthedocs.io/en/stable/project/change-log.html#v… Regards, Olivier.

9 months, 3 weeks

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu May 15, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, No topic proposed so cancelling this week. Regards, Olivier. " TF-A Tech Forum Thursday May 15, 2025 ⋅ 5pm – 6pm Central European Time - Paris Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

10 months

1
0
0 0

Re: Question about memory mapping attributes for MT_DEVICE

by Olivier Deprez

The email was moderated, re-sending on behalf of Andrei. ________________________________ From: Andrei Stefanescu <andrei.stefanescu(a)nxp.com> Sent: 13 May 2025 12:35 To: tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org> Cc: Ghennadi Procopciuc <ghennadi.procopciuc(a)nxp.com>; Ciprian Marian Costea <ciprianmarian.costea(a)nxp.com>; Alexandru-Catalin Ionita <alexandru-catalin.ionita(a)nxp.com> Subject: Question about memory mapping attributes for MT_DEVICE Hi, I noticed that the memory mapping attributes for MT_DEVICE memory are defined to: nGnRE [1]. Why was nGnRE selected instead of nGnRnE? Platforms which have USE_COHERENT_MEM set to 1 will map the coherent memory area as MT_DEVICE. This area is helpful for cases where a backery lock is shared between cores which have MMU enabled and cores which don’t (whose access is equivalent to nGnRnE). This would generate an access attributes mismatch for the coherent memory area. Would it be ok to send a patch which changes the ATTR_DEVICE to nGnRnE? Best regards, Andrei Stefanescu [1] - https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a.git…

10 months

3
6
0 0

Changelog for v2.13 Release

by Govindraj Raja

Hello Everyone, Ahead of the TF-A v2.13 release, please review the autogenerated changelog for your platform. It’s built from the commit messages of all patches merged since v2.12. If you spot anything that needs a quick manual tweak, just let us know. Patch: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/38170 Rendered Version: https://ci-builds.trustedfirmware.org/static-files/Jr7PSOAIj0pMAfjvJ-b7Y7G7… -- Thanks, Govindraj R

10 months, 1 week

1
0
0 0

Trusted Firmware-A LTS v2.10.16 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.16 is now available. This release contains the following patches: 3b9e21608 chore(cpus): remove in-order checks [1] d7483aa8f fix(cpus): add missing add_erratum_entry [2] ab526df97 refactor(cpus): drop unused argument forward_flag [3] a86f15fb2 refactor(cpus): move errata check to common code [4] 5a1a6929f refactor(cpus): optimize CVE checking [5] [1] https://review.trustedfirmware.org/q/Iee5a8cb49834e9f35c6c2f2a84065430ca1ec… [2] https://review.trustedfirmware.org/q/I19a484c73ac31a90b3ff1b219f647c88a1c81… [3] https://review.trustedfirmware.org/q/Ib1fcbe081e94657e21d983e0db59ceec9993b… [4] https://review.trustedfirmware.org/q/I2c6d4468f7125d4d99ccdebc5ea8f9e439036… [5] https://review.trustedfirmware.org/q/I873534e367a35c99461d0a616ff7bf856a000… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.16/change-log.html Thanks, TF-A LTS team

10 months, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.8.31 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.31 is now available. This release contains the following patches: 30d688676 fix(cpus): workaround for Cortex-X4 erratum 2957258 [1] b4dd8f62f fix(cpus): workaround for Neoverse-V3 erratum 2970647 [2] 34614e084 fix(cpus): fix a typo in errata doc [3] fa4bdbb57 fix(cpus): declare reset errata correctly [4] 9ec650fc7 refactor(cpus): convert the Cortex-A65 to use the errata framework [5] 88ca67b78 refactor(cpus): convert checker functions to standard helpers [6] f67c3ea96 perf(cpus): inline cpu_rev_var checks [7] 6a6b0bed3 refactor(cpus): directly invoke errata reporter [8] d54e07a25 refactor(cpus): remove cpu specific errata funcs [9] d1ea85820 refactor(cpus): declare runtime errata correctly [10] 7bf485d93 refactor(cpus): register DSU errata with the errata framework's wrappers [11] [1] https://review.trustedfirmware.org/q/I2d8e7f4ce19ca2e1d87527c31e7778d81aff0… [2] https://review.trustedfirmware.org/q/Iedf7d799451f0be58a5da1f93f7f5b6940f2b… [3] https://review.trustedfirmware.org/q/I2332a3fcaf56a7aaab5a04e3d40428cc746d2… [4] https://review.trustedfirmware.org/q/I22c3043ab454ce94b3c122c856e5804bc2ebb… [5] https://review.trustedfirmware.org/q/I91cd6111ccf95d6b7ee2364ac2126cb98ee4b… [6] https://review.trustedfirmware.org/q/Ic1dff2bc5235195f7cfce1709cd42467f88b3… [7] https://review.trustedfirmware.org/q/I51608352f23b2244ea7a99e76c10892d257f1… [8] https://review.trustedfirmware.org/q/Ie4a4fd60429aca37cf434e79c0ce2992a5ff5… [9] https://review.trustedfirmware.org/q/I04fefbde5f0ff63b1f1cd17c864557a14070d… [10] https://review.trustedfirmware.org/q/I316daeee603e86c9f2bdccf91e1b10f7ec6c3… [11] https://review.trustedfirmware.org/q/Iefa36325804ea093e938f867b9a6f49a6984b… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.31/change-log.html Thanks, TF-A LTS team

10 months, 2 weeks

1
0
0 0

Invitation: TF-A Tech Forum @ Every 2 weeks from 4pm to 5pm on Thursday (BST) (tf-a@lists.trustedfirmware.org)

by Shaun Longhorn

TF-A Tech Forum Every 2 weeks from 4pm to 5pm on Thursday United Kingdom Time Location https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34… https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786… Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu, 78 occurrence(s)Please download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJcocu6gqDgjEtOkyBhSQauR1sUyFwIcNKLa/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34.1Meeting ID: 935 5786 3987Passcode: 939141---One tap mobile+12532158782,,93557863987# US (Tacoma)+13017158592,,93557863987# US (Washington DC)---Dial by your location• +1 253 215 8782 US (Tacoma)• +1 301 715 8592 US (Washington DC)• +1 305 224 1968 US• +1 309 205 3325 US• +1 312 626 6799 US (Chicago)• +1 346 248 7799 US (Houston)• +1 360 209 5623 US• +1 386 347 5053 US• +1 507 473 4847 US• +1 564 217 2000 US• +1 646 558 8656 US (New York)• +1 646 931 3860 US• +1 669 444 9171 US• +1 669 900 9128 US (San Jose)• +1 689 278 1000 US• +1 719 359 4580 US• +1 253 205 0468 US• 833 548 0276 US Toll-free• 833 548 0282 US Toll-free• 833 928 4608 US Toll-free• 833 928 4609 US Toll-free• 833 928 4610 US Toll-free• 877 853 5247 US Toll-free• 888 788 0099 US Toll-freeMeeting ID: 935 5786 3987Find your local number: https://linaro-org.zoom.us/u/adoz9mILli Guests tf-a(a)lists.trustedfirmware.org View all guest info https://calendar.google.com/calendar/event?action=VIEW&eid=NnR0NGMyZWJkdnBn… Reply for tf-a(a)lists.trustedfirmware.org and view more details https://calendar.google.com/calendar/event?action=VIEW&eid=NnR0NGMyZWJkdnBn… Your attendance is optional. ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

10 months, 2 weeks

1
0
0 0

TF-A Tech forum on May 1st - cancelled

by Olivier Deprez

Hi, For some reason the invite disappeared from the shared trustedfirmware.org calendar but this message is to state there is no TF-A tech forum planned tomorrow May 1st due to lack of topics. Thanks & Regards, Olivier.

10 months, 2 weeks

1
0
0 0

Trusted Firmware-A LTS v2.12.2 Release Announcement

by ci_notify＠trustedfirmware.org

10 months, 3 weeks

1
0
0 0

Adding new platform support for ADI's ADSP-SC598

by Agarwal, Utsav

Hi All, We currently have TF-A/OP-TEE support for a platform (ADSP-SC598, arm cortex A55) in our forked repositories and would like to upstream our past efforts to align better with newer developments within the projects. As per the contributor's guide for TF-A, it mentions that it might be a good idea to start a discussion regarding the same prior to submission of a patch series. Currently, the plan is for the initial patch series to support BL31 followed by another patch series adding support for PSCI. The overarching idea being that BOOTROM passes control to u-boot SPL, which configures required peripherals and loads us into TF-A, then proceeding to load OP-TEE, followed by full uboot/linux. Please let me know your thoughts/concerns and if I should be proceeding with the patch series submission. Regards, Utsav Agarwal

10 months, 3 weeks

2
2
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW) /services/std_svc/sdei/sdei_event.c: 79 in get_event_entry_target_pe() ________________________________________________________________________________________________________ *** CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW) /services/std_svc/sdei/sdei_event.c: 79 in get_event_entry_target_pe() 73 */ 74 idx = mapsub; 75 76 /* Base of private mappings for this CPU */ 77 base_idx = (unsigned int) plat_core_pos_by_mpidr(target_pe); 78 base_idx *= nm; >>> CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW) >>> "base_idx", which might have underflowed, is passed to "sdei_private_event_table[base_idx]". 79 cpu_priv_base = &sdei_private_event_table[base_idx]; 80 /* 81 * Return the address of the entry at the same index in the 82 * per-CPU event entry. 83 */ 84 return &cpu_priv_base[idx]; ** CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS) /services/std_svc/sdei/sdei_intr_mgmt.c: 64 in sdei_is_target_pe_masked() ________________________________________________________________________________________________________ *** CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS) /services/std_svc/sdei/sdei_intr_mgmt.c: 64 in sdei_is_target_pe_masked() 58 59 /* SDEI states for all cores in the system */ 60 static sdei_cpu_state_t cpu_state[PLATFORM_CORE_COUNT]; 61 62 bool sdei_is_target_pe_masked(uint64_t target_pe) 63 { >>> CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS) >>> Using variable "plat_core_pos_by_mpidr(target_pe)" as an index to array "cpu_state". 64 const sdei_cpu_state_t *state = sdei_get_target_pe_state(target_pe); 65 66 return state->pe_masked; 67 } 68 69 int64_t sdei_pe_mask(void) ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

10 months, 3 weeks

1
0
0 0

Looking for Gerrit admin for my account issue

by Yu-Ping Wu

I need Gerrit admin's help to delete my old Gerrit account. Who should I contact? -- Yu-Ping Wu | Software Engineer | yupingso(a)google.com | +886 937 057 080

10 months, 3 weeks

2
1
0 0

Trusted Firmware-A LTS v2.10.15 Release Announcement

by ci_notify＠trustedfirmware.org

11 months

1
0
0 0

trustedfirmware git and gerrit slowness

by Olivier Deprez

Hi, You must have noticed slowness or breakages with review.trustedfirmware.org or git.trustedfirmware.org during the week. There are high and lows of network bandwidth usage affecting server availability. The issue is being investigated but not yet 100% root caused. Apologies for the frustration and inconvenience that this is causing. Rest assured the team is on board to resolve this unfortunate situation. Regards, Olivier.

11 months

1
0
0 0

Canceled event: TF-A Tech Forum @ Thu Apr 17, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled. TF-A Tech Forum Thursday Apr 17, 2025 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

11 months

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 461861: Code maintainability issues (UNUSED_VALUE) /plat/ti/k3low/common/am62l_psci.c: 35 in am62l_pwr_domain_on() ________________________________________________________________________________________________________ *** CID 461861: Code maintainability issues (UNUSED_VALUE) /plat/ti/k3low/common/am62l_psci.c: 35 in am62l_pwr_domain_on() 29 int32_t core, ret; 30 uint8_t proc_id; 31 32 core = plat_core_pos_by_mpidr(mpidr); 33 if (core < 0) { 34 ERROR("Could not get target core id: %d\n", core); >>> CID 461861: Code maintainability issues (UNUSED_VALUE) >>> Assigning value "-6" to "ret" here, but that stored value is overwritten before it can be used. 35 ret = PSCI_E_INTERN_FAIL; 36 } 37 38 proc_id = (uint8_t)(PLAT_PROC_START_ID + (uint32_t)core); 39 40 ret = ti_sci_proc_request(proc_id); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

11 months, 1 week

2
1
0 0

Canceled event: TF-A Tech Forum @ Thu Apr 3, 2025 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled. TF-A Tech Forum Thursday Apr 3, 2025 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

11 months, 2 weeks

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 458349: Integer handling issues (INCOMPATIBLE_CAST) ________________________________________________________________________________________________________ *** CID 458349: Integer handling issues (INCOMPATIBLE_CAST) /plat/intel/soc/common/socfpga_sip_svc.c: 2190 in sip_smc_handler_v1() 2184 SMC_RET1(handle, status); 2185 } else { 2186 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2187 } 2188 2189 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: >>> CID 458349: Integer handling issues (INCOMPATIBLE_CAST) >>> Pointer "&x1" points to an object whose effective type is "unsigned long" (64 bits, unsigned) but is dereferenced as a narrower "unsigned int" (32 bits, unsigned). This may lead to unexpected results depending on machine endianness. 2190 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2191 SMC_RET1(handle, status); 2192 2193 case INTEL_SIP_SMC_ATF_BUILD_VER: 2194 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2195 VERSION_MINOR, VERSION_PATCH); ** CID 458348: Integer handling issues (INCOMPATIBLE_CAST) ________________________________________________________________________________________________________ *** CID 458348: Integer handling issues (INCOMPATIBLE_CAST) /plat/intel/soc/common/socfpga_sip_svc.c: 1250 in sip_smc_handler_v3() 1244 0); 1245 SMC_RET1(handle, status); 1246 } 1247 1248 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1249 { >>> CID 458348: Integer handling issues (INCOMPATIBLE_CAST) >>> Pointer "&x4" points to an object whose effective type is "unsigned long" (64 bits, unsigned) but is dereferenced as a narrower "unsigned int" (32 bits, unsigned). This may lead to unexpected results depending on machine endianness. 1250 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1251 (uint32_t *) &x4, &mbox_error); 1252 SMC_RET1(handle, status); 1253 } 1254 1255 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

11 months, 2 weeks

1
0
0 0

Removal of erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock”.

by Govindraj Raja

Hi All, If you're downstream platform maintainer or maintainer for mtk or qti platforms for TF-A, I want to bring to your attention about this patch in review - https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/36700 This patch removes erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock” this should not be handled within TF-A. The static setting of PF_MODE in TF-A does not correctly address the erratum and may introduce unnecessary performance degradation on platforms that adopt it without fully understanding its implications. -- Thanks, Govindraj R

11 months, 3 weeks

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 49 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 13 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 20 of 49 defect(s) ** CID 457912: Concurrent data access violations (MISSING_LOCK) /services/std_svc/sdei/sdei_event.c: 117 in sdei_get_registered_event_count() ________________________________________________________________________________________________________ *** CID 457912: Concurrent data access violations (MISSING_LOCK) /services/std_svc/sdei/sdei_event.c: 117 in sdei_get_registered_event_count() 111 unsigned int j; 112 int count = 0; 113 114 /* Add up reg counts for each mapping. */ 115 for_each_mapping_type(i, mapping) { 116 iterate_mapping(mapping, j, map) { >>> CID 457912: Concurrent data access violations (MISSING_LOCK) >>> Accessing "map->reg_count" without holding lock "sdei_ev_map.lock". Elsewhere, "sdei_ev_map.reg_count" is written to with "sdei_ev_map.lock" held 2 out of 3 times. 117 count += map->reg_count; 118 } 119 } 120 121 return count; ** CID 457911: Null pointer dereferences (REVERSE_INULL) /plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_cpu_pm.c: 801 in cpupm_invoke() ________________________________________________________________________________________________________ *** CID 457911: Null pointer dereferences (REVERSE_INULL) /plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_cpu_pm.c: 801 in cpupm_invoke() 795 ret = MTK_CPUPM_E_ERR; 796 break; 797 #endif /* CPU_PM_SUSPEND_NOTIFY */ 798 799 #ifdef CPU_PM_PWR_REQ 800 case CPUPM_INVOKE_PWR_REQ_ACTIVE: >>> CID 457911: Null pointer dereferences (REVERSE_INULL) >>> Null-checking "priv" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 801 if (priv) { 802 if (req->stat.uid == CPUPM_PWR_REQ_UID_MAGIC) 803 req->stat.uid = CPUPM_PWR_STAT_REQ_UID_MAGIC; 804 else 805 ret = MTK_CPUPM_E_ERR; 806 } else ** CID 457910: Integer handling issues (INTEGER_OVERFLOW) /lib/libc/strtoll.c: 128 in strtoll() ________________________________________________________________________________________________________ *** CID 457910: Integer handling issues (INTEGER_OVERFLOW) /lib/libc/strtoll.c: 128 in strtoll() 122 any = 1; 123 acc *= base; 124 acc += c; 125 } 126 } 127 if (any < 0) { >>> CID 457910: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "acc", where "neg ? -9223372036854775808LL : 9223372036854775807LL" is known to be equal to -9223372036854775808, underflows the type of "acc", which is type "unsigned long long". 128 acc = neg ? LLONG_MIN : LLONG_MAX; 129 } else if (neg) 130 acc = -acc; 131 if (endptr != NULL) 132 *endptr = (char *)(any ? s - 1 : nptr); 133 return (acc); ** CID 457909: (INTEGER_OVERFLOW) /drivers/nxp/ddr/nxp-ddr/regs.c: 159 in cal_timing_cfg() /drivers/nxp/ddr/nxp-ddr/regs.c: 128 in cal_timing_cfg() ________________________________________________________________________________________________________ *** CID 457909: (INTEGER_OVERFLOW) /drivers/nxp/ddr/nxp-ddr/regs.c: 159 in cal_timing_cfg() 153 const unsigned int ext_acttopre = picos_to_mclk(clk, 154 pdimm->tras_ps) >> 4U; 155 const unsigned int ext_acttorw = picos_to_mclk(clk, 156 pdimm->trcd_ps) >> 4U; 157 const unsigned int ext_caslat = (2U * cas_latency - 1U) >> 4U; 158 const unsigned int ext_add_lat = additive_latency >> 4U; >>> CID 457909: (INTEGER_OVERFLOW) >>> Expression "picos_to_mclk(clk, pdimm->trfc1_ps) - 8U", where "picos_to_mclk(clk, pdimm->trfc1_ps)" is known to be equal to 0, underflows the type of "picos_to_mclk(clk, pdimm->trfc1_ps) - 8U", which is type "unsigned int". 159 const unsigned int ext_refrec = (picos_to_mclk(clk, 160 pdimm->trfc1_ps) - 8U) >> 4U; 161 const unsigned int ext_wrrec = (picos_to_mclk(clk, pdimm->twr_ps) + 162 (popts->otf_burst_chop_en ? 2U : 0U)) >> 4U; 163 const unsigned int rwt_same_cs = 0U; 164 const unsigned int wrt_same_cs = 0U; /drivers/nxp/ddr/nxp-ddr/regs.c: 128 in cal_timing_cfg() 122 const int acttorw_mclk = picos_to_mclk(clk, pdimm->trcd_ps); 123 const int caslat_ctrl = (cas_latency - 1) << 1; 124 const int trfc1_min = pdimm->die_density >= 0x3 ? 16000 : 125 (pdimm->die_density == 0x4 ? 26000 : 126 (pdimm->die_density == 0x5 ? 35000 : 127 55000)); >>> CID 457909: (INTEGER_OVERFLOW) >>> Expression "refrec_ctrl", where "picos_to_mclk(clk, pdimm->trfc1_ps) - 8U" is known to be equal to 4294967288, overflows the type of "refrec_ctrl", which is type "int const". 128 const int refrec_ctrl = picos_to_mclk(clk, 129 pdimm->trfc1_ps) - 8; 130 int wrrec_mclk = picos_to_mclk(clk, pdimm->twr_ps); 131 const int acttoact_mclk = max(picos_to_mclk(clk, 132 pdimm->trrds_ps), 133 4U); ** CID 457908: (INTEGER_OVERFLOW) /drivers/marvell/amb_adec.c: 70 in amb_check_win() /drivers/marvell/amb_adec.c: 60 in amb_check_win() ________________________________________________________________________________________________________ *** CID 457908: (INTEGER_OVERFLOW) /drivers/marvell/amb_adec.c: 70 in amb_check_win() 64 } 65 66 /* size parameter validity check */ 67 if (!IS_POWER_OF_2(win->win_size)) { 68 WARN("Window %d: window size is not power of 2 (0x%" PRIx64 ")\n", 69 win_num, win->win_size); >>> CID 457908: (INTEGER_OVERFLOW) >>> Expression "win->win_size - 1UL", where "win->win_size" is known to be equal to 0, underflows the type of "win->win_size - 1UL", which is type "unsigned long". 70 win->win_size = ROUND_UP_TO_POW_OF_2(win->win_size); 71 WARN("Rounding size to 0x%" PRIx64 "\n", win->win_size); 72 } 73 } 74 75 static void amb_enable_win(struct addr_map_win *win, uint32_t win_num) /drivers/marvell/amb_adec.c: 60 in amb_check_win() 54 } 55 56 base_addr = win->base_addr << AMB_BASE_OFFSET; 57 /* for AMB The base is always 1M aligned */ 58 /* check if address is aligned to 1M */ 59 if (IS_NOT_ALIGN(base_addr, AMB_WIN_ALIGNMENT_1M)) { >>> CID 457908: (INTEGER_OVERFLOW) >>> Expression "base_addr + 1048576U", where "base_addr" is known to be equal to 4294901760, overflows the type of "base_addr + 1048576U", which is type "unsigned int". 60 win->base_addr = ALIGN_UP(base_addr, AMB_WIN_ALIGNMENT_1M); 61 WARN("Window %d: base address unaligned to 0x%x\n", 62 win_num, AMB_WIN_ALIGNMENT_1M); 63 WARN("Align up the base address to 0x%" PRIx64 "\n", win->base_addr); 64 } 65 ** CID 457907: Control flow issues (DEADCODE) /plat/mediatek/drivers/spm/mt8196/mt_spm_internal.c: 774 in __spm_set_pcm_wdt() ________________________________________________________________________________________________________ *** CID 457907: Control flow issues (DEADCODE) /plat/mediatek/drivers/spm/mt8196/mt_spm_internal.c: 774 in __spm_set_pcm_wdt() 768 /* Enable PCM WDT (normal mode) to start count if needed */ 769 if (en) { 770 mmio_clrsetbits_32(PCM_CON1, REG_PCM_WDT_WAKE_LSB, 771 SPM_REGWR_CFG_KEY); 772 773 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) >>> CID 457907: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "mmio_write_32(469779860UL, ...". 774 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); 775 mmio_write_32(PCM_WDT_VAL, mmio_read_32(PCM_TIMER_VAL) + 776 PCM_WDT_TIMEOUT); 777 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | 778 REG_PCM_WDT_EN_LSB); 779 } else { ** CID 457906: Integer handling issues (INTEGER_OVERFLOW) /plat/intel/soc/common/soc/socfpga_reset_manager.c: 1274 in socfpga_cpurstrelease() ________________________________________________________________________________________________________ *** CID 457906: Integer handling issues (INTEGER_OVERFLOW) /plat/intel/soc/common/soc/socfpga_reset_manager.c: 1274 in socfpga_cpurstrelease() 1268 cpurstrelease_status = mmio_read_32(SOCFPGA_RSTMGR(CPURSTRELEASE)); 1269 1270 if ((cpurstrelease_status & RSTMGR_CPUSTRELEASE_CPUx) == cpu_id) { 1271 return RSTMGR_RET_OK; 1272 } 1273 udelay(1000); >>> CID 457906: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "timeout--", where "timeout" is known to be equal to 0, underflows the type of "timeout--", which is type "unsigned int". 1274 } while (timeout-- > 0); 1275 1276 return RSTMGR_RET_ERROR; ** CID 457905: Parse warnings (PARSE_ERROR) /mbedtls/library/common.h: 23 in () ________________________________________________________________________________________________________ *** CID 457905: Parse warnings (PARSE_ERROR) /mbedtls/library/common.h: 23 in () 17 #include <assert.h> 18 #include <stddef.h> 19 #include <stdint.h> 20 #include <stddef.h> 21 22 #if defined(__ARM_NEON) >>> CID 457905: Parse warnings (PARSE_ERROR) >>> cannot open source file "arm_neon.h" 23 #include <arm_neon.h> 24 #define MBEDTLS_HAVE_NEON_INTRINSICS 25 #elif defined(MBEDTLS_PLATFORM_IS_WINDOWS_ON_ARM64) 26 #include <arm64_neon.h> 27 #define MBEDTLS_HAVE_NEON_INTRINSICS 28 #endif ** CID 457904: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /plat/rockchip/rk3576/scmi/rk3576_clk.c: 517 in rk3576_lpll_get_rate() ________________________________________________________________________________________________________ *** CID 457904: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /plat/rockchip/rk3576/scmi/rk3576_clk.c: 517 in rk3576_lpll_get_rate() 511 512 rate64 *= m; 513 rate64 = rate64 / p; 514 515 if (k != 0) { 516 /* fractional mode */ >>> CID 457904: Integer handling issues (OVERFLOW_BEFORE_WIDEN) >>> Potentially overflowing expression "24000000U * k" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). 517 uint64_t frac_rate64 = 24000000 * k; 518 519 postdiv = p * 65536; 520 frac_rate64 = frac_rate64 / postdiv; 521 rate64 += frac_rate64; 522 } ** CID 457903: Integer handling issues (INTEGER_OVERFLOW) /drivers/marvell/mv_ddr/ddr3_training_ip_engine.c: 1905 in mv_ddr_load_dm_pattern_to_odpg() ________________________________________________________________________________________________________ *** CID 457903: Integer handling issues (INTEGER_OVERFLOW) /drivers/marvell/mv_ddr/ddr3_training_ip_engine.c: 1905 in mv_ddr_load_dm_pattern_to_odpg() 1899 data_low = pattern_table_get_word(0, pattern, (u8)(pattern_len * 2)); 1900 data_high = pattern_table_get_word(0, pattern, (u8)(pattern_len * 2 + 1)); 1901 } 1902 1903 /* odpg mbus dm definition is opposite to ddr4 protocol */ 1904 if (dm_dir == DM_DIR_INVERSE) >>> CID 457903: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "dm_data", where "~((data_low & 0xfU) | (data_high & 0xf0U))" is known to be equal to 255, overflows the type of "dm_data", which is type "u8". 1905 dm_data = ~((data_low & LOW_NIBBLE_BYTE_MASK) | (data_high & HIGH_NIBBLE_BYTE_MASK)); 1906 else 1907 dm_data = (data_low & LOW_NIBBLE_BYTE_MASK) | (data_high & HIGH_NIBBLE_BYTE_MASK); 1908 1909 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_WR_DATA_LOW_REG, data_low, MASK_ALL_BITS); 1910 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_WR_DATA_HIGH_REG, data_high, MASK_ALL_BITS); ** CID 457902: Insecure data handling (INTEGER_OVERFLOW) ________________________________________________________________________________________________________ *** CID 457902: Insecure data handling (INTEGER_OVERFLOW) /lib/libfdt/fdt_rw.c: 495 in fdt_pack() 489 int mem_rsv_size; 490 491 FDT_RW_PROBE(fdt); 492 493 mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) 494 * sizeof(struct fdt_reserve_entry); >>> CID 457902: Insecure data handling (INTEGER_OVERFLOW) >>> "mem_rsv_size", which might have overflowed, is passed to "fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt32_ld(&((struct fdt_header const *)fdt)->size_dt_struct), fdt32_ld(&((struct fdt_header const *)fdt)->size_dt_strings))". 495 fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt), 496 fdt_size_dt_strings(fdt)); 497 fdt_set_totalsize(fdt, fdt_data_size_(fdt)); 498 499 return 0; ** CID 457901: Integer handling issues (INTEGER_OVERFLOW) /plat/mediatek/drivers/spmi/pmif_common.c: 111 in pmif_spmi_read_cmd() ________________________________________________________________________________________________________ *** CID 457901: Integer handling issues (INTEGER_OVERFLOW) /plat/mediatek/drivers/spmi/pmif_common.c: 111 in pmif_spmi_read_cmd() 105 ret = pmif_check_idle(arb->mstid); 106 if (ret) 107 goto done; 108 109 /* Send the command. */ 110 offset = arb->regs[PMIF_SWINF_3_ACC]; >>> CID 457901: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "opc << 30", where "opc" is known to be equal to 2, overflows the type of "opc << 30", which is type "int". 111 mmio_write_32((uintptr_t)(arb->base + offset), PMIF_RW_CMD_SET(opc, 0, sid, bc, addr)); 112 /* 113 * Wait for Software Interface FSM state to be WFVLDCLR, 114 * read the data and clear the valid flag. 115 */ 116 ret = pmif_check_vldclr(arb->mstid); ** CID 457900: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /lib/extensions/amu/aarch32/amu.c: 51 in amu_enable() ________________________________________________________________________________________________________ *** CID 457900: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /lib/extensions/amu/aarch32/amu.c: 51 in amu_enable() 45 /* Enable all architected counters by default */ 46 write_amcntenset0(AMCNTENSET0_Pn_MASK); 47 if (is_feat_amu_aux_supported()) { 48 unsigned int core_pos = plat_my_core_pos(); 49 50 /* Something went wrong if we're trying to write higher bits */ >>> CID 457900: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "get_amu_aux_enables(core_pos) & 4294901760U /* ~0xffffU */" is always 0 regardless of the values of its operands. This occurs as a value. 51 assert((get_amu_aux_enables(core_pos) & ~AMCNTENSET1_Pn_MASK) == 0); 52 write_amcntenset1(get_amu_aux_enables(core_pos)); 53 } 54 55 /* Bail out if FEAT_AMUv1p1 features are not present. */ 56 if (!is_feat_amuv1p1_supported()) { ** CID 457899: (INTEGER_OVERFLOW) /lib/libfdt/fdt_rw.c: 476 in fdt_open_into() ________________________________________________________________________________________________________ *** CID 457899: (INTEGER_OVERFLOW) /lib/libfdt/fdt_rw.c: 474 in fdt_open_into() 468 /* Try right after the old tree instead */ 469 tmp = (char *)(uintptr_t)fdtend; 470 if ((tmp + newsize) > ((char *)buf + bufsize)) 471 return -FDT_ERR_NOSPACE; 472 } 473 >>> CID 457899: (INTEGER_OVERFLOW) >>> "mem_rsv_size", which might have overflowed, is passed to "fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size, fdt32_ld(&((struct fdt_header const *)fdt)->size_dt_strings))". 474 fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size, 475 fdt_size_dt_strings(fdt)); 476 memmove(buf, tmp, newsize); 477 478 fdt_set_magic(buf, FDT_MAGIC); 479 fdt_set_totalsize(buf, bufsize); /lib/libfdt/fdt_rw.c: 476 in fdt_open_into() 470 if ((tmp + newsize) > ((char *)buf + bufsize)) 471 return -FDT_ERR_NOSPACE; 472 } 473 474 fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size, 475 fdt_size_dt_strings(fdt)); >>> CID 457899: (INTEGER_OVERFLOW) >>> "newsize", which might have underflowed, is passed to "memmove(buf, tmp, newsize)". [Note: The source code implementation of the function has been overridden by a builtin model.] 476 memmove(buf, tmp, newsize); 477 478 fdt_set_magic(buf, FDT_MAGIC); 479 fdt_set_totalsize(buf, bufsize); 480 fdt_set_version(buf, 17); 481 fdt_set_last_comp_version(buf, 16); ** CID 457898: Control flow issues (UNREACHABLE) /plat/socionext/synquacer/sq_psci.c: 142 in sq_system_off() ________________________________________________________________________________________________________ *** CID 457898: Control flow issues (UNREACHABLE) /plat/socionext/synquacer/sq_psci.c: 142 in sq_system_off() 136 gpio[1] |= 0x2; /* set high */ 137 dmbst(); 138 139 mdelay(100); 140 } 141 >>> CID 457898: Control flow issues (UNREACHABLE) >>> This code cannot be reached: "wfi();". 142 wfi(); 143 ERROR("SQ System Off: operation not handled.\n"); 144 panic(); 145 #endif 146 } 147 ** CID 457897: Integer handling issues (INTEGER_OVERFLOW) /drivers/marvell/mv_ddr/ddr3_training_ip_engine.c: 640 in ddr3_tip_ip_training() ________________________________________________________________________________________________________ *** CID 457897: Integer handling issues (INTEGER_OVERFLOW) /drivers/marvell/mv_ddr/ddr3_training_ip_engine.c: 640 in ddr3_tip_ip_training() 634 CHECK_STATUS(ddr3_tip_configure_odpg 635 (dev_num, access_type, interface_num, direction, 636 pattern_table[pattern].num_of_phases_tx, tx_burst_size, 637 pattern_table[pattern].num_of_phases_rx, 638 delay_between_burst, rd_mode, effective_cs, STRESS_NONE, 639 DURATION_SINGLE)); >>> CID 457897: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "reg_data", where "(direction == OPER_READ) ? 0 : -1073741824" is known to be equal to -1073741824, overflows the type of "reg_data", which is type "u32". 640 reg_data = (direction == OPER_READ) ? 0 : (0x3 << 30); 641 reg_data |= (direction == OPER_READ) ? 0x60 : 0xfa; 642 CHECK_STATUS(ddr3_tip_if_write 643 (dev_num, access_type, interface_num, 644 ODPG_WR_RD_MODE_ENA_REG, reg_data, 645 MASK_ALL_BITS)); ** CID 457896: Integer handling issues (INTEGER_OVERFLOW) /plat/mediatek/mt8183/drivers/devapc/devapc.c: 69 in set_master_domain_remap_infra() ________________________________________________________________________________________________________ *** CID 457896: Integer handling issues (INTEGER_OVERFLOW) /plat/mediatek/mt8183/drivers/devapc/devapc.c: 69 in set_master_domain_remap_infra() 63 domain_emi_view = domain_emi_view - DOMAIN_11; 64 clr_bit = 0x7 << (domain_emi_view * 3 + 1); 65 set_bit = domain_infra_view << (domain_emi_view * 3 + 1); 66 mmio_clrsetbits_32(base, clr_bit, set_bit); 67 } else { 68 base = DEVAPC_INFRA_DOM_RMP_0; >>> CID 457896: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "clr_bit", where "3 << domain_emi_view * 3U" is known to be equal to -1073741824, overflows the type of "clr_bit", which is type "uint32_t". 69 clr_bit = 0x3 << (domain_emi_view * 3); 70 set_bit = domain_infra_view << (domain_emi_view * 3); 71 mmio_clrsetbits_32(base, clr_bit, set_bit); 72 73 base = DEVAPC_INFRA_DOM_RMP_1; 74 set_bit = (domain_infra_view & 0x4) >> 2; ** CID 457895: (DEADCODE) /drivers/nxp/ddr/phy-gen2/phy.c: 296 in get_cdd_val() /drivers/nxp/ddr/phy-gen2/phy.c: 241 in get_cdd_val() /drivers/nxp/ddr/phy-gen2/phy.c: 270 in get_cdd_val() ________________________________________________________________________________________________________ *** CID 457895: (DEADCODE) /drivers/nxp/ddr/phy-gen2/phy.c: 296 in get_cdd_val() 290 } 291 292 tmp = rwmax; 293 c = &cdd[25]; 294 rwmax = findmax(c, 16U); 295 if (tmp > rwmax) { >>> CID 457895: (DEADCODE) >>> Execution cannot reach this statement: "rwmax = tmp;". 296 rwmax = tmp; 297 } 298 299 wrmax = wwmax; 300 301 break; /drivers/nxp/ddr/phy-gen2/phy.c: 241 in get_cdd_val() 235 236 switch (rank) { 237 case 1U: 238 tmp = rwmax; 239 rwmax = cdd[40]; 240 if (tmp > rwmax) { >>> CID 457895: (DEADCODE) >>> Execution cannot reach this statement: "rwmax = tmp;". 241 rwmax = tmp; 242 } 243 244 break; 245 246 case 2U: /drivers/nxp/ddr/phy-gen2/phy.c: 270 in get_cdd_val() 264 buf[1] = cdd[39]; 265 buf[2] = cdd[36]; 266 buf[3] = cdd[35]; 267 tmp = rwmax; 268 rwmax = findmax(buf, 4U); 269 if (tmp > rwmax) { >>> CID 457895: (DEADCODE) >>> Execution cannot reach this statement: "rwmax = tmp;". 270 rwmax = tmp; 271 } 272 273 wrmax = wwmax; 274 275 break; ** CID 457894: Integer handling issues (INTEGER_OVERFLOW) /lib/libc/strtol.c: 127 in strtol() ________________________________________________________________________________________________________ *** CID 457894: Integer handling issues (INTEGER_OVERFLOW) /lib/libc/strtol.c: 127 in strtol() 121 any = 1; 122 acc *= base; 123 acc += c; 124 } 125 } 126 if (any < 0) { >>> CID 457894: Integer handling issues (INTEGER_OVERFLOW) >>> Expression "acc", where "neg ? -9223372036854775808L : 9223372036854775807L" is known to be equal to -9223372036854775808, underflows the type of "acc", which is type "unsigned long". 127 acc = neg ? LONG_MIN : LONG_MAX; 128 } else if (neg) 129 acc = -acc; 130 if (endptr != NULL) 131 *endptr = (char *)(any ? s - 1 : nptr); 132 return (acc); ** CID 457893: (INTEGER_OVERFLOW) /plat/rockchip/rk3399/drivers/dram/dfs.c: 973 in gen_rk3399_ctl_params_f1() /plat/rockchip/rk3399/drivers/dram/dfs.c: 976 in gen_rk3399_ctl_params_f1() ________________________________________________________________________________________________________ *** CID 457893: (INTEGER_OVERFLOW) /plat/rockchip/rk3399/drivers/dram/dfs.c: 973 in gen_rk3399_ctl_params_f1() 967 tmp = 0; 968 else if (tmp1 < 5) 969 tmp = tmp1 - 1; 970 else 971 tmp = tmp1 - 5; 972 } else { >>> CID 457893: (INTEGER_OVERFLOW) >>> Expression "tmp1 - 2U", where "tmp1" is known to be equal to 0, underflows the type of "tmp1 - 2U", which is type "unsigned int". 973 tmp = tmp1 - 2; 974 } 975 976 mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24); 977 978 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ /plat/rockchip/rk3399/drivers/dram/dfs.c: 976 in gen_rk3399_ctl_params_f1() 970 else 971 tmp = tmp1 - 5; 972 } else { 973 tmp = tmp1 - 2; 974 } 975 >>> CID 457893: (INTEGER_OVERFLOW) >>> Expression "tmp << 24", where "tmp" is known to be equal to 4294967294, overflows the type of "tmp << 24", which is type "uint32_t". 976 mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24); 977 978 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 979 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 980 (pdram_timing->cl >= 5)) 981 tmp = pdram_timing->cl - 5; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/arm-software-arm-trusted-firmware?tab=ov…

12 months

2
1
0 0

Canceled event with note: TF-A Tech Forum @ Thu Mar 20, 2025 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling as no topic proposed. Regards, Olivier. " TF-A Tech Forum Thursday Mar 20, 2025 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

12 months

1
0
0 0

Coverity scan infra

by Bollapalli, Maheedhar Sai

[AMD Official Use Only - AMD Internal Distribution Only] Hi TF-A Team, With our internal Coverity infrastructure we are seeing multiple MISRA C issues reported (enforced) for transfer-list, while TF-A upstream CI pipeline reports only subset of those violation issues. Could you please share Coverity configuration used in TF-A upstream CI pipeline ? Regards, Maheedhar.

12 months

3
3
0 0

Canceled event with note: TF-A Tech Forum @ Thu Mar 6, 2025 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling as no topic proposed. Regards, Olivier. " TF-A Tech Forum Thursday Mar 6, 2025 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year

1
0
0 0

Trusted Firmware-A LTS v2.10.14 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.14 is now available. This release contains the following patches: 926f86bac refactor(build): allow mandatory feats disabling [1] 48b41b441 refactor(build): refactor mandatory options [2] eb26e7855 fix(build): march handling with arch-features [3] 9e469a880 refactor(build): remove enabling feat [4] f0d197618 refactor(build): minor updates [5] c7d9465b9 feat(trbe): introduce trbe_disable() function [6] b9e252aee feat(cpus): add ENABLE_ERRATA_ALL flag [7] [1] https://review.trustedfirmware.org/q/I6fdca1a3d0b405a88cd7a20309e0c1eecd57a… [2] https://review.trustedfirmware.org/q/I8b0dd076c168a647de43b8618fbbe607412f7… [3] https://review.trustedfirmware.org/q/Ifaf99af5f371fd28db376a12657ccf4f36329… [4] https://review.trustedfirmware.org/q/I8565ac4ebb3ced29835be65ea5b043a088108… [5] https://review.trustedfirmware.org/q/I12a4940e82ca5df72af5421ddab43bc6a1628… [6] https://review.trustedfirmware.org/q/If3e3bd621684b3c28f44c3ed2fe3df30b143f… [7] https://review.trustedfirmware.org/q/I2b456d304d7bf3215c7c4f4fd70b56ecbcb09… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.14/change-log.html Thanks, TF-A LTS team

1 year

1
0
0 0

Trusted Firmware-A LTS v2.12.1 Release Announcement

by ci_notify＠trustedfirmware.org

1 year

1
0
0 0

Trusted Firmware-A LTS v2.12.0 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.12.0 is now available. This release contains the following patches: Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.0/change-log.html Thanks, TF-A LTS team

1 year

1
0
0 0

Trusted Firmware-A LTS v2.12.1 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.12.1 is now available. This release contains the following patches: Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.12.1/change-log.html Thanks, TF-A LTS team

1 year

1
0
0 0

Trusted Firmware-A LTS v2.8.30 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.30 is now available. This release contains the following patches: 983f4c8ed chore(cpus): fix incorrect header macro [1] 1a2a26897 refactor(errata-abi): move EXTRACT_PARTNUM to arch.h [2] 37db9abef refactor(cm): move remaining EL2 save/restore into C [3] f2a263ed8 fix(cm): update gic el2 sysregs save/restore mechanism [4] 8c6068fab fix(cpus): workaround for accessing ICH_VMCR_EL2 [5] c32e3a38d fix(cpus): workaround for Cortex-A710 erratum 3701772 [6] 3b8a3ad15 fix(cpus): workaround for Cortex-A715 erratum 3699560 [7] c7d5de9fe fix(cpus): workaround for Cortex-A720 erratum 3699561 [8] 2296df6fe fix(cpus): workaround for Cortex-X2 erratum 3701772 [9] ed4bd3c61 fix(cpus): workaround for Cortex-X3 erratum 3701769 [10] 395f67e87 fix(cpus): workaround for Cortex-X4 erratum 3701758 [11] 2414a852a fix(cpus): workaround for Neoverse-N2 erratum 3701773 [12] 35caff979 fix(cpus): workaround for Neoverse-V3 erratum 3701767 [13] 55589ce29 chore(smccc): bump up SMCCC version to 1.4 [14] [1] https://review.trustedfirmware.org/q/I6a4a8ec6546adb41e24d8885cb445fa8be830… [2] https://review.trustedfirmware.org/q/Id8bbaf21566f3145a75cfa0dafec6823ed2df… [3] https://review.trustedfirmware.org/q/If690f792e70b97fd4b4cd5f43847a71719b12… [4] https://review.trustedfirmware.org/q/I8d55c3dc6a17c4749748822d4a738912c1e13… [5] https://review.trustedfirmware.org/q/I9f0403601c6346276e925f02eab55908b009d… [6] https://review.trustedfirmware.org/q/I997c9cfaa75321f22b4f690c4d3f234c0b51c… [7] https://review.trustedfirmware.org/q/I183aa921b4b6f715d64eb6b70809de2566017… [8] https://review.trustedfirmware.org/q/I7ea3aaf3e7bf6b4f3648f6872e505a41247b1… [9] https://review.trustedfirmware.org/q/I2ffc5e7d7467f1bcff8b895fea52a1daa7d14… [10] https://review.trustedfirmware.org/q/Ifd722e1bb8616ada2ad158297a7ca80b19a33… [11] https://review.trustedfirmware.org/q/I4ee941d1e7653de7a12d69f538ca05f7f9f99… [12] https://review.trustedfirmware.org/q/If95bd67363228c8083724b31f630636fb27f3… [13] https://review.trustedfirmware.org/q/I5be0de881f408a9e82a07b8459d79490e9065… [14] https://review.trustedfirmware.org/q/Ie5476c4601bd504d3f3e8433e1d672ebd0a75… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.30/change-log.html Thanks, TF-A LTS team

1 year

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu Feb 20, 2025 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, No topic planned for today. Thanks & Regards, Olivier." TF-A Tech Forum Thursday Feb 20, 2025 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year

1
0
0 0

Trusted Firmware-A LTS v2.10.13 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.13 is now available. This release contains the following patches: b2be8b051 fix(security): enable WORKAROUND_CVE_2024_7881 build option [1] 8618e9d8f fix(security): add CVE-2024-7881 mitigation to Cortex-X4 [2] 81476ada1 fix(security): add CVE-2024-7881 mitigation to Cortex-X925 [3] 6caef6a1f fix(security): add CVE-2024-7881 mitigation to Neoverse-V2 [4] a7371652e fix(security): add CVE-2024-7881 mitigation to Neoverse-V3 [5] 023e80d4c fix(security): add CVE-2024-7881 mitigation to Cortex-X3 [6] b5386661a fix(security): add support in cpu_ops for CVE-2024-7881 [7] 64618d664 fix(security): apply SMCCC_ARCH_WORKAROUND_4 to affected cpus [8] f823cc74e fix(cm): update gic el2 sysregs save/restore mechanism [9] 053bdc35f refactor(fvp): move cpus with nomodel [10] 813f66774 chore: rename hermes to neoverse-n3 [11] 86b37315e chore(cpus): fix incorrect header macro [12] 57ab066a2 refactor(errata-abi): move EXTRACT_PARTNUM to arch.h [13] 57bdc57e3 fix(cpus): workaround for accessing ICH_VMCR_EL2 [14] 8f709377f fix(cpus): workaround for Cortex-A710 erratum 3701772 [15] 857cfc2e9 fix(cpus): workaround for Cortex-A715 erratum 3699560 [16] 36b53f90f fix(cpus): workaround for Cortex-A720 erratum 3699561 [17] 17b8a8a33 fix(cpus): workaround for Cortex-A725 erratum 3699564 [18] 3e9433d76 fix(cpus): workaround for Cortex-X2 erratum 3701772 [19] 1852f608b fix(cpus): workaround for Cortex-X3 erratum 3701769 [20] db3048d54 fix(cpus): workaround for Cortex-X4 erratum 3701758 [21] c8a6cc0a1 fix(cpus): workaround for Cortex-X925 erratum 3701747 [22] 1d17578bd fix(cpus): workaround for Neoverse-N2 erratum 3701773 [23] e2a5da1c0 fix(cpus): workaround for Neoverse-N3 erratum 3699563 [24] fc497736f fix(cpus): workaround for Neoverse-V3 erratum 3701767 [25] [1] https://review.trustedfirmware.org/q/Id77f82a4dfaa4422729f7e3f2429f47cc90d9… [2] https://review.trustedfirmware.org/q/I0bec96d4f71a08a89c6612e272ecfb173f80d… [3] https://review.trustedfirmware.org/q/I53e72e4dbc8937cea3c344a5ba04664c50a07… [4] https://review.trustedfirmware.org/q/I129814eb3494b287fd76a3f7dbc50f76553b2… [5] https://review.trustedfirmware.org/q/Ib5c644895b8c76d3c7e8b5e6e98d7b9afef7f… [6] https://review.trustedfirmware.org/q/I410517d175a80fc6f459fa6ce5c30c0a38db9… [7] https://review.trustedfirmware.org/q/I417389f040c6ead7f96f9b720d29061833f43… [8] https://review.trustedfirmware.org/q/I1b1ffaa1f806f07472fd79d5525f81764d99b… [9] https://review.trustedfirmware.org/q/I8d55c3dc6a17c4749748822d4a738912c1e13… [10] https://review.trustedfirmware.org/q/I3da12d2f8d9c246b435b31adfac61c79dc1ab… [11] https://review.trustedfirmware.org/q/I912d4c824c5004a8c1909c68fef77f1f5e202… [12] https://review.trustedfirmware.org/q/I6a4a8ec6546adb41e24d8885cb445fa8be830… [13] https://review.trustedfirmware.org/q/Id8bbaf21566f3145a75cfa0dafec6823ed2df… [14] https://review.trustedfirmware.org/q/I9f0403601c6346276e925f02eab55908b009d… [15] https://review.trustedfirmware.org/q/I997c9cfaa75321f22b4f690c4d3f234c0b51c… [16] https://review.trustedfirmware.org/q/I183aa921b4b6f715d64eb6b70809de2566017… [17] https://review.trustedfirmware.org/q/I7ea3aaf3e7bf6b4f3648f6872e505a41247b1… [18] https://review.trustedfirmware.org/q/Ifad1f6c3f5b74060273f897eb5e4b79dd9f08… [19] https://review.trustedfirmware.org/q/I2ffc5e7d7467f1bcff8b895fea52a1daa7d14… [20] https://review.trustedfirmware.org/q/Ifd722e1bb8616ada2ad158297a7ca80b19a33… [21] https://review.trustedfirmware.org/q/I4ee941d1e7653de7a12d69f538ca05f7f9f99… [22] https://review.trustedfirmware.org/q/I080296666f89276b3260686c2bdb8de63fc17… [23] https://review.trustedfirmware.org/q/If95bd67363228c8083724b31f630636fb27f3… [24] https://review.trustedfirmware.org/q/I77aaf8ae0afff3adde9a85f4a1a13ac9d1daf… [25] https://review.trustedfirmware.org/q/I5be0de881f408a9e82a07b8459d79490e9065… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.13/change-log.html Thanks, TF-A LTS team

1 year

1
0
0 0

Trusted Firmware-A LTS v2.8.29 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.29 is now available. This release contains the following patches: 772bdd3bc style: normalize linker script code style [1] cf5e7d8d4 build: always prefix section names with `.` [2] e2084abfc fix(services): disable workaround discovery on aarch32 for now [3] cc04eac23 fix(security): enable WORKAROUND_CVE_2024_7881 build option [4] 2ef768d4a fix(security): add CVE-2024-7881 mitigation to Cortex-X4 [5] 172ccad6a fix(security): add CVE-2024-7881 mitigation to Neoverse-V2 [6] cbf4a4e3c fix(security): add CVE-2024-7881 mitigation to Neoverse-V3 [7] a7f53d34f fix(security): add CVE-2024-7881 mitigation to Cortex-X3 [8] 8fc0fa7c0 fix(security): add support in cpu_ops for CVE-2024-7881 [9] 337aa3bf1 fix(security): apply SMCCC_ARCH_WORKAROUND_4 to affected cpus [10] 1e4b43644 feat(fvp): allow configurable FVP Trusted SRAM size [11] [1] https://review.trustedfirmware.org/q/Ibee2afad0d543129c9ba5a8a22e3ec17d77e3… [2] https://review.trustedfirmware.org/q/I51c13c5266d5975fbd944ef4961328e72f82f… [3] https://review.trustedfirmware.org/q/Ic19973a8e4d50a97f274d4461794c117b3373… [4] https://review.trustedfirmware.org/q/Id77f82a4dfaa4422729f7e3f2429f47cc90d9… [5] https://review.trustedfirmware.org/q/I0bec96d4f71a08a89c6612e272ecfb173f80d… [6] https://review.trustedfirmware.org/q/I129814eb3494b287fd76a3f7dbc50f76553b2… [7] https://review.trustedfirmware.org/q/Ib5c644895b8c76d3c7e8b5e6e98d7b9afef7f… [8] https://review.trustedfirmware.org/q/I410517d175a80fc6f459fa6ce5c30c0a38db9… [9] https://review.trustedfirmware.org/q/I417389f040c6ead7f96f9b720d29061833f43… [10] https://review.trustedfirmware.org/q/I1b1ffaa1f806f07472fd79d5525f81764d99b… [11] https://review.trustedfirmware.org/q/I8344d3718564cd2bd53f1e6860e2fe341ae24… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.29/change-log.html Thanks, TF-A LTS team

1 year

1
0
0 0

TBBR: Question about the available Non Volatile Counters

by Rares Constantin

Hi, I have a question regarding the TBBR implementation for non-volatile counters in TF-A. While looking through the code and documentation for Trusted Boot authentication options, it was not clear why there are only two non-volatile counters for the Trusted and Non-Trusted worlds (`TRUSTED_FW_NVCOUNTER` and `NON_TRUSTED_FW_NVCOUNTER`). This is true for the Arm DEN0006D specification, but it was retired and ARM DEN0072 is the current specification. Is there any specific reason why there isn't a counter for each authenticated image declared and created by `cert_create` or is the retired specification the only reason? This limits the non-volatile counter extensions for all certificates, meaning that the Trusted OS content certificate for example cannot be authenticated with another extension, unless I add a custom certificate with another non-volatile counter extension and a new command line option. To quote the ARM DEN0072 TBBR specification [source: https://developer.arm.com/documentation/den0072/latest]: "It is recommended to implement as many version counters as there are images, where each image can use a separate counter without affecting other images. However, the number of rollback counters that can practically be supported is implementation dependent.". Thank you!

1 year, 1 month

2
3
0 0

Canceled event with note: TF-A Tech Forum @ Thu Feb 6, 2025 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling as no topic proposed this week. Regards, Olivier. " TF-A Tech Forum Thursday Feb 6, 2025 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 1 month

1
0
0 0

Trusted Firmware-A LTS v2.8.28 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.28 is now available. This release contains the following patches: d4ce532c6 fix(arm): add extra hash config to validate ROTPK [1] 0f7eed07d refactor(mbedtls): rename default mbedtls confs [2] ae45ec9d4 docs(prerequisites): update mbedtls to version 3.6.2 [3] 8c37a4b7f feat(mbedtls): mbedtls config update for v3.6.2 [4] bf358fef7 docs: add inital lts doc [5] 633fc7323 docs: updates to LTS [6] 0330b630a chore(deps): bump jinja2 in the pip group across 1 directory [7] b3d5cc387 chore(deps): bump cross-spawn [8] 2c6035419 docs(maintainers): update LTS maintainers [9] [1] https://review.trustedfirmware.org/q/Ib3128ce7b0fb5c0858624ecbc998d456968be… [2] https://review.trustedfirmware.org/q/I1f665c2471877ecc833270c511749ff845046… [3] https://review.trustedfirmware.org/q/Ibc4a8712c92019648fe0e75390cd3540d86b7… [4] https://review.trustedfirmware.org/q/I79027f6c741ab3f419f7b555321507e6a78b9… [5] https://review.trustedfirmware.org/q/I1434c29f0236161d2a127596e2cc528bf4cc3… [6] https://review.trustedfirmware.org/q/Iafc606a66ea3ea69c51b433867b5025b8debe… [7] https://review.trustedfirmware.org/q/I4502ed17a6ce37f53ac64370a5d7fe756875f… [8] https://review.trustedfirmware.org/q/I78624d7ef8c3842a2271d091bf2d3213d9455… [9] https://review.trustedfirmware.org/q/Ibf087c6b0e24d6faa9dafb6f8a0955a47f583… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.28/change-log.html Thanks, TF-A LTS team

1 year, 1 month

1
0
0 0

Trusted Firmware-A LTS v2.10.12 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.12 is now available. This release contains the following patches: 8b2c88573 fix(arm): add extra hash config to validate ROTPK [1] 0ac65e7aa refactor(mbedtls): rename default mbedtls confs [2] 44161dcb1 docs(prerequisites): update mbedtls to version 3.6.2 [3] 564922601 feat(mbedtls): mbedtls config update for v3.6.2 [4] 13657a3f3 docs: add inital lts doc [5] 3d85a19f2 docs: updates to LTS [6] 7c8c034e5 chore(deps): bump jinja2 in the pip group across 1 directory [7] 924c7f42c chore(deps): bump cross-spawn [8] 8355ef772 docs(maintainers): update LTS maintainers [9] [1] https://review.trustedfirmware.org/q/Ib3128ce7b0fb5c0858624ecbc998d456968be… [2] https://review.trustedfirmware.org/q/I1f665c2471877ecc833270c511749ff845046… [3] https://review.trustedfirmware.org/q/Ibc4a8712c92019648fe0e75390cd3540d86b7… [4] https://review.trustedfirmware.org/q/I79027f6c741ab3f419f7b555321507e6a78b9… [5] https://review.trustedfirmware.org/q/I1434c29f0236161d2a127596e2cc528bf4cc3… [6] https://review.trustedfirmware.org/q/Iafc606a66ea3ea69c51b433867b5025b8debe… [7] https://review.trustedfirmware.org/q/I4502ed17a6ce37f53ac64370a5d7fe756875f… [8] https://review.trustedfirmware.org/q/I78624d7ef8c3842a2271d091bf2d3213d9455… [9] https://review.trustedfirmware.org/q/Ibf087c6b0e24d6faa9dafb6f8a0955a47f583… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.12/change-log.html Thanks, TF-A LTS team

1 year, 1 month

1
0
0 0

question about encryption

by 林觀明

Hi I tried to turn on encryption in BL31. And, I met some trouble. Here is my code. ``` static struct plat_io_policy policies[] = { ... [BL31_IMAGE_ID] = {&enc_dev_handle, &bl31_uuid_spec, check_enc_fip}, .... [ENC_IMAGE_ID] = {&fip_dev_handle, NULL, check_fip} } int plat_get_image_source(...) { ... policy = &policies[image_id]; ret = policy->check[policy->image_spec]; ... } static int check_fip(const uintptr_t spec) { int ret; ret = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle); if (ret) { ERROR("io_dev_open failed for FIP (%d)\n", ret); return ret; } ret = io_dev_init(fip_dev_handle, fip_image_id); if (ret) { ERROR("io_dev_init failed for FIP image id %lu (%d)\n", fip_image_id, ret); io_dev_close(fip_dev_handle); } return ret; } static int check_enc_fip(const uintptr_t spec) { int result; uintptr_t local_image_handle; /* See if a Firmware Image Package is available */ result = io_dev_open(enc_dev_con, (uintptr_t)NULL, &enc_dev_handle); if (result) { ERROR("io_dev_open failed for FIP (%d)\n", result); return result; } result = io_dev_init(enc_dev_handle, (uintptr_t)ENC_IMAGE_ID); if (result != 0) return result; return result; } ``` But, I can't boot successfully. Below is log. ``` INFO: Image id=3 loaded: 0x40800000 - 0x4080e299 INFO: BL2: Loading image id 5 WARNING: ===== allocate_dev_info 1 ===== WARNING: ==== -12 ==== ERROR: io_dev_open failed for FIP (-12) ERROR: Image id 11 open failed with -12 WARNING: Failed to obtain reference to image id=11 (-12) ERROR: BL2: Failed to load image id 5 (-12) ``` And, I found root cause in `allocate_dev_info` and `free_dev_info` in `drivers/io/io_fip.c` In `allocate_dev_info`, there is a count, `fip_dev_count`, increasing by 1 after calling `fip_dev_open` There is a check. The value of MAX_FIP_DEVICES is 1. ``` if (fip_dev_count < (unsigned int)MAX_FIP_DEVICES) { unsigned int index = 0; result = find_first_fip_state(0, &index); assert(result == 0); /* initialize dev_info */ dev_info_pool[index].funcs = &fip_dev_funcs; dev_info_pool[index].info = (uintptr_t)&state_pool[index]; *dev_info = &dev_info_pool[index]; ++fip_dev_count; } ``` And, in `fip_dev_close`, The `fip_dev_count` will be decreased by 1. However, The root casue is it call fip_dev_open but not calling fip_dev_close. It cause the `fip_dev_count` not be decreased by 1. Now, I have two solution. 1. Increasing the MAX_FIP_DEVICES, it will be working. 2. Add the io_dev_close in `enc_dev_close` in `driver/io_/io_encrypted.c`. And, it will call the fip_dev_close. It will be working. Do you have any idea in this solution ? Which solution is more general ? Thanks !

1 year, 1 month

2
1
0 0

TF-A Tech Forum - Jan 23rd 2025 - RMM design of EL0 applications support

by Olivier Deprez

Hi, On Jan 23rd 2025, in the TF-A Tech forum, Mate Toth-Pal and Soby Mathew will present the RMM design of EL0 applications support. The TF-A Tech forum is a regular open forum for anyone from the open source community to participate. Feel free to reach if you have a topic you'd want to present. It can be a design review with slides, walking through RFC patches, or more generic discussion around open source projects. Regards, Olivier. TF-A Tech Forum Thursday Jan 23, 2025 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org

1 year, 1 month

1
0
0 0

Trusted Firmware-A LTS v2.8.27 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.27 is now available. This release contains the following patches: 03d2ef8b0 fix(cpus): workaround for CVE-2024-5660 for Cortex-X4 [1] 85b4f4595 fix(cpus): workaround for CVE-2024-5660 for Neoverse-V3 [2] 9761fcc4d fix(cpus): workaround for CVE-2024-5660 for Cortex-X3 [3] cfa1200ff fix(cpus): workaround for CVE-2024-5660 for Neoverse-V2 [4] 5625d9e28 fix(cpus): workaround for CVE-2024-5660 for Cortex-A710 [5] ca1a7aaf7 fix(cpus): workaround for CVE-2024-5660 for Neoverse-N2 [6] feb80a641 fix(cpus): workaround for CVE-2024-5660 for Cortex-X1 [7] de65c9fc4 fix(cpus): workaround for CVE-2024-5660 for Cortex-A78 [8] d87e44989 fix(cpus): workaround for CVE-2024-5660 for Cortex-A78C [9] 5e9988827 fix(cpus): workaround for CVE-2024-5660 for Cortex-A78_AE [10] ba5453ca4 fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1 [11] 1f48d849e fix(cpus): workaround for CVE-2024-5660 for Cortex-A77 [12] 07a4df505 fix(cpus): workaround for CVE-2024-5660 for Cortex-X2 [13] 9f342211f chore(cpus): optimise runtime errata applications [14] 3edd92a1f fix(cpus): workaround for Cortex-X4 erratum 2923985 [15] [1] https://review.trustedfirmware.org/q/I378cb4978919cced03e7febc2ad431c572eac… [2] https://review.trustedfirmware.org/q/I9ed2590bf1215bf6a692f01dfd351e469ff07… [3] https://review.trustedfirmware.org/q/Ibe90313948102ece3469f2cfe3faccc7f4bee… [4] https://review.trustedfirmware.org/q/If66687add52d16f68ce54fe5433dd3b3f067e… [5] https://review.trustedfirmware.org/q/I10feea238600dcceaac7bb75a59db7913ca65… [6] https://review.trustedfirmware.org/q/I2b9dea78771cc159586a03ff563c0ec79591e… [7] https://review.trustedfirmware.org/q/I3124db3980f2786412369a010ca6abbbbaa3b… [8] https://review.trustedfirmware.org/q/I4e40388bef814481943b2459fe35dd7267c62… [9] https://review.trustedfirmware.org/q/Ieb8d7b122320d16bf8987a43dc683ca41227b… [10] https://review.trustedfirmware.org/q/I33ac653fcb45f687fe9ace1c76a3eb2000459… [11] https://review.trustedfirmware.org/q/Ia59452ea38c66b291790956d7f2880bfcd56d… [12] https://review.trustedfirmware.org/q/Ic71b163883ea624e9f2f77deb8b30c6961293… [13] https://review.trustedfirmware.org/q/If28804e154617a39d7d52c40b3a00a14a39df… [14] https://review.trustedfirmware.org/q/I02f9dd7d0619feb54c870938ea186be5e3a6c… [15] https://review.trustedfirmware.org/q/I9207802ad479919a7f77c1271019fa2479e07… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.27/change-log.html Thanks, TF-A LTS team

1 year, 2 months

1
0
0 0

Trusted Firmware-A LTS v2.10.11 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.11 is now available. This release contains the following patches: 96498991d chore: rename Chaberton to Cortex-A725 [1] b229b47bd chore: rename Blackhawk to Cortex-X925 [2] 698e68fe1 fix(cpus): workaround for CVE-2024-5660 for Cortex-X925 [3] e42abf298 fix(cpus): workaround for CVE-2024-5660 for Cortex-X4 [4] a6375e1fe fix(cpus): workaround for CVE-2024-5660 for Neoverse-V3 [5] 17e17ed3f fix(cpus): workaround for CVE-2024-5660 for Cortex-X3 [6] 3efc9e130 fix(cpus): workaround for CVE-2024-5660 for Neoverse-V2 [7] f7ae819f0 fix(cpus): workaround for CVE-2024-5660 for Cortex-A710 [8] 282e63544 fix(cpus): workaround for CVE-2024-5660 for Neoverse-N2 [9] c7d3c9eb2 fix(cpus): workaround for CVE-2024-5660 for Cortex-X1 [10] 30c57c58a fix(cpus): workaround for CVE-2024-5660 for Cortex-A78 [11] 87250d2bb fix(cpus): workaround for CVE-2024-5660 for Cortex-A78C [12] a02a863d3 fix(cpus): workaround for CVE-2024-5660 for Cortex-A78_AE [13] 4fd2a6702 fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1 [14] 5673d345a fix(cpus): workaround for CVE-2024-5660 for Cortex-A77 [15] ad9dfdc58 fix(cpus): workaround for CVE-2024-5660 for Cortex-X2 [16] 0eed05ee7 chore(cpus): optimise runtime errata applications [17] 196984e65 fix(cpus): workaround for Cortex-X4 erratum 2923985 [18] [1] https://review.trustedfirmware.org/q/I981b22d3b37f1aa6e25ff1f35aa156fff9c30… [2] https://review.trustedfirmware.org/q/I51e40a7bc6b8871c53c40d1f341853b1fd7fd… [3] https://review.trustedfirmware.org/q/I9d5a07ca6b89b27d8876f4349eff2af26c962… [4] https://review.trustedfirmware.org/q/I378cb4978919cced03e7febc2ad431c572eac… [5] https://review.trustedfirmware.org/q/I9ed2590bf1215bf6a692f01dfd351e469ff07… [6] https://review.trustedfirmware.org/q/Ibe90313948102ece3469f2cfe3faccc7f4bee… [7] https://review.trustedfirmware.org/q/If66687add52d16f68ce54fe5433dd3b3f067e… [8] https://review.trustedfirmware.org/q/I10feea238600dcceaac7bb75a59db7913ca65… [9] https://review.trustedfirmware.org/q/I2b9dea78771cc159586a03ff563c0ec79591e… [10] https://review.trustedfirmware.org/q/I3124db3980f2786412369a010ca6abbbbaa3b… [11] https://review.trustedfirmware.org/q/I4e40388bef814481943b2459fe35dd7267c62… [12] https://review.trustedfirmware.org/q/Ieb8d7b122320d16bf8987a43dc683ca41227b… [13] https://review.trustedfirmware.org/q/I33ac653fcb45f687fe9ace1c76a3eb2000459… [14] https://review.trustedfirmware.org/q/Ia59452ea38c66b291790956d7f2880bfcd56d… [15] https://review.trustedfirmware.org/q/Ic71b163883ea624e9f2f77deb8b30c6961293… [16] https://review.trustedfirmware.org/q/If28804e154617a39d7d52c40b3a00a14a39df… [17] https://review.trustedfirmware.org/q/I02f9dd7d0619feb54c870938ea186be5e3a6c… [18] https://review.trustedfirmware.org/q/I9207802ad479919a7f77c1271019fa2479e07… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.11/change-log.html Thanks, TF-A LTS team

1 year, 2 months

1
0
0 0

Canceled event with note: TF-A Tech Forum @ Thu Jan 9, 2025 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, No topic planned for this week. Regards, Olivier. " TF-A Tech Forum Thursday Jan 9, 2025 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 2 months

1
0
0 0

Re: Linker errors with ENABLE_LTO and LD overriding

by Bollapalli, Maheedhar Sai

Hi, Adding further details: build command, error log and linker version. Build command : make -j12 CC=aarch64-none-elf-gcc LD=aarch64-none-elf-ld CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 ZYNQMP_CONSOLE=dtb bl31 Error Log: usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: build/zynqmp/debug/bl31/bl31_entrypoint.o: in function `bl31_entrypoint': bl31/aarch64/bl31_entrypoint.S:79:(.text.asm.bl31_entrypoint+0x108): undefined reference to `bl31_setup' bl31/aarch64/bl31_entrypoint.S:93:(.text.asm.bl31_entrypoint+0x10c): undefined reference to `bl31_main' build/zynqmp/debug/bl31/cpu_data.o: in function `_cpu_data_by_index': lib/el3_runtime/aarch64/cpu_data.S:44:(.text.asm._cpu_data_by_index+0x8): undefined reference to `percpu_data' usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: lib/el3_runtime/aarch64/cpu_data.S:45:(.text.asm._cpu_data_by_index+0xc): undefined reference to `percpu_data' usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: build/zynqmp/debug/bl31/context.o: in function `el3_exit': arm-trusted-firmware$ aarch64-none-elf-ld --version GNU ld (GNU Binutils) 2.42.0.20240620 arm-trusted-firmware$ aarch64-none-elf-gcc --version aarch64-xilinx-elf-gcc.real (GCC) 13.3.0 Regards, Maheedhar.

1 year, 2 months

3
4
0 0

Erratum 1530924 handling

by Bollapalli, Maheedhar Sai

Hi, On AMD-Xilinx ZynqMP platform there is a erratum (1530924) which is mentioned as applied as shown in the log below: " INFO: BL31: cortex_a53: CPU workaround for erratum 1530924 was applied " Refer to the code comments mentioned below, there is no "erratum has no workaround in the CPU. Generic code must take care " https://gitenterprise.xilinx.com/Linux/arm-trusted-firmware/blob/master/lib… However, we found no handling in the generic code either. Can we be guided further regarding the handling of erratum 1530924 ? Regards, Maheedhar.

1 year, 2 months

2
2
0 0

Canceled event: TF-A Tech Forum @ Thu Dec 26, 2024 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled. TF-A Tech Forum Thursday Dec 26, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 2 months

1
0
0 0

Re: Query regarding the test coverage thru tf-a-tests

by Nagal, Amit

Hi , I am referring to the code coverage as below : https://ci-builds.trustedfirmware.org/static-files/htxSEy4sEOQXtuGetFtzHqAm… I see a lot of files from non plat code getting covered with code coverage . can somebody help me with further information : 1. Where are cputests related unit test scripts hosted for non plat files like bl31_main.c ? 2. can we use the unit test & code coverage infra for other platforms say AMD-Xilinx? 3. How is the code coverage achieved for assembly .S files like bl31_entrypoint.S ? Regards Amit From: Nagal, Amit Sent: Wednesday, December 11, 2024 1:23 PM To: Gyorgy Szing <Gyorgy.Szing(a)arm.com>; Mark Dykes <Mark.Dykes(a)arm.com>; Thangaraj, Senthil Nathan <SenthilNathan.Thangaraj(a)amd.com>; Olivier Deprez <Olivier.Deprez(a)arm.com>; tf-a-tests(a)lists.trustedfirmware.org; Joanna Farley <Joanna.Farley(a)arm.com> Cc: Jain, Ronak <ronak.jain(a)amd.com>; Simek, Michal <michal.simek(a)amd.com> Subject: RE: Query regarding the test coverage thru tf-a-tests Hi Everyone, I see very limited number of unit tests cpp files hosted at https://git.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-unit-tests/+/refs… Do we have more unit tests implemented for TF-A and available publicly anywhere ? Regards Amit From: Gyorgy Szing <Gyorgy.Szing(a)arm.com<mailto:Gyorgy.Szing@arm.com>> Sent: Wednesday, November 20, 2024 2:44 PM To: Nagal, Amit <amit.nagal(a)amd.com<mailto:amit.nagal@amd.com>>; Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com>>; Thangaraj, Senthil Nathan <SenthilNathan.Thangaraj(a)amd.com<mailto:SenthilNathan.Thangaraj@amd.com>>; Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com>>; tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org>; Joanna Farley <Joanna.Farley(a)arm.com<mailto:Joanna.Farley@arm.com>> Cc: Jain, Ronak <ronak.jain(a)amd.com<mailto:ronak.jain@amd.com>>; Simek, Michal <michal.simek(a)amd.com<mailto:michal.simek@amd.com>> Subject: Re: Query regarding the test coverage thru tf-a-tests Hi Amit, “can this be utilized to perform unit testing for platforms other than fvp” Unit-tests executables are running on the “build host” which often is the X86 based PC of the developer (or a CI worker). UT is favoring low cost and sacrificing some level of test correctness. It assumes the compiled C code is fully portable and works the same on all platforms. Moreover, it focuses on C function correctness, and checks if a specific function works as designed. Verifying higher level operation is out of scope (e.g. function implements any feature correctly or is behaving correctly when called by other functions in the system). In turn the complexity of embedded development is removed (managing the target, updating the firmware, using a JTAG interface for debugging, etc…), and the resource constraints of the embedded target is not present. The code coverage executed on the fvp platform is a system test, it exercises the product on an emulated target. It verifies the correctness of the code as it executes like it will in a real-world scenario. This is a higher value test, but it is much more expensive in terms of time and complexity than UT. “Is c-picker tool available inside arm still as of now ?” No, it is public, although it is a bit hidden. It lives on the c-picker branch to the Trusted Services repository (see [1) Similarly, Firmware Test Builder lives on the fwtb branch (see 2). This branch is independent of TS code and contains only the two tools. We have plans to move each to dedicated repositories, but I don’t know when I will have the time to do this. (FWTB and c-picker was developed by my team (TS) and is used and maintained by both projects. Before the TS project was started, we were working on TF-A. I can help with the tools, but I am not familiar to TF-A specifics like, how the tools are integrated to TF-A or which parts of TF-A are covered by UT cases.) 1: https://review.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/re… 2: https://review.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/re… /George On 2024-11-20, 06:05, "Nagal, Amit via TF-A-Tests" <tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org>> wrote: Hi Mark, From unit test prospective , I saw this document https://www.trustedfirmware.org/docs/TF-A-UnitLevelTesting.pdf. can this be utilized to perform unit testing for platforms other than fvp ? Is c-picker tool available inside arm still as of now ? Regards Amit From: Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com>> Sent: Tuesday, October 29, 2024 9:20 PM To: Nagal, Amit <amit.nagal(a)amd.com<mailto:amit.nagal@amd.com>>; Thangaraj, Senthil Nathan <SenthilNathan.Thangaraj(a)amd.com<mailto:SenthilNathan.Thangaraj@amd.com>>; Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com>>; tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org>; Joanna Farley <Joanna.Farley(a)arm.com<mailto:Joanna.Farley@arm.com>> Cc: Jain, Ronak <ronak.jain(a)amd.com<mailto:ronak.jain@amd.com>>; Simek, Michal <michal.simek(a)amd.com<mailto:michal.simek@amd.com>> Subject: Re: Query regarding the test coverage thru tf-a-tests Amit, It appears I was incorrect in getting coverage outside of the flows we have internally. I apologize for the confusion... Mark ________________________________ From: Nagal, Amit <amit.nagal(a)amd.com<mailto:amit.nagal@amd.com<mailto:amit.nagal@amd.com%3cmailto:amit.nagal@amd.com>>> Sent: Friday, October 25, 2024 12:07 AM To: Thangaraj, Senthil Nathan <SenthilNathan.Thangaraj(a)amd.com<mailto:SenthilNathan.Thangaraj@amd.com<mailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com>>>; Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com>>>; Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com>>>; tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>> <tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>>; Joanna Farley <Joanna.Farley(a)arm.com<mailto:Joanna.Farley@arm.com<mailto:Joanna.Farley@arm.com%3cmailto:Joanna.Farley@arm.com>>> Cc: Jain, Ronak <ronak.jain(a)amd.com<mailto:ronak.jain@amd.com<mailto:ronak.jain@amd.com%3cmailto:ronak.jain@amd.com>>>; Simek, Michal <michal.simek(a)amd.com<mailto:michal.simek@amd.com<mailto:michal.simek@amd.com%3cmailto:michal.simek@amd.com>>> Subject: RE: Query regarding the test coverage thru tf-a-tests Hi @Mark Dykes<mailto:Mark.Dykes@arm.com> , Can you please share insights about how to get coverage information using manual tests run for FVP platform . That will help us to atleast get the coverage information for non platform code ( we are interested for bl31) . Regards Amit From: Thangaraj, Senthil Nathan <SenthilNathan.Thangaraj(a)amd.com<mailto:SenthilNathan.Thangaraj@amd.com<mailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com>>> Sent: Tuesday, September 10, 2024 12:23 AM To: Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com>>>; Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com>>>; tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>; joanna.farley(a)arm.com<mailto:joanna.farley@arm.com<mailto:joanna.farley@arm.com%3cmailto:joanna.farley@arm.com>> Cc: Jain, Ronak <ronak.jain(a)amd.com<mailto:ronak.jain@amd.com<mailto:ronak.jain@amd.com%3cmailto:ronak.jain@amd.com>>>; Nagal, Amit <amit.nagal(a)amd.com<mailto:amit.nagal@amd.com<mailto:amit.nagal@amd.com%3cmailto:amit.nagal@amd.com>>>; Simek, Michal <michal.simek(a)amd.com<mailto:michal.simek@amd.com<mailto:michal.simek@amd.com%3cmailto:michal.simek@amd.com>>> Subject: RE: Query regarding the test coverage thru tf-a-tests Thank you Joanna and Mark, for your insights and response. I wasn’t aware that these tests are running on a Virtual Platform and that’s how the coverage is being measured. I’ll look into this further, decide how we want to integrate it into our project, and get back to you. I appreciate your help and support here. Best regards, Senthil From: Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com>>> Sent: Wednesday, August 28, 2024 9:03 AM To: Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com>>>; tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>; Thangaraj, Senthil Nathan <SenthilNathan.Thangaraj(a)amd.com<mailto:SenthilNathan.Thangaraj@amd.com<mailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com>>> Cc: Jain, Ronak <ronak.jain(a)amd.com<mailto:ronak.jain@amd.com<mailto:ronak.jain@amd.com%3cmailto:ronak.jain@amd.com>>>; Nagal, Amit <amit.nagal(a)amd.com<mailto:amit.nagal@amd.com<mailto:amit.nagal@amd.com%3cmailto:amit.nagal@amd.com>>>; Simek, Michal <michal.simek(a)amd.com<mailto:michal.simek@amd.com<mailto:michal.simek@amd.com%3cmailto:michal.simek@amd.com>>> Subject: RE: Query regarding the test coverage thru tf-a-tests Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding. Senthil, I do have a way to get coverage for manual test runs using FVP if that helps. I can assist if needed…. Mark From: Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com>>> Sent: Wednesday, August 28, 2024 12:53 AM To: Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com>>>; tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>; Thangaraj, Senthil Nathan <SenthilNathan.Thangaraj(a)amd.com<mailto:SenthilNathan.Thangaraj@amd.com<mailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com>>> Cc: Jain, Ronak <ronak.jain(a)amd.com<mailto:ronak.jain@amd.com<mailto:ronak.jain@amd.com%3cmailto:ronak.jain@amd.com>>>; Nagal, Amit <amit.nagal(a)amd.com<mailto:amit.nagal@amd.com<mailto:amit.nagal@amd.com%3cmailto:amit.nagal@amd.com>>>; Simek, Michal <michal.simek(a)amd.com<mailto:michal.simek@amd.com<mailto:michal.simek@amd.com%3cmailto:michal.simek@amd.com>>> Subject: Re: Query regarding the test coverage thru tf-a-tests Hi Senthil, * Is there a way to get code coverage for manual test runs? Sorry, I'm not aware of such capability. As you say code coverage implies use of CI scripting that isn't possible to reproduce locally out of the box (afaik). Regards, Olivier. ________________________________ From: Thangaraj, Senthil Nathan via TF-A-Tests <tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>> Sent: 26 August 2024 23:58 To: Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com>>>; Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com>>>; tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>> <tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>> Cc: Jain, Ronak <ronak.jain(a)amd.com<mailto:ronak.jain@amd.com<mailto:ronak.jain@amd.com%3cmailto:ronak.jain@amd.com>>>; Nagal, Amit <amit.nagal(a)amd.com<mailto:amit.nagal@amd.com<mailto:amit.nagal@amd.com%3cmailto:amit.nagal@amd.com>>>; Simek, Michal <michal.simek(a)amd.com<mailto:michal.simek@amd.com<mailto:michal.simek@amd.com%3cmailto:michal.simek@amd.com>>> Subject: [Tf-a-tests] Re: Query regarding the test coverage thru tf-a-tests Hi Mark and Oliver, A gentle reminder on the below request. Thanks, Senthil From: Thangaraj, Senthil Nathan Sent: Tuesday, August 20, 2024 3:44 PM To: Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com>>>; Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com>>>; tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>> Cc: Jain, Ronak <ronak.jain(a)amd.com<mailto:ronak.jain@amd.com<mailto:ronak.jain@amd.com%3cmailto:ronak.jain@amd.com>>>; Nagal, Amit <amit.nagal(a)amd.com<mailto:amit.nagal@amd.com<mailto:amit.nagal@amd.com%3cmailto:amit.nagal@amd.com>>>; Simek, Michal <michal.simek(a)amd.com<mailto:michal.simek@amd.com<mailto:michal.simek@amd.com%3cmailto:michal.simek@amd.com>>> Subject: RE: Query regarding the test coverage thru tf-a-tests Thanks a lot Mark and Oliver for your inputs and pointers. All of these seem to be more closely integrated with the CI/CD builds. Is there a way to get code coverage for manual test runs? Specifically, I'm looking to get coverage results after loading and executing all the tests from a developer build (e.g., using a binary like tftf.bin). Best regards, Senthil From: Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com>>>> Sent: Tuesday, August 20, 2024 3:16 PM To: Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com>>>>; tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>>; Thangaraj, Senthil Nathan <SenthilNathan.Thangaraj(a)amd.com<mailto:SenthilNathan.Thangaraj@amd.com<mailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com<mailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com>>>> Subject: RE: Query regarding the test coverage thru tf-a-tests Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding. All, This link is more current. The overall coverage numbers are not being reported due to an issue that is being worked on now. However you can see the individual coverage metrics if you click on a particular config where is says "success". The next page will have the link "Build Artifacts" at the top and so click that to the next where you will see the directory "trace_report". Click this and you will see a list of contents one of which should be index.html. If you click this you will see the individual coverage report for that config(test). tf-a-ci-coverage-gateway #72 [Jenkins] (trustedfirmware.org)<https://ci.trustedfirmware.org/job/tf-a-ci-coverage-gateway/72/> Let me know if you have questions... Mark From: Olivier Deprez <Olivier.Deprez(a)arm.com<mailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com<mailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com%3cmailto:Olivier.Deprez@arm.com>>>> Sent: Tuesday, August 20, 2024 2:27 AM To: tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>>; Thangaraj, Senthil Nathan <SenthilNathan.Thangaraj(a)amd.com<mailto:SenthilNathan.Thangaraj@amd.com<mailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com<mailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com%3cmailto:SenthilNathan.Thangaraj@amd.com>>>>; Mark Dykes <Mark.Dykes(a)arm.com<mailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com<mailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com%3cmailto:Mark.Dykes@arm.com>>>> Subject: Re: Query regarding the test coverage thru tf-a-tests Hi, You can refer to this job showing code coverage results aggregation from multiple test configurations: https://ci.trustedfirmware.org/job/tf-a-ci-coverage-gateway/67/ https://ci-builds.trustedfirmware.org/static-files/IK1tucCNXFdhS4AAQth8N7zW… I don't think there is a test level granularity. @Mark Dykes<mailto:Mark.Dykes@arm.com> may know better. Regards, Olivier. ________________________________ From: Thangaraj, Senthil Nathan via TF-A-Tests <tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>>> Sent: 20 August 2024 08:40 To: tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>> <tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>>> Subject: [Tf-a-tests] Query regarding the test coverage thru tf-a-tests Dear TF-A team, I have a query regarding the TF-A test. Specifically, I would like to know if there is a method to find out the code coverage for a specific test or for all the tests in current run? Your direction in this regard will be really appreciated. Thank you, Senthil -- TF-A-Tests mailing list -- tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>>> To unsubscribe send an email to tf-a-tests-leave(a)lists.trustedfirmware.org<mailto:tf-a-tests-leave@lists.trustedfirmware.org<mailto:tf-a-tests-leave@lists.trustedfirmware.org%3cmailto:tf-a-tests-leave@lists.trustedfirmware.org<mailto:tf-a-tests-leave@lists.trustedfirmware.org%3cmailto:tf-a-tests-leave@lists.trustedfirmware.org%3cmailto:tf-a-tests-leave@lists.trustedfirmware.org%3cmailto:tf-a-tests-leave@lists.trustedfirmware.org>>> -- TF-A-Tests mailing list -- tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org%3cmailto:tf-a-tests@lists.trustedfirmware.org>> To unsubscribe send an email to tf-a-tests-leave(a)lists.trustedfirmware.org<mailto:tf-a-tests-leave@lists.trustedfirmware.org<mailto:tf-a-tests-leave@lists.trustedfirmware.org%3cmailto:tf-a-tests-leave@lists.trustedfirmware.org>> -- TF-A-Tests mailing list -- tf-a-tests(a)lists.trustedfirmware.org<mailto:tf-a-tests@lists.trustedfirmware.org> To unsubscribe send an email to tf-a-tests-leave(a)lists.trustedfirmware.org<mailto:tf-a-tests-leave@lists.trustedfirmware.org>

1 year, 2 months

2
4
0 0

Canceled event with note: TF-A Tech Forum @ Thu Dec 12, 2024 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled with a note: "Hi, Cancelling as no topic proposed. Regards, Olivier. " TF-A Tech Forum Thursday Dec 12, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 3 months

1
0
0 0

Unable to merge gerrit#33536

by Amarinder Singh Sethi (QUIC)

Hi, I recently uploaded the patch (https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/33536) to add qti platform support for qcs615. The patch is fully isolated and doesn't touch any common code and doesn't get included in any other platform compilation. On enabling basic CI, I see some failures which are unrelated to my patch. I wonder what the next step should be. If somebody can help me, it will be greatly appreciated. Thanks Amarinder

1 year, 3 months

2
2
0 0

Trusted Firmware-A LTS v2.8.26 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.26 is now available. This release contains the following patches: a449c1360 build(npm): bump word-wrap from 1.2.3 to 1.2.4 [1] ceb400895 build(npm): update Node.js and all packages [2] 0abe5d571 build(deps): bump braces [3] 3de9d3abd chore(deps): bump micromatch [4] [1] https://review.trustedfirmware.org/q/I9a383e6d6ae907858028980eadccfa2070f42… [2] https://review.trustedfirmware.org/q/[1, "always", "Change-Id:"], /* Warning */ [3] https://review.trustedfirmware.org/q/I7e2a543a3bc67d426a69fc25f93b878c9b5a3… [4] https://review.trustedfirmware.org/q/I783a6838616c570a41a5a0f58db3e6430c43c… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.26/change-log.html Thanks, TF-A LTS team

1 year, 3 months

1
0
0 0

Trusted Firmware-A LTS v2.10.10 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.10 is now available. This release contains the following patches: 3ea256c36 build(deps): bump pip from 23.1.2 to 23.3 [1] f8a06a0f8 build(deps): bump urllib3 from 2.0.2 to 2.2.2 [2] 93ad43e79 build(deps): bump jinja2 from 3.1.2 to 3.1.4 [3] ebf6430a0 build(deps): bump idna from 3.4 to 3.7 [4] c5d2a030a build(deps): bump braces [5] 6c6e986bf build(npm): update Node.js and all packages [6] 395ef3534 chore(deps): bump micromatch [7] c9f3fb582 build(deps): bump setuptools in the pip group across 1 directory [8] [1] https://review.trustedfirmware.org/q/I40b0219fe5e6797fc2a2534d8ea8c9480af36… [2] https://review.trustedfirmware.org/q/I4f3a1ffe0cf374f433ac59b20b7d60ee77009… [3] https://review.trustedfirmware.org/q/I69248b2c17f8edfe7dfd27952aae688e7d424… [4] https://review.trustedfirmware.org/q/I78f5052e20572d92f1bc21213bb29b5549f34… [5] https://review.trustedfirmware.org/q/I7e2a543a3bc67d426a69fc25f93b878c9b5a3… [6] https://review.trustedfirmware.org/q/[1, "always", "Change-Id:"], /* Warning */ [7] https://review.trustedfirmware.org/q/I783a6838616c570a41a5a0f58db3e6430c43c… [8] https://review.trustedfirmware.org/q/Ibd4e4730bfc5cce8d85ec55021983d6f748ff… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.10/change-log.html Thanks, TF-A LTS team

1 year, 3 months

1
0
0 0

Firmware-A v2.12 release follow up - shrinkwrap

by Olivier Deprez

Hi, As a follow up to the Firmware-A v2.12 release [1], we are pleased to share the shrinkwrap tool [2] configurations have been updated to consume latest firmware/upstream ingredients using following tags: TF-A: v2.12.0 TF-a-tests: v2.12.0 Hafnium: v2.12.0 TF-RMM: tf-rmm-v0.6.0 CCA EDK2: 3223_arm_cca_rmm_v1.0_rel0_v3 linux: cca-full/v5+v7 kvmtool: cca/v3 An additional merge request is in queue for kvm-unit-tests update to cca/rmm-v1.0-rel0 tag. Shrinkwrap is a convenient tool for building a fully integrated Arm CCA SW stack running on the Base AEM FVP platform. In particular this is the tool of choice for RMM development to reproduce a 3 or 4 worlds RME based environment. Regards, Olivier. [1] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.… [2] https://shrinkwrap.docs.arm.com/en/latest/

1 year, 3 months

1
0
0 0

Re: Interaction with TF-a from NS World

by Tamas Ban

Hi Max, > Can we say this presentation (2022) is there and ready to use? Yes, there are multiple measured boot and attestation schemes are implemented in TF-A and Trusted Services. What to use is depends on your use case and your system capability: - A class core only - A+M system where the M core is in a secure enclave > By the way, you mentioned that attestation is not handled in TF-a (EL3), but the below EL3 handler handles it (RMM_ATTEST_GET_PLAT_TOKEN). Does it just send the request to the "Trusted Service" you were referencing? No, they are different. The available options/schemes: * -If you have a single A class core and you want something similar to psa_initial_attest_get_token() then read this: https://trusted-services.readthedocs.io/en/latest/services/attest-service-d… Here the token is created by a secure service running in SEL0/1. EL3 only responsible for making the world switch (S<->NS). This is callable from Linux user space, with the libs and kernel driver pointed out by George. * What you mentioned above (RMM_ATTEST_GET_PLAT_TOKEN) is basically the CCA attestation scheme, where there are two halves tokens. It is targeting the RME capable systems which otherwise have A+M cores. One half of the token is produced by the M class secure enclave(HES) the other half by the RMM running in REL2 on the A core. There is a hash link between the half tokens. Please elaborate your use case then I can help more! Regards, Tamas From: Gyorgy Szing <Gyorgy.Szing(a)arm.com> Sent: Monday, December 2, 2024 11:43 AM To: Max Adam <maxadamcamb(a)gmail.com>; Tamas Ban <Tamas.Ban(a)arm.com> Subject: Re: [TF-A] Interaction with TF-a from NS World Hi, "By the way, you mentioned that attestation is not handled in TF-a (EL3)," Sorry, my bad. Since you mentioned PSA I got the impression you are after PSA Initial Attestation, and that is out of scope for TF-A. Tamas: Can you please respond to the RMM related attestation question? /George On 2024-12-02, 11:38, "Max Adam" <maxadamcamb(a)gmail.com<mailto:maxadamcamb@gmail.com>> wrote: Hi Gyorgy, Thank you for the detailed comment. It is really helpful, especially this link seems good to chase: https://git.yoctoproject.org/meta-arm/about/documentation/trusted-services.… Basically, I was following this link from @Tamas.ban@arm.com<mailto:Tamas.ban@arm.com>; "CCA attestation and measured both" https://www.trustedfirmware.org/docs/Attestation_and_Measured_Boot.pdf Can we say this presentation (2022) is there and ready to use? By the way, you mentioned that attestation is not handled in TF-a (EL3), but the below EL3 handler handles it (RMM_ATTEST_GET_PLAT_TOKEN). Does it just send the request to the "Trusted Service" you were referencing? Error! Filename not specified. Gyorgy Szing <Gyorgy.Szing(a)arm.com<mailto:Gyorgy.Szing@arm.com>>, 2 Ara 2024 Pzt, 09:29 tarihinde şunu yazdı: Hi Max, Please check this picture [1]. It shows the exception levels on an aarch64 platforms, and typical components executing at each exception level. TF-A is a Secure Monitor implementation. It is the most privileged component, and its main goal is to route calls between the NWd and SWd. Each call to SWd must go through this component. E.g. if an "aarch64 App" wishes to use a service provided by a Trusted Service, a call has to be made into EL1 (e.g. Linux Kernel), then if a Hypervisor is present to EL2, then to the Monitor at EL3 (TF-A), then to optional S-EL2 (e.g. Hafnium), S-EL1 (e.g. OP_TEE) and finally to S-EL0. TF-A does not implement the PSA APIs. OP-TEE is a Trusted OS, and a reference implementation of the Global Platforms standards [2]. PSA is not part of GP, and AFAIK there is no TA implementing PSA APIs. The PSA reference implementation for Cortex-A is developed in the Trusted Services project. The project implements all services required for PSA certification (Crypto, ITS, PS, Attestation) plus a few non-psa ones like Firmware Update Service or UEFI Variable service. We developed a Linux kernel driver called tstee (up-stream since v6.10) , and two shared libraries which can be used by linux user-space applications to access the services. Libts implements service discovery and the TS RPC components, and "libtspsa" carries easy to use PSA client implementations (basically the C PSA API). Trusted Services follows the Firmware Framework for A-Profile standard (FF-A) which defines a protocol to be used between exception levels and a runtime model. PSA services are deployed to S-EL0 Secure Partitions and need a Secure Partition Manager implementation executing at a higher exception levels. The reference SPMD implementation is part of the TF-A project, the S-EL2 reference SPMC is Hafnium [5], and the S-EL1 reference implementation is OP-TEE SPMC [6]. (Only one SPMC implementation can be present on a system.) A major difference between the Cortex-M and the Cortex-A ecosystem is the level of diversity. While a Cortex-M stack is typically implemented using components from one or maximum a few stakeholders, a Cortex-A stack is built from components owned by a vast set of owners. As a result, integration of a Cortex-A software stack is much more complex. There are multiple integration systems targeting the problem like Buildroot and Yocto. Trusted Services supports two integration systems currently. The OP-TEE integration system, which is a gnumake and Buildroot based solution (see [7]) and Yocto where the meta-arm layer [8] hosts TS recipes. Please find some TS specific meta-arm documentation here: [9] For more help and information, about PSA on Cortex-A and TS feel free to drop an email to the TS mailing list [10], and/or to me. /George 1: https://documentation-service.arm.com/static/63a065c41d698c4dc521cb1b 2: https://globalplatform.org/about-globalplatform/ 3: https://trusted-services.readthedocs.io/en/stable/overview/index.html 4: https://developer.arm.com/architectures/Firmware%20Framework%20for%20A-Prof… 5: https://hafnium.readthedocs.io/en/latest/secure-partition-manager/index.html 6: https://optee.readthedocs.io/en/latest/architecture/spmc.html 7: https://github.com/OP-TEE/build 8: https://git.yoctoproject.org/meta-arm 9: https://git.yoctoproject.org/meta-arm/about/documentation/trusted-services.… 10: https://lists.trustedfirmware.org/mailman3/lists/trusted-services.lists.tru… On 2024-12-01, 21:14, "Max Adam via TF-A" <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>> wrote: Hello All, I am coming from the TF-m domain, and now I am struggling with TF-a as I am not a Linux expert. I am just looking for the interactions with TF-a, such as getting psa attestation token etc. How can I find example these interactions from NS World (Linux) or lower privilege Secure World Executions such as OP-TEE or OP-TEE TAs? I suppose there shall be drivers and APIs provided by TF-a? Thanks Max

1 year, 3 months

3
3
0 0

Interaction with TF-a from NS World

by Max Adam

Hello All, I am coming from the TF-m domain, and now I am struggling with TF-a as I am not a Linux expert. I am just looking for the interactions with TF-a, such as getting psa attestation token etc. How can I find example these interactions from NS World (Linux) or lower privilege Secure World Executions such as OP-TEE or OP-TEE TAs? I suppose there shall be drivers and APIs provided by TF-a? Thanks Max

1 year, 3 months

2
1
0 0

Addition of mbedTLS as a submodule dependency to TF-A-Tests

by Soby Mathew

Hi Everyone, In order to facilitate development for Device Assignment tests for RME-DA, we have added MbedTLS repo as a submodule dependency to tf-a-tests. The merge commit can be found here : https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/3e72cd… The patch is done in such a way that existing build of TF-A-Tests or Test run is not affected due to the additional dependency. Only tests which depend on MbedTLS will be affected in that they will either be skipped or fail at runtime due to the missing dependency. Also, the change allows to use the config `MBEDTLS_DIR` to point to a MbedTLS directory outside the tf-a-tests source tree. This aligns with the TF-A mechanism for MbedTLS dependancy in case the submodule mechanism is not preferred. We expect existing CI and testing infrastructure to be unaffected by this change. Please let us know if you have any comments. Best Regards Soby Mathew

1 year, 3 months

1
0
0 0

Trusted Firmware-A LTS v2.8.25 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.25 is now available. This release contains the following patches: 3e1ecab9a build(deps): bump pip from 23.1.2 to 23.3 [1] 73421e1df build(deps): bump urllib3 from 2.0.2 to 2.2.2 [2] b607e5481 build(deps): bump jinja2 from 3.1.2 to 3.1.4 [3] 720d7ea22 build(deps): bump idna from 3.4 to 3.7 [4] [1] https://review.trustedfirmware.org/q/I40b0219fe5e6797fc2a2534d8ea8c9480af36… [2] https://review.trustedfirmware.org/q/I4f3a1ffe0cf374f433ac59b20b7d60ee77009… [3] https://review.trustedfirmware.org/q/I69248b2c17f8edfe7dfd27952aae688e7d424… [4] https://review.trustedfirmware.org/q/I78f5052e20572d92f1bc21213bb29b5549f34… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.25/change-log.html Thanks, TF-A LTS team

1 year, 3 months

1
0
0 0

Canceled event: TF-A Tech Forum @ Thu Nov 28, 2024 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled. TF-A Tech Forum Thursday Nov 28, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 3 months

1
0
0 0

Trusted Firmware v2.12 release announcement

by Olivier Deprez

Hi All, We are pleased to announce the formal release of Trusted Firmware-A version 2.12 bundle of project deliverables. This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium, RMM, Trusted Services, and TF-A OpenCI scripts/jobs components. These went live on Nov, 21st 2024. Please find references to tags and change logs at the end of this email. Many thanks to the trustedfirmware.org community for the active engagement in delivering this release! Notable features of the release version 2.12 are as follows: TF-A/EL3 * New CPUs support: Cortex-A320 (Arcadia), Cortex-A720AE. * Arch extensions: : FEAT_THE, FEAT_LS64_ACCDATA, FEAT_Debugv8p9, FEAT_SCTLR2, FEAT_FGT2 ; Arm 9.4 : FEAT_D128 support. * Context management: Asymmetric CPU features, EL3 execution context, SVE S/R support. * RME: GPT contiguous descriptor (or GPT large mappings support). * Arm CCA: added attestation generic library, el3 attestation token signing support. Boot flow * Tools: * Introduced the Transfer List Compiler (TLC) Host Tool supporting the FW hand-off specification. * Introduced CoT Device Tree to C File (DT2C) tool. * mbedTLS Improvements: * Resolved random authentication failures with ECDSA. * Enhanced mbedTLS configuration selection. * Maximize usage of mbedTLS library APIs in TF-A. * Upgraded to mbedTLS v3.6.1. * Feature addition/support: * Support for the ECDSA P-384 curve with the PSA Crypto implementation. * Documentation: * Added the DPE Design and Threat Model document to TF-A readthedocs. Errata (CPU/GIC) * Cortex-A720, Cortex-A520, Cortex-X4 errata. TF-A platforms support * New platforms added: TC4, RD-1 AE, RK3566/RK3568. * Platform fixes: FPGA, FVP, Neoverse-RD, TC, Corstone-1000, Allwinner, AST2700, Poplar, Agilex, A3K, MT8188, iMX8M, S32G274A, qemu, Rpi3, Rockchip, STM32MP1, STM32MP2, Versal, ZynqMP. Hafnium/SPM (S-EL2) * FF-A features additions * FF-A v1.2 FFA_MSG_WAIT RX buffer ownership flag. * FF-A v1.2 FFA_VERSION endpoint restriction. * FF-A v1.1 VM availability messages. * Architectural support * vCPU IPI signaling. * Arch timer virtualization. * RME: GPF support and memcpy hardening. * Secure Interrupt Handling for UP S-EL1 partitions. TF-RMM (R-EL2) * REL0 RMM 1.0 support. * Support for alternative attestation token signing via EL3. * Various improvements and bugfixes as listed in the change log. TF-A Tests * Arm arch. extensions: AMU, FEAT_FGT2, LS64_ACCDATA, FEAT_Debugv8p9, LS64 64-byte load/store. * Asymmetric feature testing (FEAT_SPE, FEAT_TRBE, FEAT_TCR2). * EL1 and EL2 context switch tests. * FF-A: v1.2 support, S-EL2 arch timer virtualization, S-EL2+RME hardening, EL3 SPMC TFTF test suite, EL3 SVE test coverage. * RME: RMM v1.0 testing support, PCIe DOE support, RMI support for FEAT_LPA2, SIMD, PAuth. * Platforms: AMD Versal Gen 2 added, Neoverse-RD refactoring, FVP PCIe support. Release tags across repositories: https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r… https://git.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags… https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-ci-scripts/+/refs/t… https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-job-configs/+/refs/… https://git.trustedfirmware.org/plugins/gitiles/hafnium/hafnium/+/refs/tags… https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-ci-scripts/+/ref… https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-job-configs/+/re… https://git.trustedfirmware.org/plugins/gitiles/TF-RMM/tf-rmm/+/refs/tags/t… https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/… Change logs: https://trustedfirmware-a.readthedocs.io/en/v2.12.0/change-log.html#id1 https://trustedfirmware-a-tests.readthedocs.io/en/latest/change-log.html#ve… https://hafnium.readthedocs.io/en/v2.12.0/change-log.html#v2-12 https://tf-rmm.readthedocs.io/en/latest/about/change-log.html#v0-6-0 Regards, Olivier.

1 year, 3 months

1
0
0 0

Changelog for v2.12 Release

by Govindraj Raja

Hello Everyone, Please take a look at the changelog for your respective platforms ahead of the TF-A v2.12 release. The changelog is autogenerated from the commit messages of the patches that have been merged since the v2.11 release. Here's your chance to give us guidance on any small manual adjustments you would like to see. Patch: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/33483 Rendered Version: https://ci-builds.trustedfirmware.org/static-files/pAvWwn44kBOyAVI04_7T9WjV… -- Thanks, Govindraj R

1 year, 4 months

1
0
0 0

Canceled event: TF-A Tech Forum @ Thu Nov 14, 2024 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled. TF-A Tech Forum Thursday Nov 14, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 4 months

1
0
0 0

Reference Secure Partition Code with FF-A

by Belsare, Akshay

Hello everyone, I'm seeking a reference code for a Standalone Secure Partition using FF-A. Any guidance or suggestions would be greatly appreciated! TIA, Akshay

1 year, 4 months

3
2
0 0

TF-A: Compilation issues for Rockchip platforms

by Quentin Schulz

Hi all, I've sent a few patches for fixing some compilation warnings or issues on Rockchip platforms [1][2][3][4][5] but I'm left with a few still... [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/33080 [2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/33081 [3] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/33082 [4] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/33083 [5] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/33084 1) RK3588 symbol redefinition in assembly ======================================================================== commit fc3b98b2124c2b773322da0201e9ad7a697e6323 Author: Quentin Schulz <quentin.schulz(a)cherry.de> Date: Mon Oct 28 12:40:18 2024 +0100 fix(rk3588): pmu: fix assembly symbol redefinition Somehow cpus_pd_req_enter_wfi() gets called multiple times and clang isn't happy about redefining the same label multiple times (it is an inline function). An option could be to force the code to not be inlined (with __attribute__((noinline))) as removing the explicit inline still made the compiler inline the code. Recreate the while loop without a label to fix the clang build issue: plat/rockchip/rk3588/drivers/pmu/pmu.c:763:7: error: symbol 'wfi_loop' is already defined 763 | "wfi_loop:\n" | ^ <inline asm>:5:1: note: instantiated into assembly here 5 | wfi_loop: | ^ Signed-off-by: Quentin Schulz <quentin.schulz(a)cherry.de> Change-Id: Ie9f55135b2f95a78deb7cbb94f9a62d3ba61e808 diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c index f693dbdf0..f05d3e58f 100644 --- a/plat/rockchip/rk3588/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c @@ -760,10 +760,10 @@ static inline void cpus_pd_req_enter_wfi(void) "mrs x0, S3_0_C15_C2_7\n" "orr x0, x0, #0x1\n" "msr S3_0_C15_C2_7, x0\n" - "wfi_loop:\n" + "ldr x0, .+4\n" "isb\n" "wfi\n" - "b wfi_loop\n"); + "br x0\n"); } static void nonboot_cpus_off(void) ========================================================================= This only happens for clang and I'm a bit confused as to why. Applying the above patch fixing that issue but inspecting the assembly code reveals something really odd. **With** that patch, with gcc: 25c8c: d510149f msr dbgprcr_el1, xzr 25c90: d538f2e0 mrs x0, s3_0_c15_c2_7 25c94: b2400000 orr x0, x0, #0x1 25c98: d518f2e0 msr s3_0_c15_c2_7, x0 25c9c: 58000020 ldr x0, 0x25ca0 25ca0: d5033fdf isb 25ca4: d503207f wfi 25ca8: d61f0000 br x0 **with** that patch, with clang: 26d2c: d510149f msr dbgprcr_el1, xzr 26d30: d538f2e0 mrs x0, s3_0_c15_c2_7 26d34: b2400000 orr x0, x0, #0x1 26d38: d518f2e0 msr s3_0_c15_c2_7, x0 26d3c: 58000020 ldr x0, 0x26d40 <--- "my" ldr 26d40: d5033fdf isb 26d44: d503207f wfi 26d48: d61f0000 br x0 <--- "my" br 26d4c: 94000e76 bl 0x2a724 26d50: d510149f msr dbgprcr_el1, xzr 26d54: d538f2e0 mrs x0, s3_0_c15_c2_7 26d58: b2400000 orr x0, x0, #0x1 26d5c: d518f2e0 msr s3_0_c15_c2_7, x0 26d60: 58000020 ldr x0, 0x26d64 <--- "my" ldr 26d64: d5033fdf isb 26d68: d503207f wfi 26d6c: d61f0000 br x0 <--- "my" br So I think the above patch is just a band-aid on what the actually is but I have no idea what could be going on. If I use this patch instead, to match the other assembly instructions in this file ========================================================================= diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c index f693dbdf0..a4128b214 100644 --- a/plat/rockchip/rk3588/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c @@ -760,10 +760,10 @@ static inline void cpus_pd_req_enter_wfi(void) "mrs x0, S3_0_C15_C2_7\n" "orr x0, x0, #0x1\n" "msr S3_0_C15_C2_7, x0\n" - "wfi_loop:\n" + "1:\n" "isb\n" "wfi\n" - "b wfi_loop\n"); + "b 1b\n"); } static void nonboot_cpus_off(void) ========================================================================= It happily compiles, though the binary still seems to contain this loop twice. Using __attribute__((noinline)) the code is not duplicated, but I assume this is expected as it would now simply be a function. 2) RK3399 warning array subscript 0 is outside array bounds of 'volatile unsigned int[0]' [-Warray-bounds=] """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" In file included from src/dram.c:12: src/dram.c: In function 'm0_main': include/rk3399_mcu.h:15:34: warning: array subscript 0 is outside array bounds of 'volatile unsigned int[0]' [-Warray-bounds=] 15 | (*(volatile unsigned int *)(c)); __v; }) | ~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/rk3399_mcu.h:16:69: note: in definition of macro 'mmio_write_32' 16 | #define mmio_write_32(c, v) ((*(volatile unsigned int *)(c)) = (v)) | ^ src/dram.c:67:23: note: in expansion of macro 'mmio_read_32' 67 | mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); | ^~~~~~~~~~~~ cc1: note: source object is likely at address zero In function 'ddr_set_pll', inlined from 'm0_main' at src/dram.c:71:2: include/rk3399_mcu.h:14:40: warning: array subscript 0 is outside array bounds of 'volatile unsigned int[0]' [-Warray-bounds=] 14 | #define mmio_read_32(c) ({unsigned int __v = \ | ^~~ include/rk3399_mcu.h:16:69: note: in definition of macro 'mmio_write_32' 16 | #define mmio_write_32(c, v) ((*(volatile unsigned int *)(c)) = (v)) | ^ src/dram.c:47:23: note: in expansion of macro 'mmio_read_32' 47 | mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); | ^~~~~~~~~~~~ In function 'm0_main': cc1: note: source object is likely at address zero In function 'ddr_set_pll', inlined from 'm0_main' at src/dram.c:71:2: include/rk3399_mcu.h:14:40: warning: array subscript 0 is outside array bounds of 'volatile unsigned int[0]' [-Warray-bounds=] 14 | #define mmio_read_32(c) ({unsigned int __v = \ | ^~~ include/rk3399_mcu.h:16:69: note: in definition of macro 'mmio_write_32' 16 | #define mmio_write_32(c, v) ((*(volatile unsigned int *)(c)) = (v)) | ^ src/dram.c:49:23: note: in expansion of macro 'mmio_read_32' 49 | mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); | ^~~~~~~~~~~~ In function 'm0_main': cc1: note: source object is likely at address zero include/rk3399_mcu.h:16:35: warning: array subscript 0 is outside array bounds of 'volatile unsigned int[0]' [-Warray-bounds=] 16 | #define mmio_write_32(c, v) ((*(volatile unsigned int *)(c)) = (v)) | ~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/dram.c:80:9: note: in expansion of macro 'mmio_write_32' 80 | mmio_write_32(PARAM_ADDR + PARAM_M0_DONE, M0_DONE_FLAG); | ^~~~~~~~~~~~~ cc1: note: source object is likely at address zero """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" This function is used in many places, but only in very specific places is it triggering a warning, when PARAM_ADDR is used, but only when accessed from m0 C files. PARAM_ADDR is set to 0xc0. From !m0 files, access to PARAM_ADDR seems to be done through the M0_PARAM_ADDR which is M0_BINCODE_BASE + PARAM_ADDR. For m0 files, it's directly accessing PARAM_ADDR. I honestly don't really know why it's complaining for m0 files but not the !m0 ones. 3) RK3399 expected string in '.incbin' directive This is only for clang. """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" <instantiation>:6:10: error: expected string in '.incbin' directive .incbin /home/qschulz/work/upstream/trusted-firmware-a/build/rk3399/release/m0/rk3399m0.bin ^ plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20:1: note: while in macro instantiation INCBIN """/home/qschulz/work/upstream/trusted-firmware-a/build/rk3399/release/m0/rk3399m0.bin""", "rk3399m0_bin", ".sram.incbin" ^ <instantiation>:6:10: error: expected string in '.incbin' directive .incbin /home/qschulz/work/upstream/trusted-firmware-a/build/rk3399/release/m0/rk3399m0pmu.bin ^ plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21:1: note: while in macro instantiation INCBIN """/home/qschulz/work/upstream/trusted-firmware-a/build/rk3399/release/m0/rk3399m0pmu.bin""", "rk3399m0pmu_bin", ".pmusram.incbin" ^ """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" With the following patch: ========================================================================= diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu_fw.S b/plat/rockchip/rk3399/drivers/pmu/pmu_fw.S index 26f331317..ed70cba1f 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu_fw.S +++ b/plat/rockchip/rk3399/drivers/pmu/pmu_fw.S @@ -11,7 +11,7 @@ .type \sym, @object .align 4 \sym : - .incbin \file + .incbin "\file" .size \sym , .-\sym .global \sym\()_end \sym\()_end : ========================================================================= clang seems happy with that error but the linker triggers another one: ld.lld: warning: ignoring memory region assignment for non-allocatable section '.incbin_sram' ld.lld: error: section '.pmusram' will not fit in region 'PMUSRAM': overflowed by 3928 bytes Would appreciate some guidance there :) Cheers, Quentin

1 year, 4 months

3
15
0 0

Re: TF-A: Compilation issues for Rockchip platforms

by Chris Kay

I’m afraid I’ve not been able to reproduce the .incbin error – it all links fine for me. $ clang --version Ubuntu clang version 18.1.3 (1ubuntu1) Target: aarch64-unknown-linux-gnu Thread model: posix InstalledDir: /usr/bin

1 year, 4 months

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 447712: Integer handling issues (NO_EFFECT) /plat/arm/board/fvp/fvp_pm.c: 332 in fvp_node_hw_state() ________________________________________________________________________________________________________ *** CID 447712: Integer handling issues (NO_EFFECT) /plat/arm/board/fvp/fvp_pm.c: 332 in fvp_node_hw_state() 326 int ret = 0; 327 328 /* 329 * The format of 'power_level' is implementation-defined, but 0 must 330 * mean a CPU. We also allow 1 to denote the cluster 331 */ >>> CID 447712: Integer handling issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "power_level < 0ULL". 332 if ((power_level < ARM_PWR_LVL0) || (power_level > ARM_PWR_LVL1)) 333 return PSCI_E_INVALID_PARAMS; 334 335 /* 336 * Read the status of the given MPDIR from FVP power controller. The 337 * power controller only gives us on/off status, so map that to expected ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 4 months

1
0
0 0

Canceled event: TF-A Tech Forum @ Thu Oct 31, 2024 5pm - 6pm (GMT+1) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled. TF-A Tech Forum Thursday Oct 31, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 4 months

1
0
0 0

TF-A Tech Forum regular call

by Olivier Deprez

Dear TF-A ML members, As mentioned in https://www.trustedfirmware.org/meetings/tf-a-technical-forum/, trustedfirmware.org hosts regular technical calls on Thursdays. It mentions TF-A although in practise a number of Cortex-A projects beyond TF-A were discussed (refer to prior recordings on this page). Unfortunately this slot hasn't been very active recently. By this email I'm kindly emphasizing this forum is open to the community (and beyond trustedfirmware.org members) and you are welcome to propose topics. Presentations/slides are not strictly necessary, and we can also host informal discussions or session of questions. If you think of a topic, please reach to me and I'll be happy to accommodate. Thanks for your contributions in advance! Regards, Olivier.

1 year, 4 months

1
0
0 0

How to configure TZC-400 in ATF?

by 钱非凡

I tried to add two new tzc regions in ATF's source code, and test the memory access in the new region. ```cpp #define ARM_TZC_REGIONS_DEF \ {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE, TZC_REGION_S_RDWR, 0}, \ {ARM_NS_DRAM1_BASE, 0xA0000000-1, ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ {0xA0000000, 0xB0000000-1, ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ {0xB0000000, 0xC0000000-1, ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ {0xC0000000, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} ``` But FVP throws some warnings: ``` Info: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: common_reset starts Info: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: build config register value 0x3003f08 4 filters, 9 regions, address width 64 Info: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.flashloader0: FlashLoader: Loaded 3164 kB from file '/home/bea1e/functionality-prototype/build/../trusted-firmware-a/build/fvp/release/fip.bin' Info: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.secureflashloader: FlashLoader: Loaded 25 kB from file '/home/bea1e/functionality-prototype/build/../trusted-firmware-a/build/fvp/release/bl1.bin' Info: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: common_reset starts Info: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: build config register value 0x3003f08 4 filters, 9 regions, address width 64 Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 220 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5126760 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 224 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5126760 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 228 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5126760 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 22c In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5126760 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 230 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5126760 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 234 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5126760 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 240 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5127800 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 244 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5127800 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 248 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5127800 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 24c In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5127800 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 250 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5127800 ns Warning: FVP_Base_RevC_2xAEMvA: FVP_Base_RevC_2xAEMvA.bp.tzc_400: attempt to write invalid address 254 In file: (unknown):0 In process: FVP_Base_RevC_2xAEMvA.thread_p_32 @ 5127800 ns ``` It seems the configuration registers for the two new regions are invalid. But I dont know how to solve this problem. Here are the arguments of FVP: ``` -C bp.ve_sysregs.exit_on_shutdown=1 \ -C cache_state_modelled=0 \ -C pctl.startup=0.0.0.0 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C bp.secure_memory=1 \ -C bp.dram_size=8 \ -C bp.tzc_400.diagnostics=1 \ -C bp.secureflashloader.fname=$(TF_A_PATH)/build/fvp/$(TF_A_BUILD)/bl1.bin \ -C bp.flashloader0.fname=$(TF_A_PATH)/build/fvp/$(TF_A_BUILD)/fip.bin \ -C bp.virtioblockdevice.image_path=$(BOOT_IMG) ``` Should I add more arguments while booting FVP? Is there any other advice for me to test the TZASC configurations?

1 year, 4 months

2
1
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 447121: Incorrect expression (UNUSED_VALUE) /drivers/cadence/emmc/cdns_sdmmc.c: 434 in card_reset() ________________________________________________________________________________________________________ *** CID 447121: Incorrect expression (UNUSED_VALUE) /drivers/cadence/emmc/cdns_sdmmc.c: 434 in card_reset() 428 uint32_t reg_value = 0; 429 430 /* Reading SRS10 value before writing */ 431 reg_value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_SRS10); 432 433 if (power_enable == true) { >>> CID 447121: Incorrect expression (UNUSED_VALUE) >>> Assigning value "4294963455U" to "reg_value" here, but that stored value is overwritten before it can be used. 434 reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); 435 reg_value = ((1 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); 436 } else { 437 reg_value &= ~((7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); 438 } 439 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_SRS10, reg_value); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 4 months

1
0
0 0

Trusted Firmware-A LTS v2.10.9 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.9 is now available. This release contains the following patches: c4c6eae4e feat(cm): add errata 2938996, 2726228 [1] 33a04460d fix(cpus): modify the fix for Cortex-A75 erratum 764081 [2] [1] https://review.trustedfirmware.org/q/I53b037839820c8b3a869f393588302a365d5b… [2] https://review.trustedfirmware.org/q/Ifda1f4cb32bdec9a9af29397ddc03bf22a7a8… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.9/change-log.html Thanks, TF-A LTS team

1 year, 4 months

1
0
0 0

Trusted Firmware-A LTS v2.8.24 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.24 is now available. This release contains the following patches: 10cd41d91 feat(cm): add errata 2938996, 2726228 [1] 578d3577f fix(cpus): modify the fix for Cortex-A75 erratum 764081 [2] [1] https://review.trustedfirmware.org/q/I53b037839820c8b3a869f393588302a365d5b… [2] https://review.trustedfirmware.org/q/Ifda1f4cb32bdec9a9af29397ddc03bf22a7a8… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.24/change-log.html Thanks, TF-A LTS team

1 year, 4 months

1
0
0 0

Trusted Firmware-A LTS v2.10.8 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.8 is now available. This release contains the following patches: 9c723cd1a docs(prerequisites): update MbedTLS version to 3.6.1 [1] d3726fb42 refactor(mbedtls): remove hack in LIBMBEDTLS_CFLAGS [2] 34a4f2446 fix(cpus): workaround for Cortex-X4 erratum 3076789 [3] [1] https://review.trustedfirmware.org/q/I1a68dfcb52a8361c1689cb6ef12d265a6462f… [2] https://review.trustedfirmware.org/q/I934adefbf2fed16e16b9d98bc8674125b70b0… [3] https://review.trustedfirmware.org/q/Ib100bfab91efdb6330fdcdac127bcc5732d59… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.8/change-log.html Thanks, TF-A LTS team

1 year, 4 months

1
0
0 0

Trusted Firmware-A LTS v2.8.23 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.23 is now available. This release contains the following patches: 89c138ae8 docs(prerequisites): update MbedTLS version to 3.6.1 [1] 625207291 fix(cpus): workaround for Cortex-X4 erratum 3076789 [2] [1] https://review.trustedfirmware.org/q/I1a68dfcb52a8361c1689cb6ef12d265a6462f… [2] https://review.trustedfirmware.org/q/Ib100bfab91efdb6330fdcdac127bcc5732d59… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.23/change-log.html Thanks, TF-A LTS team

1 year, 4 months

1
0
0 0

Canceled event: TF-A Tech Forum @ Thu Oct 17, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled. TF-A Tech Forum Thursday Oct 17, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 4 months

1
0
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 445539: High impact quality (WRITE_CONST_FIELD) /drivers/arm/dcc/dcc_console.c: 153 in console_dcc_register() ________________________________________________________________________________________________________ *** CID 445539: High impact quality (WRITE_CONST_FIELD) /drivers/arm/dcc/dcc_console.c: 153 in console_dcc_register() 147 .flush = dcc_console_flush, 148 }, 149 }; 150 151 int console_dcc_register(console_t *console) 152 { >>> CID 445539: High impact quality (WRITE_CONST_FIELD) >>> A write to an aggregate overwrites a const-qualified field within the aggregate. 153 memcpy(console, &dcc_console.console, sizeof(console_t)); 154 return console_register(console); 155 } 156 157 void console_dcc_unregister(console_t *console) 158 { 159 dcc_console_flush(console); 160 (void)console_unregister(console); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 4 months

1
0
0 0

Kernel source for RAS error injection on neoverse reference design platform

by Nagal, Amit

Hi, I am referring to https://neoverse-reference-design.docs.arm.com/en/latest/features/ras/ras.h… for RAS error injection on neoverse reference design platform. I am referring to below steps : mount -t debugfs none /sys/kernel/debug # Step needed for Buildroot only echo 0x80020000 > /sys/kernel/debug/apei/einj/error_type echo 1 > /sys/kernel/debug/apei/einj/oem-einj/sel-firmware-first echo 1 > /sys/kernel/debug/apei/einj/oem-einj/sel-component echo 1 > /sys/kernel/debug/apei/einj/oem-einj/sel-error-type echo 1 > /sys/kernel/debug/apei/einj/error_inject I want to refer to kernel source driver which exposes attributes : sel-firmware-first , sel-component , sel-error-type. Also that driver must be doing the actual injections and registering sdei events with EL3 . can I be advised where to look in for kernel sources ? Regards Amit

1 year, 5 months

4
6
0 0

New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 445362: Uninitialized variables (UNINIT) /drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c: 95 in atxslewrate_program() ________________________________________________________________________________________________________ *** CID 445362: Uninitialized variables (UNINIT) /drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c: 95 in atxslewrate_program() 89 uint32_t atxpredrvmode; 90 uint32_t c_addr; 91 uint16_t atxslewrate; 92 93 c_addr = anib << 12; 94 >>> CID 445362: Uninitialized variables (UNINIT) >>> Using uninitialized value "ck_anib_inst[0]". 95 if ((anib == ck_anib_inst[0]) || (anib == ck_anib_inst[1])) { 96 /* CK ANIB instance */ 97 #if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE 98 atxpredrvmode = 0x0U; 99 #else /* STM32MP_LPDDR4_TYPE */ 100 atxpredrvmode = 0x1U; ** CID 445361: Control flow issues (DEADCODE) /drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c: 1021 in aforcetricont_acx4anibdis_program() ________________________________________________________________________________________________________ *** CID 445361: Control flow issues (DEADCODE) /drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c: 1021 in aforcetricont_acx4anibdis_program() 1015 #endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ 1016 1017 /* 1018 * If all the lanes can be disabled, and Anib is not the first or last disable 1019 * entire chiplet 1020 */ >>> CID 445361: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "anib != 0U" inside this statement: "if (aforcetricont == 15U &&...". 1021 if ((aforcetricont == 0xFU) && (anib != 0U) && 1022 (anib != (config->uib.numanib - 1U))) { 1023 acx4anibdis = acx4anibdis | (0x1U << anib); 1024 } 1025 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TANIB | c_addr | 1026 CSR_AFORCETRICONT_ADDR))), ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=u001.AxU2LYlgjL6eX23u9ErQy-2…

1 year, 5 months

1
0
0 0

Introduction and Interest in Contributing to the TF-A Project

by omar elmasry

Dear TF-A Contributors, I hope this email finds you well. My name is Omar, and I am an Embedded Software Engineer at Valeo. I am excited to introduce myself to the Trusted Firmware-A community and look forward to contributing to the project. I have already enrolled in the mailing list and reviewed the documentation. I am passionate about technical deep dives and always eager to explore new areas. I am particularly interested in ARM-based projects, and I'm enthusiastic about getting involved with fellow geeks who share the same passion for cutting-edge technology. I would greatly appreciate any guidance on current tasks or areas where contributions are needed so I can start contributing effectively. Thank you for your time, and I look forward to collaborating with all of you! Best regards, Omar Embedded Software Engineer | Valeo (+20) 10 6962 8429

1 year, 5 months

1
0
0 0

Trusted Firmware-A LTS v2.10.7 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.10.7 is now available. This release contains the following patches: 23b59a38b fix(cpus): workaround for Cortex-X4 erratum 2897503 [1] [1] https://review.trustedfirmware.org/q/I3178a890b6f1307b310e817af75f8fdfb8668… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.10.7/change-log.html Thanks, TF-A LTS team

1 year, 5 months

1
0
0 0

Trusted Firmware-A LTS v2.8.22 Release Announcement

by ci_notify＠trustedfirmware.org

Hello, Trusted Firmware-A LTS version 2.8.22 is now available. This release contains the following patches: ac24f38b8 fix(cpus): workaround for Cortex-X4 erratum 2897503 [1] [1] https://review.trustedfirmware.org/q/I3178a890b6f1307b310e817af75f8fdfb8668… Alternatively, Change Log is available in the documentation section: https://trustedfirmware-a.readthedocs.io/en/lts-v2.8.22/change-log.html Thanks, TF-A LTS team

1 year, 5 months

1
0
0 0

Re: TF-A Tech Forum

by Olivier Deprez

Hi, Cancelling as no topic planned for today. Regards, Olivier. ________________________________ From: Trusted Firmware Public Meetings Sent: 24 July 2024 17:36 To: Trusted Firmware Public Meetings <linaro.org_havjv2figrh5egaiurb229pd8c(a)group.calendar.google.com>; marek.bykowski(a)gmail.com <marek.bykowski(a)gmail.com>; okash.khawaja(a)gmail.com <okash.khawaja(a)gmail.com>; tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org> Subject: TF-A Tech Forum When: 03 October 2024 17:00-18:00. Where: This event has been updated We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/<https://www.google.com/url?q=https%3A%2F%2Fwww.trustedfirmware.org%2Fmeetin…> Trusted Firmware is inviting you to a scheduled Zoom meeting. Join Zoom Meeting https://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvd…<https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fmy%2Ftruste…> One tap mobile +16465588656,,9159704974# US (New York) +16699009128,,9159704974# US (San Jose) Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-free Meeting ID: 915 970 4974 Find your local number: https://zoom.us/u/ad27hc6t7h<https://www.google.com/url?q=https%3A%2F%2Fzoom.us%2Fu%2Fad27hc6t7h&sa=D&us…> When Every 2 weeks from 8am to 9am on Thursday (Mountain Standard Time - Phoenix) Guests marek.bykowski(a)gmail.com<mailto:marek.bykowski@gmail.com> okash.khawaja(a)gmail.com<mailto:okash.khawaja@gmail.com> tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> View all guest info<https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1…> RSVP for tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> for all events in this series Yes<https://calendar.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tM…> No<https://calendar.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tM…> Maybe<https://calendar.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tM…> More options<https://calendar.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1…> Invitation from Google Calendar<https://calendar.google.com/calendar/> You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more<https://support.google.com/calendar/answer/37135#forwarding>

1 year, 5 months

1
0
0 0

Canceled event: TF-A Tech Forum @ Thu Oct 3, 2024 5pm - 6pm (GMT+2) (tf-a@lists.trustedfirmware.org)

by Olivier Deprez

This event has been canceled. TF-A Tech Forum Thursday Oct 3, 2024 ⋅ 5pm – 6pm Central European Time - Paris We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Trusted Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://linaro-org.zoom.us/my/trustedfirmware?pwd=VktXcm5MNUUyVVM4R0k3ZUtvdU84QT09 One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h Guests tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

1 year, 5 months

1
0
0 0

2026

2025

2024

2023

2022

2021

2020

2019

2018

TF-A