This event has been canceled with a note:
"No TF-A Tech forum on Dec 25th."
TF-A Tech Forum
Thursday Dec 25, 2025 ⋅ 5pm – 6pm
Central European Time - Paris
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https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
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Hi, On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will
present a design update on TF-RMM Live Firmware Activation: This
presentation describes the revised TF-RMM Low-VA MMU and
global-runtime-data design required to support Live Firmware Activation
(LFA). Compared to the earlier approach (outlined in the TFA Tech Forum
session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings
and per-platform handcrafted Low-VA contexts, the new design is driven by
several changes in RMM specification: RMM must now support runtime
mapping/unmapping of PAs for RMM objects like struct granule , reuse those
dynamic mappings across LFA transitions. These PAs can come either from NS
world at runtime or EL3 reservation from RMM carveout. In order to migrate
Stage 1 dynamic mappings across LFA instances, RMM needs to reduce
dependence on platform-specific MMU setup, and provide a structured
framework for allocating, versioning and migrating global runtime data. The
Stage 1 Low-VA is therefore split into static and dynamic regions managed
by the common xlat layer. The detailed design is captured in the TF-RMM
wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial
design presented in the TFA Tech Forum session on 12-Jun-2025 [1] : [1]
Previous LFA discussion:
https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations [2]
https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act…
Regards, Olivier.
TF-A Tech Forum
Thursday Dec 11, 2025 ⋅ 5pm – 6pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A
Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu,
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Hi,
On Dec 11th in the TF-A Tech Forum at 4.00pm UK, Soby Mathew will present a design update on TF-RMM Live Firmware Activation:
This presentation describes the revised TF-RMM Low-VA MMU and global-runtime-data design required to support Live Firmware Activation (LFA). Compared to the earlier approach (outlined in the TFA Tech Forum session on 12-Jun-2025 [1] ), which assumed mostly fixed boot time mappings and per-platform handcrafted Low-VA contexts, the new design is driven by several changes in RMM specification: RMM must now support runtime mapping/unmapping of PAs for RMM objects like struct granule , reuse those dynamic mappings across LFA transitions. These PAs can come either from NS world at runtime or EL3 reservation from RMM carveout.
In order to migrate Stage 1 dynamic mappings across LFA instances, RMM needs to reduce dependence on platform-specific MMU setup, and provide a structured framework for allocating, versioning and migrating global runtime data. The Stage 1 Low-VA is therefore split into static and dynamic regions managed by the common xlat layer. The detailed design is captured in the TF-RMM wiki RFC “TF-RMM Live Firmware Activation [2]” and builds on the initial design presented in the TFA Tech Forum session on 12-Jun-2025 [1] :
[1] Previous LFA discussion: https://github.com/TF-RMM/tf-rmm/wiki/TFA-Tech-Forum-Presentations
[2] https://github.com/TF-RMM/tf-rmm/wiki/RFC:-TF%E2%80%90RMM-Live-Firmware-Act…
Regards,
Olivier.
Please have a look at following patch, where on our platform we try to maintain single image of TFA (for custom CPU and Cortex A55)
Cortex A55 does not have Secure EL2 implemented, while on the other hand our custom CPU has secure EL2 (and we run Hafnium there)
On Cortex A55 ARM AEM model:
write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
the context was set before as
u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
and setting ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT causes crash since secure EL2 is not implemented.
resulting into following patch which resolves the issue. seeking feedback/discussion if I can post it to upstream TFA,
let me know if I am missing something here.
lib/el3_runtime: set NS bit if secure el2 is not implemented
before setting icc_sre_el2 set NS bit for non-secure context so that
the ICC_SRE_DIB_BIT and ICC_SRE_DFB_BIT are preserved
Signed-off-by: Oza Pawandeep <quic_poza(a)quicinc.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index e31255868..5100f2f00 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1411,7 +1411,18 @@ static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t securit
u_register_t scr_el3 = read_scr_el3();
#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
- write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
+ if (is_feat_sel2_supported()) {
+ write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
+ } else {
+ write_scr_el3(scr_el3 | SCR_NS_BIT);
+ isb();
+
+ write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
+
+ write_scr_el3(scr_el3);
+ isb();
+ }
+
#else
write_scr_el3(scr_el3 | SCR_NS_BIT);
isb();
Regards,
Oza.
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TF-A Tech Forum
Thursday 2025-11-13 ⋅ 4pm – 5pm
United Kingdom Time
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
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Tech ForumTime: May 15, 2025 02:00 PM London Every 2 weeks on Thu,
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