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Hi
I'm looking for a suggestion for a reliable place to store a small boot
index for PSA Firmware Update. SNVS LPGPRs looked promising, but NXP’s
guidance is thin and we don’t keep the battery-backed LP domain alive, so
those values won’t survive many power cycles. Are there better options on
LS1028A? Would using the user RAM byte in our external I2C RTC make sense?
Or perhaps should I store it on eMMC? (we don't use raw NOR/NAND flash).
That RTC I mentioned is already accessed in both U-Boot and Linux, so I’m
wary of conflicts but can try it if you think it’s viable.
Any suggestions would be much appreciated.
Best regards
Patryk
Hi,
I have a sort of generic Arm architecture question that's not directly
related to TF-A (other than that TF-A controls some of the registers
involved in this decision), but I'm hoping that one of the experts
here can still help me out or at least refer me to someone who can.
I'm trying to figure out how exception routing for SError aborts works
in EL2. Specifically, I have a bootloader (BL33) running in NS-EL2 and
I want the "simple" setup that it manages all its own exceptions, the
same way that an OS kernel normally manages all exceptions at EL1. I
assumed that I could achieve that simply by installing exception
handlers, unmasking all exceptions in PSTATE, and leaving all the
special trap feature bits in the MSRs at 0 (disabled).
This seems to work for synchronous exceptions and external aborts, but
not for SErrors. Looking at the architecture reference manual
(revision L.b), table D1-14 in section D1.3.6.3 (page D1-6114), I can
see that my case is represented by the first line (all special trap
bits 0), which shows that SErrors caused by EL0 and EL1 would be
routed to EL1 as expected (though even when PSTATE.A is 1 which seems
odd?), but SErrors caused by EL2 will get ignored and remain pending
(with no regard to PSTATE.A). Instead, the "default" behavior I expect
(aborts get routed to the EL that caused them if PSTATE.A is 0) seems
to require me to enable SCTLR_EL2.NMEA. But if you're looking at the
description of SCTLR_EL2.NMEA, it says that it controls whether
PSTATE.A masks SError exceptions at EL2 (and that if it is 0, SError
exceptions are not taken at EL2 if PSTATE.A == 1). Doesn't that imply
that SError exceptions *are* taken at EL2 if PSTATE.A == 0? What does
a control that seems to be about trapping masked aborts from a lower
EL have to do with unmasked aborts from my current EL?
Basically, I think what I'm asking is: is that table really correct as
printed (some behavior we've observed seems to indicate it is), and if
so, why? Why do SError exceptions seem to behave differently by
default in EL1 and EL2 (in regards to unmasked exceptions taken from
the same exception level)? Why does the PSTATE.A bit only seem to
apply to EL0 and EL1, not EL2 and EL3, even for exceptions taken from
the same level, when this peculiarity seems to not be mentioned
anywhere else in the manual? Why do SError exceptions get treated so
differently from external aborts in EL2/EL3, when in EL1 they seem to
mostly count as the same? Is the current description of the NMEA bit
in the SCTLR_EL2 register documentation really accurate, if it also
seems to make fundamental changes to cases not really mentioned in
that description? Is there any way for EL2 to only handle its own
SError exceptions without interfering with EL1's exception handling
when FEAT_DoubleFault2 is not implemented (other than flipping
HCR_EL2.AMO on every EL2 entry/exit)? And am I the only one who finds
this all incredibly inconsistent and confusing?
I feel like I'm missing some critical insight in how you were meant to
think about this to make it make sense, would appreciate any help in
that regard!
Thanks,
Julius
Hi,
We are pleased to announce the formal release of Trusted Firmware-A version 2.14 bundle of project deliverables.
This includes Trusted Firmware-A, Trusted Firmware-A Tests, Hafnium, TF-RMM, Trusted Services, and TF-A OpenCI scripts/jobs components.
These went live on Nov, 24th 2025.
Please find tag references and change logs at the end of this email.
Many thanks to the trustedfirmware.org community for the active engagement in delivering this release!
Notable features of the release version 2.14 are as follows:
TF-A/EL3
* New architectural features support: FEAT_FGWTE3, FEAT_IDTE3, FEAT_RME_GPC2, FEAT_AIE, FEAT_CPA2, FEAT_MPAM_PE_BW_CTRL, FEAT_PFAR, FEAT_RME_GDI.
*
Live Firmware Activation: base support enabling TF-RMM LFA, added RMM MEM RESERVE ABI.
*
Armv9 CPU power down abandon support
* GICv5 driver permitting normal world kernel boot
* GIC720-AE support added
* Per-cpu framework supporting NUMA platforms
* SMCCC SoC name support (SMCCC v1.6 SMCCC_ARCH_SOC_ID)
* SPMD: added FF-A v1.3 FFA_NS_RES_INFO_GET, FFA_ABORT interfaces
* EL3 SPMC: add multiple UUIDs support, TPM event log delivered by HOB list, FFA_MEM_RETRIEVE_REQ from hypervisor
* RME: FEAT_D128 for realm world, SMCCC_ARCH_FEATURE_AVAILABILITY
* Platforms: RD-Aspen added, updates to Arm FVP/Juno, AMD Versal Gen2, Intel, MT8189, MT8196, i.MX94, i.MX95, S32G274A, QTI Kodiak, Renesas R-Car, STM32MP1, STM32MP2, STM32MP21, STM32MP25, Xilinx Versal, ZynqMP
Boot flow
* Transfer list and event log libraries now offered as shared libraries consumed as submodules by TF-A.
* Update to mbedTLS 3.6.5
* Various PSA FWU improvements, namely BL2 in a dedicated FIP, GPT-corruption notifications to BL32, and expanded FWU tests.
Errata/Security mitigations (CPU/GIC)
* New CPU support: Arm Lumex C1, Dionysus, Caddo/Veymont, Venom.
* Added close to 30 new CPU errata across multiple processor families, based on the latest SDEN updates.
Hafnium/SPM (S-EL2)
* FF-A v1.3 early adoption
* FFA_NS_RES_INFO_GET ABI added
* Partition lifecycle support: new states, abort handling. Pre-requisite to secure partitions live firmware activation.
* Notifications support refactored with per-vCPU notifications removed.
* Multi-GIC configuration supporting complex topologies.
* Shrinkwrap used at core of Hafnium testing infrastructure.
TF-RMM (R-EL2)
* RMM v1.1 Planes support
* PMU, timer, GIC ownership transfer.
* Support for FEAT_S1POE/S1PIE, FEAT_S2POE/S2PIE
* RMM v1.1 Memory Encryption Contexts (MEC) support
* Realm Device Assignment
* RMM v1.1. ALP12 base Device Assignment support
* RMI VDEV ABIs, PDEV life cycle, root port IDE key programming, SPDM client as EL0 app.
* Improved ID registers trapping leveraging SMCCC ARCH_FEATURE_AVAILABILITY, in light of future FEAT_IDTE3 support.
* Additional architectural support: FEAT_TCR2, FEAT_D128, single-copy atomics,
TF-A Tests
*
RME: DA and PCIe, Planes, MEC
*
SPM/FF-A
* Bumped support o FF-A v1.3
* FFA_ABORT ABI
* Deprecated per-vCPU notifications.
* FWU: added negative testing (invalid image size, corrupted ROTPK)
* GICv5 support added
* Arm architecture tests
* FEAT_TCR2 (for RME) , FEAT_IDTE3, FEAT_MPAM_PE_BW_CTRL, FEAT_EBEP, FEAT_AIE, FEAT_PFAR
* SMCCC_ARCH_SOC_ID
* SMCCC_ARCH_FEATURE_AVAILABILITY
* Fuzzing: added SMC fuzzer documentation
* Basic LFA framework tests
* Platforms updates: AMD/Xilinx, Arm FVP, Corstone-1000
Trusted Services
* RD-Aspen platform support added.
* EFI ESRT handling in FWU Proxy (supporting Corstone1000 platform).
* Block Storage service threat modelling.
Release tags across repositories:
https://git.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/r…https://git.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags…https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-ci-scripts/+/refs/t…https://git.trustedfirmware.org/plugins/gitiles/ci/tf-a-job-configs/+/refs/…https://git.trustedfirmware.org/plugins/gitiles/hafnium/hafnium/+/refs/tags…https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-ci-scripts/+/ref…https://git.trustedfirmware.org/plugins/gitiles/ci/hafnium-job-configs/+/re…https://git.trustedfirmware.org/plugins/gitiles/TF-RMM/tf-rmm/+/refs/tags/t…https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/…
Change logs:
https://trustedfirmware-a.readthedocs.io/en/v2.14.0/change-log.html#id1https://trustedfirmware-a-tests.readthedocs.io/en/v2.14.0/change-log.html#v…https://hafnium.readthedocs.io/en/v2.14.0/change-log.html#id1https://tf-rmm.readthedocs.io/en/tf-rmm-v0.8.0/about/change-log.html#v0-8-0https://git.trustedfirmware.org/plugins/gitiles/TS/trusted-services/+/refs/…
Regards,
Olivier.
Hi,
This is a one off session for a partner to present coming improvements related to Hafnium project.
Apologies for the meeting time not accommodating people in US timezones.
We'll record the session and publish in the TF-A tech forum page as usual.
Regards,
Olivier.
________________________________
From: Google Calendar <calendar-notification(a)google.com> on behalf of Olivier Deprez via Hafnium <hafnium(a)lists.trustedfirmware.org>
Sent: 07 November 2025 09:13
To: hafnium(a)lists.trustedfirmware.org <hafnium(a)lists.trustedfirmware.org>
Subject: [Hafnium] Invitation: TF-A Tech Forum - Hafnium future looking improvements @ Thu Nov 13, 2025 12pm - 1pm (GMT+1) (hafnium(a)lists.trustedfirmware.org)
TF-A Tech Forum - Hafnium future looking improvements
Thursday Nov 13, 2025 ⋅ 12pm – 1pm
Central European Time - Paris
Location
https://linaro-org.zoom.us/j/93557863987?pwd=56a1l8cBnetDTZ6eazHGaE1Ctk4W34…https://www.google.com/url?q=https%3A%2F%2Flinaro-org.zoom.us%2Fj%2F9355786…
Hi, This is a one off session for a partner to present coming improvements
related to Hafnium project. Apologies for the meeting time not
accommodating people in US timezones. We'll record the session and publish
in the TF-A tech forum page as usual. Regards,Olivier.Trusted Firmware is
inviting you to a scheduled Zoom meeting.Please download and import the
following iCalendar (.ics) files to your calendar
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