Hi Pali,
My understanding of the errata reporting mechanism is that some erratas are always checked during CPU boot. If the corresponding MACRO (ERRATA_A53_*) is disabled, then the ERRATA_MISSING code is reported.
I would be concerned if the CPU is affected by the errata. If the errata needs to be enabled, the fix would be to enable the ERRATA_A53_* from the platform makefile.
Hope this helps.
-Varun
-----Original Message-----
From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Pali Rohár via TF-A
Sent: Wednesday, July 7, 2021 9:11 PM
To: Olivier Deprez <Olivier.Deprez(a)arm.com>; Bipin Ravi <Bipin.Ravi(a)arm.com>; tf-a(a)lists.trustedfirmware.org
Cc: Konstantin Porotchkin <kostap(a)marvell.com>; Marek Behún <marek.behun(a)nic.cz>
Subject: Re: [TF-A] Missing CPU workaround warning message
External email: Use caution opening links or attachments
Hello! Could somebody from TF-A helps with these two topics? I would really need to know if "missing errata warnings" debug message is some critical and needs to be fixed (and how?) or it is just a debug message and therefore should not be a warning...
On Monday 28 June 2021 17:11:18 Pali Rohár wrote:
> On Monday 28 June 2021 14:03:06 Olivier Deprez wrote:
> > Hi,
> >
> > Is the question strictly related to this platform not implementing the mentioned errata (for which a platform change can be emitted)?
>
> Hello! The first question is if this is an issue that CPU workaround
> is missing. And if yes (which seems to be) how big issue it is? And
> how to resolve it?
>
> > Or is it more generally that those "missing errata warnings" are not printed in release mode?
> > Assuming the latter, it looks to me it is the integrator mistake to not include the appropriate mitigations at development phase (hence while using debug mode for building TF-A).
> > Then when the device is deployed (hence most often built for release mode), if this message is printed it is an indication for a malicious agent that such attack vector through mis-implemented errata is possible. So the consequence is possibly even worst than just "missing" to include the errata.
> >
> > Other TF-Aers (Bipin?) may have other opinions?
>
> And this is a second question. If missing CPU workaround is an issue,
> should not be it printed also in release build?
>
> Also I see that in release builds are omitted not only messages about
> missing CPU workarounds, but basically _all_ warning messages. But
> notice messages are _not_ omitted. Which seems strange as in most
> cases notice message has lower priority than warning message.
>
> >
> > Regards,
> > Olivier.
> >
> > ________________________________________
> > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of
> > Pali Rohár via TF-A <tf-a(a)lists.trustedfirmware.org>
> > Sent: 28 June 2021 15:36
> > To: tf-a(a)lists.trustedfirmware.org
> > Cc: Konstantin Porotchkin; Marek Behún
> > Subject: [TF-A] Missing CPU workaround warning message
> >
> > Hello! If TF-A for Marvell Armada 3720 platform is compiled in debug
> > mode then at runtime it prints following warning messages:
> >
> > WARNING: BL1: cortex_a53: CPU workaround for 855873 was missing!
> > WARNING: BL1: cortex_a53: CPU workaround for 1530924 was missing!
> >
> > These lines are not printed in non-debug mode. It is an issue?
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Hi All,
We have refactored/redesigned the existing measured boot driver present in the TF-A repo to support it with multiple backend driver(s) (for example, TCG Event Log, physical TPM, etc) instead of it being strongly coupled with the TCG Event Log driver.
Proposed refactored patches are posted here: https://review.trustedfirmware.org/q/topic:%22refactor-mb%22+(status:open%2…
Any feedback/comments on these patches are much appreciated.
These patches mainly consist of the below changes:
1. Move image measurement in the generic layer, just after loading and authentication of the image. Previously, the platform layer was responsible for the measurement. For example, the Arm FVP platform layer was doing it as part of the post-load hook operation.
2. Measurement and recording of the images loaded by BL1. Previously, DTB config files loaded by BL1 were not part of measured at all. Also, it looks safer and cleaner approach to record the measurement taken by BL1 straightaway in TCG Event log buffer/physical TPM/any other TPM backend instead of deferring these recordings to BL2.
3. Pass Event Log buffer information from BL1 to BL2 so that the TCG Event Log buffer initialised by BL1 extended further with the measurements taken by BL2.
Note: These patches neither add any new functional backend driver for measured boot nor update any existing backend driver functionality (i.e. TCG Event Log driver). These changes only structured the measured boot code to provide a space to plug in any new backend driver(s) in future for the measured boot.
Thanks,
Manish Badarkhe
Hi all,
I tried submitting a change for review at https://review.trustedfirmware.org,
but I ran into authentication issues.
1. First try (https):
$ git push origin HEAD:refs/for/integration
Username for 'https://review.trustedfirmware.org': jatron
Password for 'https://jatron@review.trustedfirmware.org':
remote: Unauthorized
fatal: Authentication failed for '
https://review.trustedfirmware.org/TF-A/trusted-firmware-a/'
I tried clicking "GENERATE NEW PASSWORD" in
https://review.trustedfirmware.org/settings/, but I got the following
error message:
An error occurred
Error 500 (Server Error): Internal server error
Endpoint: /accounts/self/password.http
2. Second try (ssh):
I got the following error message when I tried registering a new SSH key
for use with Gerrit. This happened when I clicked "ADD NEW SSH KEY" in
https://review.trustedfirmware.org/settings/.
An error occurred
Error 500 (Server Error): Internal server error
Endpoint: /accounts/self/sshkeys
The error message didn't stop the GUI from recording my key though. My new
key was listed under "SSH keys" after the change. When I ran a git push
command using ssh, I got the following error.
$ git push ssh://jatron@review.trustedfirmware.org/TF-A/trusted-firmware-a
HEAD:refs/for/integration
jatron(a)review.trustedfirmware.org: Permission denied (publickey).
fatal: Could not read from remote repository.
Please make sure you have the correct access rights
and the repository exists.
Am I doing something incorrectly? Any help would be much appreciated. If
this is not the mailing list for these types of questions, please let me
know so I can reroute my email to the proper destination.
Thanks,
Jorge Troncoso
Hi all,
I'm planning to submit a series of patches that aim to improve the
robustness and reusability of the UFS code. The impacted files
are drivers/ufs/ufs.c and include/drivers/ufs.h. The patches mainly consist
of the below changes:
1. Delete asserts. Return error values instead.
2. Add retry logic and timeouts.
3. Remove infinite loops.
4. Reuse ufshc_send_uic_cmd() for DME_GET and DME_SET commands.
5. Add a function ufs_send_cmd() that can be reused in other places.
ufs_send_cmd() calls four functions in
sequence: get_utrd(&utrd), ufs_prepare_cmd(&utrd,
...), ufs_send_request(utrd.task_tag), and ufs_check_resp(&utrd,
RESPONSE_UPIU).
I wanted to give everyone visibility of what is coming up and hopefully
start a discussion around this work. Any early input to help shape the
design would be much appreciated.
Thanks,
Jorge Troncoso
Hi all,
I want to write a TA which will be called from the Normal World and be
handled by a specific Trusted OS. Currently, I am using 3 Cactus OS
(provided by TF-A-Tests) in SEL1, and a Hafnium in SEL2. Here is my partial
building cmd
make CROSS_COMPILE=aarch64-none-elf- SPD=spmd CTX_INCLUDE_EL2_REGS=1
ARM_ARCH_MINOR=4 PLAT=fvp DEBUG=1
BL33=../tf-a-tests/build/fvp/debug/tftf.bin
BL32=../hafnium/out/reference/secure_aem_v8a_fvp_clang/hafnium.bin
SP_LAYOUT_FILE=../tf-a-tests/build/fvp/debug/sp_layout.json all fip
I have created some EL3 services at services/std_svc, but have not created
a TA.
In my view, to call the TA, I think I should pass (1) the ID of the TA (but
I am not sure how to get the ID) (2) several parameters, which may be
loaded into registers. Here may be a calling process.
ldr x0,=0xdeadbeef // loading ID
ldr x1,=0x11111 // input parameters
ldr x2,=0x22222 // input parameters
smc #0
Then I think I should write a corresponding handler (of the TA) in Cactus
OS. When we call "smc #0", EL3 will trap it, and route it to a specific TA.
However, I don't know how to do it. Can you provide some useful examples?
Sincerely,
Wang Chenxu
Hello,
Last Thursday we got an issue on our @foss.st.com mail server,
preventing us from receiving mails.
The issue was corrected, and I can now correctly receive mails, except
the ones from trustedfirmware.org.
Is there some kind of filtering on trustedfirmware.org side, as those
addresses got error replies?
I've tried to delete my yann.gautier(a)foss.st.com in the trusted firmware
gerrit settings, to re-enter it again, but I cannot receive the
verification e-mail.
Could you check if @foss.st.com addresses are rejected somewhere?
Thanks,
Yann
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
3 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 3 of 3 defect(s)
** CID 373165: Code maintainability issues (UNUSED_VALUE)
/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.c: 467 in spm_vcorefs_get_vcore()
________________________________________________________________________________________________________
*** CID 373165: Code maintainability issues (UNUSED_VALUE)
/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.c: 467 in spm_vcorefs_get_vcore()
461 int spm_vcorefs_get_vcore(unsigned int gear)
462 {
463 int ret_val;
464
465 switch (gear) {
466 case 3:
>>> CID 373165: Code maintainability issues (UNUSED_VALUE)
>>> Assigning value from "vcore_opp_0_uv" to "ret_val" here, but that stored value is overwritten before it can be used.
467 ret_val = vcore_opp_0_uv;
468 case 2:
469 ret_val = vcore_opp_1_uv;
470 case 1:
471 ret_val = vcore_opp_2_uv;
472 case 0:
** CID 373164: Code maintainability issues (UNUSED_VALUE)
/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.c: 471 in spm_vcorefs_get_vcore()
________________________________________________________________________________________________________
*** CID 373164: Code maintainability issues (UNUSED_VALUE)
/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.c: 471 in spm_vcorefs_get_vcore()
465 switch (gear) {
466 case 3:
467 ret_val = vcore_opp_0_uv;
468 case 2:
469 ret_val = vcore_opp_1_uv;
470 case 1:
>>> CID 373164: Code maintainability issues (UNUSED_VALUE)
>>> Assigning value from "vcore_opp_2_uv" to "ret_val" here, but that stored value is overwritten before it can be used.
471 ret_val = vcore_opp_2_uv;
472 case 0:
473 default:
474 ret_val = vcore_opp_3_uv;
475 }
476 return ret_val;
** CID 373163: Code maintainability issues (UNUSED_VALUE)
/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.c: 469 in spm_vcorefs_get_vcore()
________________________________________________________________________________________________________
*** CID 373163: Code maintainability issues (UNUSED_VALUE)
/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.c: 469 in spm_vcorefs_get_vcore()
463 int ret_val;
464
465 switch (gear) {
466 case 3:
467 ret_val = vcore_opp_0_uv;
468 case 2:
>>> CID 373163: Code maintainability issues (UNUSED_VALUE)
>>> Assigning value from "vcore_opp_1_uv" to "ret_val" here, but that stored value is overwritten before it can be used.
469 ret_val = vcore_opp_1_uv;
470 case 1:
471 ret_val = vcore_opp_2_uv;
472 case 0:
473 default:
474 ret_val = vcore_opp_3_uv;
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
Hi all,
I have a little question, how can I disable the hypervisor mode so EL2 will be just bridge to EL1 ns?
(I mean without touching common ARM code only the platform-oriented code)
Thanks,
Boaz.
________________________________
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