July 2021 - TF-A - lists.trustedfirmware.org

Re: [TF-A] Missing CPU workaround warning message

by Varun Wadekar

Hi Pali, My understanding of the errata reporting mechanism is that some erratas are always checked during CPU boot. If the corresponding MACRO (ERRATA_A53_*) is disabled, then the ERRATA_MISSING code is reported. I would be concerned if the CPU is affected by the errata. If the errata needs to be enabled, the fix would be to enable the ERRATA_A53_* from the platform makefile. Hope this helps. -Varun -----Original Message----- From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Pali Rohár via TF-A Sent: Wednesday, July 7, 2021 9:11 PM To: Olivier Deprez <Olivier.Deprez(a)arm.com>; Bipin Ravi <Bipin.Ravi(a)arm.com>; tf-a(a)lists.trustedfirmware.org Cc: Konstantin Porotchkin <kostap(a)marvell.com>; Marek Behún <marek.behun(a)nic.cz> Subject: Re: [TF-A] Missing CPU workaround warning message External email: Use caution opening links or attachments Hello! Could somebody from TF-A helps with these two topics? I would really need to know if "missing errata warnings" debug message is some critical and needs to be fixed (and how?) or it is just a debug message and therefore should not be a warning... On Monday 28 June 2021 17:11:18 Pali Rohár wrote: > On Monday 28 June 2021 14:03:06 Olivier Deprez wrote: > > Hi, > > > > Is the question strictly related to this platform not implementing the mentioned errata (for which a platform change can be emitted)? > > Hello! The first question is if this is an issue that CPU workaround > is missing. And if yes (which seems to be) how big issue it is? And > how to resolve it? > > > Or is it more generally that those "missing errata warnings" are not printed in release mode? > > Assuming the latter, it looks to me it is the integrator mistake to not include the appropriate mitigations at development phase (hence while using debug mode for building TF-A). > > Then when the device is deployed (hence most often built for release mode), if this message is printed it is an indication for a malicious agent that such attack vector through mis-implemented errata is possible. So the consequence is possibly even worst than just "missing" to include the errata. > > > > Other TF-Aers (Bipin?) may have other opinions? > > And this is a second question. If missing CPU workaround is an issue, > should not be it printed also in release build? > > Also I see that in release builds are omitted not only messages about > missing CPU workarounds, but basically _all_ warning messages. But > notice messages are _not_ omitted. Which seems strange as in most > cases notice message has lower priority than warning message. > > > > > Regards, > > Olivier. > > > > ________________________________________ > > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of > > Pali Rohár via TF-A <tf-a(a)lists.trustedfirmware.org> > > Sent: 28 June 2021 15:36 > > To: tf-a(a)lists.trustedfirmware.org > > Cc: Konstantin Porotchkin; Marek Behún > > Subject: [TF-A] Missing CPU workaround warning message > > > > Hello! If TF-A for Marvell Armada 3720 platform is compiled in debug > > mode then at runtime it prints following warning messages: > > > > WARNING: BL1: cortex_a53: CPU workaround for 855873 was missing! > > WARNING: BL1: cortex_a53: CPU workaround for 1530924 was missing! > > > > These lines are not printed in non-debug mode. It is an issue? > > -- > > TF-A mailing list > > TF-A(a)lists.trustedfirmware.org > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli > > sts.trustedfirmware.org%2Fmailman%2Flistinfo%2Ftf-a&data=04%7C01 > > %7Cvwadekar%40nvidia.com%7Cb3605175f552468740e708d941836783%7C43083d > > 15727340c1b7db39efd9ccc17a%7C0%7C0%7C637612854914595696%7CUnknown%7C > > TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX > > VCI6Mn0%3D%7C1000&sdata=%2FW6HuFPYQCD5ECIA%2FZZxhm5ti5HYILNlsWTz > > moJ7L8E%3D&reserved=0 -- TF-A mailing list TF-A(a)lists.trustedfirmware.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.tru…

3 years, 10 months

6
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Re: [TF-A] Rethrow SError from EL3 to kernel on arm64

by Ming Huang

Hi, I did the test report SDEI to kernel with fatal severity in APEI / CPER while EL3 received SEA(SCR_EL3.EA = 1). Kernel will panic and print calltrace, but this calltrace was not the position where error occured(another word where throw SEA), instead calltrace in ghes.c. How can SDEI solution let kernel print calltrace at right position? For issue analysis, the right position calltrace is very useful. For ACPI firmware-first, we set SCR_EL3.EA = 1, although the solution rethrow EA back to kernel will suffer from some problems, but this solution can let kernel print calltrace at right position. Best Regards, Ming Huang On 5/25/21 8:08 PM, James Morse via TF-A wrote: > Hi Pali, > > I assume the aborts you are ignoring are precise! SError can be imprecise. > I guess these are due to some integration issue with the PCIe root-complex. You shouldn't > get aborts outside a RAS error. PCIe has DPC/eDPC and AER for signalling RAS errors - I > guess these aren't supported on your platform. > > > To emulte the synchronous/asynchronous exceptions means emulating what the CPU would do if > SCR_EL3.EA weren't set. I'm not sure how familiar you are with the CPU's exception model > and all its routing/masking controls. A short tour of what is involved: > (the numbered references are for DDI0487G.a, they may have moved in your version) > > > To emulate an exception you need to copy ESR_EL3, SPSR_EL3 and ELR_EL3 to the ESR, SPSR > and ELR of the target EL. You need to calculated new PSTATE and PC for SPSR_EL3 and > ELR_EL3. The way the CPU does this is described in the psuedocode in the arm-arm. See > AArch64.TakeException. This will involve reading SCTLR of the target EL. > For Synchronous-External-Abort, if the FnV bit is clear, you should copy FAR_EL3 to FAR of > the target EL too. > > There is a GPL implementation of some of these bits in the kernel's KVM code, but that is > probably of limited use due to the license. > > > To determine the target EL you need to examine the routing controls set by the lower ELs. > Synchronous Exceptions are the easiest as they can't be masked: > The routing rules are describe in D1.12.4 "Routing synchronous External Aborts" is a > little terse. It glosses over HCR_EL2.TGE that would also route the exception to EL2. > > For a synchronous-external-abort triggered by EL1 where HCR_EL2.TERR is not supported, or > clear: If the fault was at stage1, it goes to EL1, if the fault was at stage2, it goes to > EL2. There is nothing the ESR to tell you which it was as the CPU indicates this with the > target EL, which was overridden by SCR_EL3.EA. (The architecture doesn't expect you to be > re-injecting exceptions from EL3). > Pragmatically the best option is to allow HCR_EL2.AMO to route synchronous exceptions to > EL2 too. (this is a big hint that a hypervisor is managing errors for this exception > level). If ELR_EL3.S1PTW is set, this is definitely a stage2 fault, EL1 should never see > this bit set. > (Synchronous Exceptions can't be routed to a lower EL). > > > Synchronous errors were the easy one. Asynchronous error routing is described in D1.13.1 > "Asynchronous exception routing". You want to take note of HCR_EL2.{AMO, TGE}. But it can > also be masked by PSTATE.A of the target EL. (See D1.13.2 "Asynchronous exception masking"): > If SPSR_EL3.M is the target EL, SPSR_EL3.A would have masked SError. You cannot emulate > the exception if this bit is set. > If SPSR_EL3.M is lower than the target EL, then you can emulate the exception to the > target EL. > If SPSR_EL3.M is higher than the target EL, then SError is effectively masked, and you > cannot emulate the exception. > > > (I don't think HPFAR_EL2 needs to be set for these cases, but I'd need to check) > > > Finally, you still need something to do if you can't emulate the exception. Updating a > system log if you have one and rebooting is the only real option. > > > > Thanks, > > James > > > On 25/05/2021 11:08, Pali Rohár wrote: >> Hello! >> >> Platform is not ACPI based. PCIe core in some cases sends External >> Aborts to kernel which needs to be masked/ignored. I have not found a >> way how to reconfigure PCIE core to not send these aborts. >> >> In mentioned review is a link to kernel list where was discussion about >> custom kernel handlers to ignore some of EA. But this approach was >> rejected with information that TF-A should handle these aborts and >> ignores those which should not be propagated back to kernel. >> >> If I clear SCR_EL3.EA then aborts (including those which should be >> ignored) are sent to kernel and kernel makes them fatal. So this is not >> a solution. >> >> If I do not clear SCR_EL3.EA then in TF-A board/platform code I can >> implement check for aborts which needs to be ignored. But remaining >> aborts are not delivered to kernel and TF-A makes them fatal. Which is >> not correct too. >> >> So, what I need, is to route all External Aborts to TF-A, implement >> logic which ignores specific PCIE aborts and all remaining aborts needs >> to be propagated back to kernel like if SCR_EL3.EA is clear. >> >> So it means to implement some logic of abort injection. >> >> On Tuesday 25 May 2021 11:00:09 James Morse wrote: >>> Hi Guys, >>> >>> Does this platform need external-aborts to be routed to EL3? If not, you can clear >>> SCR_EL3.EA and be done with it. This allows the EL2 OS/Hypervisor to take control of the >>> routing of these exceptions. (which sounds like what you want) >>> >>> >>> Otherwise: >>> As Soby describes, the choices are SDEI or emulate the exception according to the arm-arm >>> psuedocode as if EL3 weren't implemented. This is best avoided as its difficult to get >>> right: you have to create a new PSTATE for the target exception level, and read the >>> routing controls to work out which exception level that is. >>> >>> As Achin says, emulating the exception isn't always possible as Asynchronous exceptions >>> can be masked. The hardware does this automatically when it takes an exception (e.g. irq). >>> (Linux unmask it again once its read the CPU state). >>> >>> This can leave you holding what may be an imprecise-asynchronous-abort in EL3, unable to >>> emulate the exception or proceed without causing any RAS error to become uncontained. >>> If you can't inject the emulated exception, the error still has to be handled at EL3. If >>> this is an ACPI system you can do a soft restart of the normal-world and present the error >>> via ACPI's BERT (boot error record table) which describes an error that happened in a >>> previous life. >>> >>> >>> If your platform is ACPI firmware-first, using SDEI will make life easier. You still need >>> to handle the 'SDEI masked' case, but it is a lot less likely to happen. Linux only does >>> this over power-management events that (may) disable the MMU. >>> >>> >>> (EL2 doesn't have any of these problems as errors are almost always contained by stage2, >>> and it has hardware features for injecting asynchronous exceptions, which cope with the >>> masking and deferring) >>> >>> >>> Thanks, >>> >>> James >>> >>> >>> On 25/05/2021 10:08, Achin Gupta wrote: >>>> Hi, >>>> >>>> The last time I checked injecting an SError from a higher to lower EL is a bad >>>> idea since the latter could be running with SErrors masked. >>>> >>>> EL3 could check this before injecting but then there is no consistent contract >>>> with the lower EL about reporting of these errors. SDEI does not suffer from the >>>> same problem. >>>> >>>> +James who knows more from the OS/Hypervisor perspective. >>>> >>>> cheers, >>>> Achin >>>> -------------------------------------------------------------------------------- >>>> *From:* TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Soby Mathew >>>> via TF-A <tf-a(a)lists.trustedfirmware.org> >>>> *Sent:* 25 May 2021 09:59 >>>> *To:* Pali Rohár <pali(a)kernel.org> >>>> *Cc:* kabel(a)kernel.org <kabel(a)kernel.org>; tf-a(a)lists.trustedfirmware.org >>>> <tf-a(a)lists.trustedfirmware.org> >>>> *Subject:* Re: [TF-A] Rethrow SError from EL3 to kernel on arm64 >>>> [+tf-a list] >>>> Hi Pali, >>>> There are 2 philosophies for handing SError in the system, kernel first and >>>> firmware first. Assuming you want to stick with firmware first handling (i.e >>>> scr_el3.ea is set to 1), then as you mentioned, there are 2 ways to notify the >>>> kernel for delegating the error handling: SDEI and SError injection back to >>>> kernel. Upstream TF-A only supports SDEI at the moment. >>>> >>>> For SError injection back to lower EL, you have to setup the hardware state via >>>> software at higher EL in such a way that it appears that the fault was taken to >>>> the exception vector at the lower exception level. The pseudocode function >>>> AArch64.TakeException() in ARM ARM shows the behavior when the PE takes an >>>> exception to an Exception level using AArch64 in Non-debug state. This behaviour >>>> has to replicated and it involves the higher EL setting up the PSTATE registers >>>> correctly and values in other registers for the lower EL (spsr, elr and fault >>>> syndrome registers) and jumping to the right offset point to by the vbar_elx of >>>> the lower EL. To the lower EL is appears as a SError has triggered at its >>>> exception vector and it can proceed with the fault handling. >>>> >>>> Best Regards >>>> Soby Mathew >>>> >>>>> -----Original Message----- >>>>> From: Pali Rohár <pali(a)kernel.org> >>>>> Sent: Monday, May 24, 2021 6:07 PM >>>>> To: Soby Mathew <Soby.Mathew(a)arm.com> >>>>> Subject: Rethrow SError from EL3 to kernel on arm64 >>>>> >>>>> Hello Soby! >>>>> >>>>> I have found following discussion in Armada 3720 PCIe SError issue: >>>>> https://review.trustedfirmware.org/c/TF-A/trusted-firmware- >>>> <https://review.trustedfirmware.org/c/TF-A/trusted-firmware-> >>>>> a/+/1541/comment/ca882427_d142bde2/ >>>>> >>>>> TF-A on Armada 3720 redirects all SErrors to EL3 and panic in TF-A handler. >>>>> You wrote in that discussion: >>>>> >>>>> Ideally you need to signal the SError back to kernel from EL3 using >>>>> SDEI or inject the SError to the lower EL and the kernel can decide to >>>>> die or not. >>>>> >>>>> And I would like to ask you, could you help me with implementation of this >>>>> SError rethrow functionality? Because I have absolutely no idea how to do it >>>>> and catching all SErrors in EL3 is causing issues because some of them can be >>>>> handled and recovered by kernel. >>>> -- >>>> TF-A mailing list >>>> TF-A(a)lists.trustedfirmware.org >>>> https://lists.trustedfirmware.org/mailman/listinfo/tf-a >>>> <https://lists.trustedfirmware.org/mailman/listinfo/tf-a> >>>> >>> >

4 years, 1 month

2
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Re: [TF-A] SP manifest: avoid manual updates to "entrypoint-offset"

by raghu.ncstate＠icloud.com

>> Our initial ask was to only bump the SP image entrypoint past the DTB boundary while generating SP.pkg using sptool. IIUC, the issue you brought up is for passing the manifest base address to the SP at runtime. I think these two are independent issues. Please advise. [RK] Agree here. Passing information through the manifest to the SP is orthogonal to the main problem at hand where we are assuming that the size of manifest cannot be > 4K and the entrypoint offset is always at 0x100. -Raghu -----Original Message----- From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Varun Wadekar via TF-A Sent: Tuesday, June 22, 2021 7:35 AM To: Olivier Deprez <Olivier.Deprez(a)arm.com>; tf-a(a)lists.trustedfirmware.org Cc: Raghupathy Krishnamurthy <raghupathyk(a)nvidia.com>; Nicolas Benech <nbenech(a)nvidia.com> Subject: Re: [TF-A] SP manifest: avoid manual updates to "entrypoint-offset" Hi Olivier, >> [OD] The two questions are which entity is loading boot data (can be a DT blob) that is to be consumed by the SP? And how is the address for boot data conveyed to the SP? The SP manifest is made for the SPMC consumption. I guess it's ok to conflate DT information required by the SP into the SP manifest. It means the bootloader loads both the SP manifest and the SP boot data in a single "SP package". In current implementation the SP has no standard way to know where the DT blob is loaded in its own memory range. We have experimental patches around the FF-A boot protocol which may help. [VW] You are right - bootloader loads SP.pkg (header+manifest+image) into memory. Can you please help me understand what "SP boot data" contains? For passing the SP manifest pointer to the SP we should ask for ideas from the community. Some ideas to get the discussion started: 1. SPMC creates a mapping for the manifest in the SP's virtual address space. SP issues a SVC call to get the virtual address from the SPMC 2. SPMC creates a mapping for the manifest in the SP's virtual address space and passes the pointer to SP via X0 3. SP manifest contains an entry to publish the virtual address for its manifest. SPMC reads this entry and maps the manifest at that virtual address during boot. >> [OD] If the assumptions (implementation defined) are that the SP boot data fits into the SP manifest, and that the SP finds this data at a fixed address (e.g. offset 0 in the SP package) then yes it can be a way to go. [VW] Our initial ask was to only bump the SP image entrypoint past the DTB boundary while generating SP.pkg using sptool. IIUC, the issue you brought up is for passing the manifest base address to the SP at runtime. I think these two are independent issues. Please advise. -Varun -----Original Message----- From: Olivier Deprez <Olivier.Deprez(a)arm.com> Sent: Tuesday, June 22, 2021 8:17 AM To: Varun Wadekar <vwadekar(a)nvidia.com>; tf-a(a)lists.trustedfirmware.org Cc: Raghupathy Krishnamurthy <raghupathyk(a)nvidia.com>; Nicolas Benech <nbenech(a)nvidia.com> Subject: Re: SP manifest: avoid manual updates to "entrypoint-offset" External email: Use caution opening links or attachments Hi Varun, (sorry last message sent too fast) See few comments inline [OD]. Regards, Olivier. ________________________________________ From: Varun Wadekar <vwadekar(a)nvidia.com> Sent: 17 June 2021 12:33 To: Olivier Deprez; tf-a(a)lists.trustedfirmware.org Cc: Raghupathy Krishnamurthy; Nicolas Benech Subject: RE: SP manifest: avoid manual updates to "entrypoint-offset" Hi, >> [OD] Ok. How is the SP informed about where to find the dtb (IPA address)? Saying this because the boot protocol between Hafnium and SPs is very much implementation specific at this moment and does not strictly follow the FF-A spec recommendations (data passing as TLVs). There is a trick that the manifest blob remains fortunately mapped from offset 0 in the SP IPA range. So it may be able to extract manifest data by mapping it the Stage-1 translation regime. But as said this does not follow a standard. [VW] We don't have a policy for all SPs, yet. At least I don't know of one. But in our experimental setup we plan to work on some assumptions e.g. assume the manifest blob to always be present at a certain address. [OD] The two questions are which entity is loading boot data (can be a DT blob) that is to be consumed by the SP? And how is the address for boot data conveyed to the SP? The SP manifest is made for the SPMC consumption. I guess it's ok to conflate DT information required by the SP into the SP manifest. It means the bootloader loads both the SP manifest and the SP boot data in a single "SP package". In current implementation the SP has no standard way to know where the DT blob is loaded in its own memory range. We have experimental patches around the FF-A boot protocol which may help. >> [OD] I think review link is mysteriously broken and the review lost. But Joao can provide the new link if necessary. I understand the intent of not making things too complex. [VW] Can we list down the next steps? Do we agree in principle that sptool needs to be upgraded to handle this use case? We can collaborate on an implementation, once we agree on the direction. [OD] If the assumptions (implementation defined) are that the SP boot data fits into the SP manifest, and that the SP finds this data at a fixed address (e.g. offset 0 in the SP package) then yes it can be a way to go. Cheers. -----Original Message----- From: Olivier Deprez <Olivier.Deprez(a)arm.com> Sent: Thursday, June 17, 2021 8:40 AM To: Varun Wadekar <vwadekar(a)nvidia.com>; tf-a(a)lists.trustedfirmware.org Cc: Raghupathy Krishnamurthy <raghupathyk(a)nvidia.com>; Nicolas Benech <nbenech(a)nvidia.com> Subject: Re: SP manifest: avoid manual updates to "entrypoint-offset" External email: Use caution opening links or attachments Hi Varun, Few comments [OD] Regards, Olivier. ________________________________________ From: Varun Wadekar <vwadekar(a)nvidia.com> Sent: 16 June 2021 14:37 To: Olivier Deprez; tf-a(a)lists.trustedfirmware.org Cc: Raghupathy Krishnamurthy; Nicolas Benech Subject: RE: SP manifest: avoid manual updates to "entrypoint-offset" Hi, >> Just a small heads up VHE SEL0 changes are tested within the Hafnium CI presently and do not relate to TF-A CI. sptool is a TF-A tool and there is no link to the Hafnium CI. [VW] Thanks for the heads up. >> what is the order in size for the manifest dtb you require in Tegra platform? Are the supplementary nodes in this manifest consumed by Hafnium or the SP itself? [VW] We can assume tens of KB. In the worst case, a few hundred KB. The manifest is targeted towards the SP and not meant for Hafnium. Just curious, do you see any pitfalls? [OD] Ok. How is the SP informed about where to find the dtb (IPA address)? Saying this because the boot protocol between Hafnium and SPs is very much implementation specific at this moment and does not strictly follow the FF-A spec recommendations (data passing as TLVs). There is a trick that the manifest blob remains fortunately mapped from offset 0 in the SP IPA range. So it may be able to extract manifest data by mapping it the Stage-1 translation regime. But as said this does not follow a standard. >> To set the complete picture, Joao had made some exploration around more dynamic SP configuration [2], maybe there are ideas to gather from there. [VW] Thanks for the links. I will review and leave comments - although we are not looking at introducing yet another script. [OD] I think review link is mysteriously broken and the review lost. But Joao can provide the new link if necessary. I understand the intent of not making things too complex. Cheers. -----Original Message----- From: Olivier Deprez <Olivier.Deprez(a)arm.com> Sent: Wednesday, June 16, 2021 12:59 PM To: Varun Wadekar <vwadekar(a)nvidia.com>; tf-a(a)lists.trustedfirmware.org Cc: Raghupathy Krishnamurthy <raghupathyk(a)nvidia.com>; Nicolas Benech <nbenech(a)nvidia.com> Subject: Re: SP manifest: avoid manual updates to "entrypoint-offset" External email: Use caution opening links or attachments Hi Varun, See inline [OD] Regards, Olivier. ________________________________________ From: Varun Wadekar <vwadekar(a)nvidia.com> Sent: 16 June 2021 13:07 To: Olivier Deprez; tf-a(a)lists.trustedfirmware.org Cc: Raghupathy Krishnamurthy; Nicolas Benech Subject: RE: SP manifest: avoid manual updates to "entrypoint-offset" HI Olivier, >> [OD] Just to be clear, is this about SEL0 partitions using an SEL1 >> shim No, this issue can be seen even without the shim. I don't think the usage of shim or VHE really matters here. [OD] All right. Just a small heads up VHE SEL0 changes are tested within the Hafnium CI presently and do not relate to TF-A CI. sptool is a TF-A tool and there is no link to the Hafnium CI. Not an issue as such but just making sure you have the full picture. At some point in time, when Hf VHE changes are merged we can create a specific TF-A test config to cover this case if necessary. Out of curiosity what is the order in size for the manifest dtb you require in Tegra platform? Are the supplementary nodes in this manifest consumed by Hafnium or the SP itself? >> [OD] This does not relate exactly to your problem but the effect is the "same" (aka there is more room for the manifest dtb). Agree this still requires hard-coding the entry point. At this stage I had thought of pushing the entry point even farther at a reasonably large 64KB aligned offset such that it helps with both problems. I agree, this approach is good for the short term. But I propose we craft a forward-looking solution. Are you planning on merging the sptool patch[1]? If not, I propose we come up with a way to dynamically update the SP manifest - I understand this involves adding libfdt to update the manifest. [OD] There is no pressing need to merge [1] in the short term so this can wait for a better solution. To set the complete picture, Joao had made some exploration around more dynamic SP configuration [2], maybe there are ideas to gather from there. -Varun [1] https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Freview.tr… [2] https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.tru… -----Original Message----- From: Olivier Deprez <Olivier.Deprez(a)arm.com> Sent: Wednesday, June 16, 2021 11:42 AM To: tf-a(a)lists.trustedfirmware.org; Nicolas Benech <nbenech(a)nvidia.com> Cc: Raghupathy Krishnamurthy <raghupathyk(a)nvidia.com>; Varun Wadekar <vwadekar(a)nvidia.com> Subject: Re: SP manifest: avoid manual updates to "entrypoint-offset" External email: Use caution opening links or attachments Hi, See few comments inline [OD] Regards, Olivier. ________________________________________ From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Varun Wadekar via TF-A <tf-a(a)lists.trustedfirmware.org> Sent: 16 June 2021 11:41 To: tf-a(a)lists.trustedfirmware.org Cc: Raghupathy Krishnamurthy; Nicolas Benech Subject: [TF-A] SP manifest: avoid manual updates to "entrypoint-offset" Hello, We (Nico/Raghu) have been implementing SEL0 partitions for Tegra platforms [OD] Just to be clear, is this about SEL0 partitions using an SEL1 shim (as per https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Freview.tr… )? and recently hit an issue, where the "entrypoint-offset" field of the SP manifest [1] cannot cope with increasing manifest blobs. The way the SP manifest is created today, the "entrypoint-offset" field is set to a value *statically* by the implementer. Down the line if the manifest grows past the value written in the "entrypoint-offset", we must manually update it. This needs to be fixed. We believe there is an opportunity to upgrade the sptool to handle this situation during SP package creation, where sptool calculates the manifest size and bumps the "entrypoint-offset" past the end of the manifest. There are other ways of patching the SP manifest at runtime, but they seem sub-optimal. Please let me know if there are other ideas to solve this problem. I will post a patch to update the sptool shortly but wanted to get the ball rolling. [OD] We had an attempt (https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Freview.tr…) to move the entry point farther in the image such that we can support 64KB granules in the Stage-1 translation regime. This does not relate exactly to your problem but the effect is the "same" (aka there is more room for the manifest dtb). Agree this still requires hard-coding the entry point. At this stage I had thought of pushing the entry point even farther at a reasonably large 64KB aligned offset such that it helps with both problems. Cheers. [1] 14. FF-A manifest binding to device tree - Trusted Firmware-A documentation<https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftrustedfi…> -- TF-A mailing list TF-A(a)lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/tf-a

4 years, 1 month

4
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Re: [TF-A] A Q about TZ porting guide

by Manish Pandey2

Hi Boaz, It appears that you have included plat/arm files in your platform porting which is causing Arm platform function definition to be included. Along with providing generic implementations Arm also has its own platforms(like any other partner platforms), code under plat/arm is meant only for Arm platforms. Check your make file and make sure that you don't include plat/arm/common/arm_pm.c(to avoid plat_setup_psci_ops) and plat/arm/common/aarch64/arm_helpers.S(for other functions you mentioned) this will avoid multiple definition errors. Hope this helps thanks Manish ________________________________ From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of IS20 Boaz Baron via TF-A <tf-a(a)lists.trustedfirmware.org> Sent: 29 July 2021 09:12 To: Madhukar Pappireddy <Madhukar.Pappireddy(a)arm.com> Cc: tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org>; IN20 Hila Miranda-Kuzi <Hila.Miranda-Kuzi(a)nuvoton.com> Subject: Re: [TF-A] A Q about TZ porting guide Also, those functions aren’t defined as WEAK so I encountered the same problem (multiple definitions) plat_crash_console_putc plat_crash_console_flush platform_mem_init From: IS20 Boaz Baron Sent: Thursday, July 29, 2021 10:14 AM To: Madhukar Pappireddy <Madhukar.Pappireddy(a)arm.com> Cc: tf-a(a)lists.trustedfirmware.org; IN20 Hila Miranda-Kuzi <Hila.Miranda-Kuzi(a)nuvoton.com> Subject: RE: [TF-A] A Q about TZ porting guide Thanks Madhukar for your answer, I think I wasn’t so clear. plat_setup_psci_ops is listed as mandatory in the porting guide. I implemented it locally but linkage fails because it is also defined in arm_pm.c. How do you suggest to avoid this multiple definition? Thanks, Boaz. From: Madhukar Pappireddy <Madhukar.Pappireddy(a)arm.com<mailto:Madhukar.Pappireddy@arm.com>> Sent: Wednesday, July 28, 2021 10:44 PM To: IS20 Boaz Baron <boaz.baron(a)nuvoton.com<mailto:boaz.baron@nuvoton.com>> Cc: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> Subject: RE: [TF-A] A Q about TZ porting guide Hi Boaz Yes, plat_setup_psci_ops() is mandatory. Every platform needs to implement it independently. You can use the implementation from [1] as a reference. I don’t think you have to delete any original function. If your platform does not support PSCI spec, you can implement a dummy function. Hope it helps. int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { return 0; } [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/c…<https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.trust…> Thanks, Madhukar From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org<mailto:tf-a-bounces@lists.trustedfirmware.org>> On Behalf Of IS20 Boaz Baron via TF-A Sent: Wednesday, July 28, 2021 7:58 AM To: tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> Subject: [TF-A] A Q about TZ porting guide Hi all, I have a Q about plat_setup_psci_ops() function implementation , In the porting guide, that function is defined as mandatory BUT the original (arm) function isn’t defined as #pargam WEAK. what should I do? to use/ delete the original function? Thanks, Boaz. ________________________________ The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton. ________________________________ The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

4 years, 1 month

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Re: [TF-A] A Q about TZ porting guide

by Madhukar Pappireddy

Hi Boaz Yes, plat_setup_psci_ops() is mandatory. Every platform needs to implement it independently. You can use the implementation from [1] as a reference. I don't think you have to delete any original function. If your platform does not support PSCI spec, you can implement a dummy function. Hope it helps. int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { return 0; } [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/c… Thanks, Madhukar From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of IS20 Boaz Baron via TF-A Sent: Wednesday, July 28, 2021 7:58 AM To: tf-a(a)lists.trustedfirmware.org Subject: [TF-A] A Q about TZ porting guide Hi all, I have a Q about plat_setup_psci_ops() function implementation , In the porting guide, that function is defined as mandatory BUT the original (arm) function isn't defined as #pargam WEAK. what should I do? to use/ delete the original function? Thanks, Boaz. ________________________________ The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

4 years, 1 month

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TF-A Tech Forum Agenda: Thu 29th July 2021 16:00 – 17:00 (BST)

by Joanna Farley

Hi All, The next TF-A Tech Forum is scheduled for Thu 29th July 2021 16:00 – 17:00 (BST). Agenda: * Firmware Update Discussions - Led by Manish Badarkhe * A brief overview of firmware update mechanism as per firmware update specification release https://developer.arm.com/documentation/den0118/a/ (Version1.0 BET0). * Discuss TF-A BL2 involvement in the firmware update operation. [Patches for this work are in review: https://review.trustedfirmware.org/q/topic:%22fw-update-2%22+(status:open%2…] * Discuss existing firmware update mechanisms in the partner platforms and if any challenges to adapt to this firmware update specification. If TF-A contributors have anything they wish to present at any future TF-A tech forum please contact me to have that scheduled. Previous sessions, both recording and presentation material can be found on the trustedfirmware.org TF-A Technical meeting webpage: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/ A scheduling tracking page is also available to help track sessions suggested: https://developer.trustedfirmware.org/w/tf_a/tf-a-tech-forum-scheduling/ Final decisions on what will be presented will be shared a few days before the next meeting on the TF-A mailing list. You have been invited to the following event. TF-A Tech Forum When Every 2 weeks from 16:00 to 17:00 on Thursday United Kingdom Time Calendar tf-a(a)lists.trustedfirmware.org Who • Bill Fletcher- creator • tf-a(a)lists.trustedfirmware.org more details »<https://www.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1cTJrM…> We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/<https://www.google.com/url?q=https%3A%2F%2Fwww.trustedfirmware.org%2Fmeetin…> Trusted Firmware is inviting you to a scheduled Zoom meeting. Join Zoom Meeting https://zoom.us/j/9159704974<https://www.google.com/url?q=https%3A%2F%2Fzoom.us%2Fj%2F9159704974&sa=D&us…> Meeting ID: 915 970 4974 One tap mobile +16465588656,,9159704974# US (New York) +16699009128,,9159704974# US (San Jose) Dial by your location +1 646 558 8656 US (New York) +1 669 900 9128 US (San Jose) 877 853 5247 US Toll-free 888 788 0099 US Toll-free Meeting ID: 915 970 4974 Find your local number: https://zoom.us/u/ad27hc6t7h<https://www.google.com/url?q=https%3A%2F%2Fzoom.us%2Fu%2Fad27hc6t7h&sa=D&us…> Going (tf-a(a)lists.trustedfirmware.org)? All events in this series: Yes<https://www.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tMmk1cT…> - Maybe<https://www.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tMmk1cT…> - No<https://www.google.com/calendar/event?action=RESPOND&eid=NWlub3Ewdm1tMmk1cT…> more options »<https://www.google.com/calendar/event?action=VIEW&eid=NWlub3Ewdm1tMmk1cTJrM…> Invitation from Google Calendar<https://www.google.com/calendar/> You are receiving this courtesy email at the account tf-a(a)lists.trustedfirmware.org because you are an attendee of this event. To stop receiving future updates for this event, decline this event. Alternatively, you can sign up for a Google Account at https://www.google.com/calendar/ and control your notification settings for your entire calendar. Forwarding this invitation could allow any recipient to send a response to the organiser and be added to the guest list, invite others regardless of their own invitation status or to modify your RSVP. Learn more<https://support.google.com/calendar/answer/37135#forwarding>. Thanks Joanna

4 years, 1 month

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A Q about TZ porting guide

by IS20 Boaz Baron

Hi all, I have a Q about plat_setup_psci_ops() function implementation , In the porting guide, that function is defined as mandatory BUT the original (arm) function isn't defined as #pargam WEAK. what should I do? to use/ delete the original function? Thanks, Boaz. ________________________________ The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

4 years, 1 month

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Secure boot without FIP

by guillaume pivetta

Hi, I’m trying to implement a secure boot on a STM32MP1 without using the FIP file. For now , I am not able to use FIP format during the boot process so I use a depreciated boot process with TF-Av2.2 as FSBL and U-Boot as SSBL to boot my Board. My boot process do Romcode -> TF-A (BL2) -> SP_min (BL32) -> U-Boot (BL33) -> Linux kernel I succefully implemented signature authentification between U-Boot and Linux image, but between TF-A and U-Boot it’s a little bit harder. I learned on ST wiki how to sign my u-boot binary with the STM32MP_SigningTool_CLI, but when I sign my binary with a custom private key, TF-A don’t authentified it on boot, even if i tryed to pass my key to TF-A at compilation time with the BL33_KEY argument, which i think is dedicated to the FIP usage. I found, in the sources of TF-A, what I think being a developpement key, named « arm_rotpk_ecdsa.pem ». And when I sign my binary with this key, I am able to perform the signature check and continu my boot process. So I tryed to change this key with a custom one and recompile TF-A to update the key in the final binary, but it seem that it is not so simple. I found yesterday that the auth_mod_init() function wasn’t call because I had forgotten the TUSTED_BOARD_BOOT=1 compilation argument. But when I activate it, the compilation doesn’t work and i see « build/arm-trusted-firmware-v2.2/bl2/bl2_main.c:91: undefined reference to `auth_mod_init' » Whitch traditionnaly append when linker don’t find the .o where the functions are implemented. I would like to know if it is possible to implement some kind of authentification with custom keys without FIP and if yes where can i find some hints/ressources/tutorial ? I don’t find a lot of ressources about secure boot without FIP so I hope you will be able to help me.

4 years, 1 month

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Re: [TF-A] Please provide option to build with GICv3 for qemu

by Jens Wiklander

Hi Alexey, On Thu, Jul 22, 2021 at 10:14 AM Alexey Kazantsev via TF-A <tf-a(a)lists.trustedfirmware.org> wrote: > > Hello! > > Please add a build option for selecting GICv3 instead of GICv2 for QEMU > platform. > > There is the following line in plat/qemu/qemu/platform.mk : > QEMU_USE_GIC_DRIVER := QEMU_GICV2 > > It doesn't imply setting GICv3 externally by build system of other > projects, like OP-TEE. When building with OP-TEE we're overriding this assignment by passing "QEMU_USE_GIC_DRIVER=$(TFA_GIC_DRIVER)" (where TFA_GIC_DRIVER is either QEMU_GICV3 or QEMU_GICV2) on the command line. This is now tested on a regular basis since we've recently added Xen support to the OP-TEE build setup on QEMU V8 and this depends on using GICv3 instead of GICv2. Does this help in your case? Cheers, Jens

4 years, 1 month

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Please provide option to build with GICv3 for qemu

by Alexey Kazantsev

Hello! Please add a build option for selecting GICv3 instead of GICv2 for QEMU platform. There is the following line in plat/qemu/qemu/platform.mk : QEMU_USE_GIC_DRIVER := QEMU_GICV2 It doesn't imply setting GICv3 externally by build system of other projects, like OP-TEE. Best regards, Aleksey.

4 years, 1 month

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