Hi James & TF-A guys,
When hest acpi table configure Hardware Error Notification type as
Software Delegated Exception(0x0B) for RAS event, kernel RAS interacts with
TF-A by SDEI mechanism. On the firmware first system, kernel was notified by
TF-A sdei call.
The calling flow like as below when fatal RAS error happens:
TF-A notify kernel flow:
sdei_dispatch_event()
ehf_activate_priority()
call sdei callback // callback registered by kerenl
ehf_deactivate_priority()
Kernel sdei callback:
sdei_asm_handler()
__sdei_handler()
_sdei_handler()
sdei_event_handler()
ghes_sdei_critical_callback()
ghes_in_nmi_queue_one_entry()
/* if RAS error is fatal */
__ghes_panic()
panic()
If fatal RAS error occured, panic was called in sdei_asm_handle()
without ehf_deactivate_priority executed, which lead interrupt masked.
If interrupt masked, system would be halted in kdump flow like this:
arm-smmu-v3 arm-smmu-v3.3.auto: allocated 65536 entries for cmdq
arm-smmu-v3 arm-smmu-v3.3.auto: allocated 32768 entries for evtq
arm-smmu-v3 arm-smmu-v3.3.auto: allocated 65536 entries for priq
arm-smmu-v3 arm-smmu-v3.3.auto: SMMU currently enabled! Resetting...
So interrupt should be restored before panic otherwise kdump will hang.
In the process of sdei, a SDEI_EVENT_COMPLETE(or SDEI_EVENT_COMPLETE_AND_RESUME)
call should be called before panic for a completed run of ehf_deactivate_priority().
The ehf_deactivate_priority() function restore pmr_el1 to original value(>0x80).
The SDEI dispatch flow was broken if SDEI_EVENT_COMPLETE was not be called.
This will bring about two issue:
1 Kdump will hang for firmware reporting fatal RAS event by SDEI;
(as explain above)
2 For NMI scene,TF-A enable a secure timer, the PPI 29 will trigger periodically.
Kernel register a callback for hard lockup. The below code will not be
called when panic in kernel callback:
TF-A, services/std_svc/sdei/sdei_intr_mgmt.c sdei_intr_handler():
/*
* We reach here when client completes the event.
*
* If the cause of dispatch originally interrupted the Secure world,
* resume Secure.
*
* No need to save the Non-secure context ahead of a world switch: the
* Non-secure context was fully saved before dispatch, and has been
* returned to its pre-dispatch state.
*/
if (sec_state == SECURE)
restore_and_resume_secure_context();
/*
* The event was dispatched after receiving SDEI interrupt. With
* the event handling completed, EOI the corresponding
* interrupt.
*/
if ((map->ev_num != SDEI_EVENT_0) && !is_map_bound(map)) {
ERROR("Invalid SDEI mapping: ev=%u\n", map->ev_num);
panic();
}
plat_ic_end_of_interrupt(intr_raw);
How to fix above issues?
I think the root cause is that kernel broken the SDEI dispatch flow, so kernel
should modify to fix these issues.
Thanks,
Ming
Hi all,
We are pleased to announce the formal release of Trusted Firmware-A version 2.6, Trusted Firmware-A Tests version 2.6, Hafnium version 2.6 and TF-A OpenCI Scripts 2.6 Releases involving the tagging of multiple sub repositories.
These went live on 24th November 2021.
Notable Features of the Version 2.6 Release across repositories are as follows:
* v8-R64 Upstream support, trusted-boot (BL1) only
* RME patches (4 world support)
* Hunter & Hayes CPU support
* Demeter (Makalu ELP for Infra) CPU support
* ARM v9.0-A ETE V1.0
* ARM v9.1-A ETE V1.1
* Armv9 RME support
* Generic Firmware Update support
* Measured Boot Enhancements
* MPMM AMU support SME (Mortlach) for non-secure world (FEAT_SME)
* Security hardening LLVM/clang support.
* FF-A v1.1 notifications support.
* FF-A v1.1 interrupt handling support.
* S-EL0 partitions (through VHE in the secure world).
* SPM support for saving/restoring the normal world SVE live state.
* Build system update to LLVM/Clang 12.
* Updates to FF-A Setup and discovery.
* FF-A compliance fixes.
* Threat model introduced for SPMC at SEL2
* Eight new partner and Arm platforms support added
Please refer to the TF-A [1], Hafnium [2] and TF-A Tests [3] changelogs for the complete summary of changes the previous release.
The test plan and results [4] for the v2.6 release captures the release test activities.
TF-A [5], TF-A Test [6], Hafnium [7] and TF-A OpenCI Scripts [8] repositories are available
[1] https://trustedfirmware-a.readthedocs.io/en/v2.6/
[2] https://review.trustedfirmware.org/plugins/gitiles/hafnium/hafnium/+/HEAD/d…
[3] https://trustedfirmware-a-tests.readthedocs.io/en/v2.6/
[4] https://confluence.arm.com/display/BSGSoftware/TF-A+v2.6+Test+Plan+and+Resu…
[5] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tag/?h=v2.6
[6] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tag/?h=v2.6
[7] https://git.trustedfirmware.org/hafnium/hafnium.git/tag/?h=v2.6
[8] https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tag/?h=v2.6
Thanks & best regards,
[cid:image001.jpg@01D7E120.C34F0DA0]
Bipin Ravi | Principal Design Engineer
Bipin.Ravi(a)arm.com<mailto:Bipin.Ravi@arm.com> | Skype: Bipin.Ravi.ARM
Direct: +1-512-225 -1071 | Mobile: +1-214-212-0794
5707 Southwest Parkway, Suite 100, Austin, TX 78735
Hi.
I'm trying to run on our new platform Linux as BL33, preloaded to DDR.
currently simulated over QEMU.
I think that BL31 started BL33 in EL0, which cause problems:
QEMU outputs this message: (complete log below)
Exception return from AArch64 EL3 to AArch64 EL0 PC 0x800080000
What could I have done wrong in the configuration that caused it ?
What should I check ?
Thanks !
Ramon.
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.5(debug):v2.5-61-g84d7d6a30-dirty
NOTICE: BL1: Built : 14:53:02, Nov 21 2021
INFO: BL1: RAM 0x15500000 - 0x15513000
WARNING: BL1: neoverse_n1: CPU workaround for 1946160 was missing!
INFO: BL1: Loading BL2
INFO: Using mmap
INFO: Using FIP
INFO: Loading image id=1 at address 0x14300000
INFO: Image id=1 loaded: 0x14300000 - 0x143052d1
INFO: bl1_mem_layout->total_base = 0x14000000x
NOTICE: BL1: Booting BL2
INFO: Entry point address = 0x14300000
INFO: SPSR = 0x3c5
Exception return from AArch64 EL3 to AArch64 EL1 PC 0x14300000
INFO: BL1 inherited memory layout: 0x14000000 [size = 22020096]
NOTICE: BL2: v2.5(debug):v2.5-61-g84d7d6a30-dirty
NOTICE: BL2: Built : 14:53:02, Nov 21 2021
INFO: BL2: Skip loading image id 23
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: Using mmap
INFO: Using FIP
INFO: Loading image id=3 at address 0x800000000
INFO: Image id=3 loaded: 0x800000000 - 0x8000080a9
INFO: BL2: Skip loading image id 5
Taking exception 13 [Secure Monitor Call]
...from EL1 to EL3
...with ESR 0x17/0x5e000000
...with ELR 0x14302a04
...to EL3 PC 0x5400 PSTATE 0x3cd
NOTICE: BL1: Booting BL31
INFO: Entry point address = 0x800000000
INFO: SPSR = 0x3cd
Exception return from AArch64 EL3 to AArch64 EL3 PC 0x800000000
INFO: Boot BL33 from 0x800080000 for 0 Bytes
NOTICE: BL31: v2.5(debug):v2.5-61-g84d7d6a30-dirty
NOTICE: BL31: Built : 14:53:04, Nov 21 2021
INFO: GICv3 without legacy support detected.
INFO: ARM GICv3 driver initialized in EL3
INFO: Maximum SPI INTID supported: 63
INFO: BL31: Initializing runtime services
WARNING: BL31: neoverse_n1: CPU workaround for 1946160 was missing!
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x800080000
INFO: SPSR = 0x0
Exception return from AArch64 EL3 to AArch64 EL0 PC 0x800080000
Taking exception 1 [Undefined Instruction]
...from EL0 to EL1
...with ESR 0x18/0x6232c061
...with ELR 0x8000b7164
...to EL1 PC 0x400 PSTATE 0x3c5
Taking exception 4 [Data Abort]
This event has been canceled with this note:
"Cancelling TF-A Tech Forum this week as the team have nothing to present.
We expect to have a topic for December 2nd."
Title: TF-A Tech Forum
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
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here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
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Hi Pali,
My understanding of the errata reporting mechanism is that some erratas are always checked during CPU boot. If the corresponding MACRO (ERRATA_A53_*) is disabled, then the ERRATA_MISSING code is reported.
I would be concerned if the CPU is affected by the errata. If the errata needs to be enabled, the fix would be to enable the ERRATA_A53_* from the platform makefile.
Hope this helps.
-Varun
-----Original Message-----
From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Pali Rohár via TF-A
Sent: Wednesday, July 7, 2021 9:11 PM
To: Olivier Deprez <Olivier.Deprez(a)arm.com>; Bipin Ravi <Bipin.Ravi(a)arm.com>; tf-a(a)lists.trustedfirmware.org
Cc: Konstantin Porotchkin <kostap(a)marvell.com>; Marek Behún <marek.behun(a)nic.cz>
Subject: Re: [TF-A] Missing CPU workaround warning message
External email: Use caution opening links or attachments
Hello! Could somebody from TF-A helps with these two topics? I would really need to know if "missing errata warnings" debug message is some critical and needs to be fixed (and how?) or it is just a debug message and therefore should not be a warning...
On Monday 28 June 2021 17:11:18 Pali Rohár wrote:
> On Monday 28 June 2021 14:03:06 Olivier Deprez wrote:
> > Hi,
> >
> > Is the question strictly related to this platform not implementing the mentioned errata (for which a platform change can be emitted)?
>
> Hello! The first question is if this is an issue that CPU workaround
> is missing. And if yes (which seems to be) how big issue it is? And
> how to resolve it?
>
> > Or is it more generally that those "missing errata warnings" are not printed in release mode?
> > Assuming the latter, it looks to me it is the integrator mistake to not include the appropriate mitigations at development phase (hence while using debug mode for building TF-A).
> > Then when the device is deployed (hence most often built for release mode), if this message is printed it is an indication for a malicious agent that such attack vector through mis-implemented errata is possible. So the consequence is possibly even worst than just "missing" to include the errata.
> >
> > Other TF-Aers (Bipin?) may have other opinions?
>
> And this is a second question. If missing CPU workaround is an issue,
> should not be it printed also in release build?
>
> Also I see that in release builds are omitted not only messages about
> missing CPU workarounds, but basically _all_ warning messages. But
> notice messages are _not_ omitted. Which seems strange as in most
> cases notice message has lower priority than warning message.
>
> >
> > Regards,
> > Olivier.
> >
> > ________________________________________
> > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of
> > Pali Rohár via TF-A <tf-a(a)lists.trustedfirmware.org>
> > Sent: 28 June 2021 15:36
> > To: tf-a(a)lists.trustedfirmware.org
> > Cc: Konstantin Porotchkin; Marek Behún
> > Subject: [TF-A] Missing CPU workaround warning message
> >
> > Hello! If TF-A for Marvell Armada 3720 platform is compiled in debug
> > mode then at runtime it prints following warning messages:
> >
> > WARNING: BL1: cortex_a53: CPU workaround for 855873 was missing!
> > WARNING: BL1: cortex_a53: CPU workaround for 1530924 was missing!
> >
> > These lines are not printed in non-debug mode. It is an issue?
> > --
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<Adding TF-A mailing list to the discussion>
Thanks, Soby. I agree that this needs to be re-evaluated for platforms. I think we should introduce an option to disable them, if required.
We plan to try some more experiments and hopefully remove the locks at least for Tegra platforms.
Looking forward to the elaborate answer.
From: Soby Mathew <Soby.Mathew(a)arm.com>
Sent: Tuesday, 2 November 2021 10:18 AM
To: Varun Wadekar <vwadekar(a)nvidia.com>; Manish Pandey2 <Manish.Pandey2(a)arm.com>; Dan Handley <Dan.Handley(a)arm.com>
Cc: Joanna Farley <Joanna.Farley(a)arm.com>; Matteo Carlini <Matteo.Carlini(a)arm.com>
Subject: RE: PSCI lock contention
External email: Use caution opening links or attachments
Hi Varun,
The short answer is that the locks are used to differentiate the last-CPU-to-suspend and similarly first-CPU-to-powerup at a given power domain level. Now, recent CPU features like DynamIQ means that we don't need to do this differentiation upto cluster level which TF-A hasn't optimized for yet AFAICS. I am happy to elaborate further , but could you please send the query to the TF-A mailing list as I would prefer this discussion to happen in the open if possible.
Best Regards
Soby Mathew
From: Varun Wadekar <vwadekar(a)nvidia.com<mailto:vwadekar@nvidia.com>>
Sent: 01 November 2021 20:14
To: Soby Mathew <Soby.Mathew(a)arm.com<mailto:Soby.Mathew@arm.com>>; Manish Pandey2 <Manish.Pandey2(a)arm.com<mailto:Manish.Pandey2@arm.com>>; Dan Handley <Dan.Handley(a)arm.com<mailto:Dan.Handley@arm.com>>
Cc: Joanna Farley <Joanna.Farley(a)arm.com<mailto:Joanna.Farley@arm.com>>; Matteo Carlini <Matteo.Carlini(a)arm.com<mailto:Matteo.Carlini@arm.com>>
Subject: PSCI lock contention
Hi,
We were trying performance benchmarking for CPU_SUSPEND on Tegra platforms. We take all CPU cores to CPU_SUSPEND and then wake them up with IPI - all at once and in serial order. From the numbers, we see that the CPUs powering up later take more time than the first one. We have narrowed the most time consumed to the PSCI locks - documented at docs/perf/psci-performance-juno.rst.
Can you please help me understand why these locks were added? As a quick experiment we tried the same benchmarking *without* the locks and the firmware does not blow up, but I would like to understand the impact from the analysis on Juno (docs/perf/psci-performance-juno.rst)
Happy to hop on a call to discuss further.
Thanks.
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TF-A Community,
Just a reminder we are looking to freeze the tree for release activities starting Monday.
Thanks
Joanna
From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Joanna Farley via TF-A <tf-a(a)lists.trustedfirmware.org>
Reply to: Joanna Farley <Joanna.Farley(a)arm.com>
Date: Monday, 1 November 2021 at 12:41
To: Joanna Farley via TF-A <tf-a(a)lists.trustedfirmware.org>
Subject: [TF-A] Trusted Firmware-A v2.6 release activities in November
TF-A Community,
This is to notify that we are planning to target the Trusted Firmware-A 2.6 release during the fourth week of Nov 2021 as part of the regular 6 month cadence.
The aim is to consolidate all TF-A work since the 2.5 release. As part of this, a release candidate tag will be created and release activities will commence from 15th November 2021 across all TF-A repositories.
Essentially we will not merge any major enhancements from this date until the release is made.
Please ensure any patches desired to make the 2.6 release are submitted in good time to be complete by 12th November 2021.
Any major enhancement patches still open after that date will not be merged until after the release.
This will involve the various repositories making up the broader TF-A project including the TF-A mainline, TF-A Tests, Hafnium, TF-A CI Scripts and TF-A CI Jobs.
We will endeavour minimise the disruption on patch merging and complete release activities ASAP after we start.
Thanks
Joanna
This event has been canceled with this note:
"No TF-A Tech Forum scheduled this week so cancelling."
Title: TF-A Tech Forum
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
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Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
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Forwarded on to TF-A Mail list. Seems postings from people with gmail.com email domains get automatically rejected, sorry Ramon not sure if that can be addressed.
Joanna
On 03/11/2021, 14:20, "Ramon Fried" <rfried.dev(a)gmail.com> wrote:
Hi.
I'm trying to run the example in TF-A documentation.
I found two problems.
First, the files: "tee-header_v2.bin, tee-pager_v2.bin,
tee-pageable_v2.bin" are not provided as binary downloads, and
instructions on how to get them are missing. turn's out you need to
build optee, but this step is skipped if you choose to download the
QEMU_EFI.fd from Linaro.
Second,
after following the instructions step by step resulted in the following error:
qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57
-kernel Image -no-acpi -append
'console=ttyAMA0,38400 keep_bootcon' -initrd rootfs.cpio.gz -smp
2 -m 1024 -bios flash.bin -d unimp
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.5(release):v2.5-60-g7737fdf0e
NOTICE: BL1: Built : 13:12:39, Nov 3 2021
NOTICE: BL1: Booting BL2
NOTICE: BL2: v2.5(release):v2.5-60-g7737fdf0e
NOTICE: BL2: Built : 13:12:42, Nov 3 2021
NOTICE: BL1: Booting BL31
NOTICE: BL31: v2.5(release):v2.5-60-g7737fdf0e
NOTICE: BL31: Built : 13:12:45, Nov 3 2021
read access to unsupported AArch64 system register op0:3 op1:0 crn:12
crm:12 op2:4
This occurs on Qemu 5.0 and also 6.0
Thanks,
Ramon.