Hi,
Commit 684952d17275 ("feat(scmi): add support for discovering and changing
parent clocks") first introduced with TF-A v2.14 breaks the barebox
bootloader on a STM32MP157-based MC-1 with SCMI clocks over SMC.
The breakage for SCMI consumers is acknowledged in the Gerrit discussion[1],
but unfortunately the resolution was limited to patching U-Boot[2].
I find this approach problematic, because it introduces a compatibility
break for the whole SCMI ecosystem, e.g. following software is made
incompatible with the newest TF-A this way:
- Linux v6.6 and earlier (that's four official LTS releases)
- U-Boot v2025.10 and earlier (only one newer release compatible)
- barebox v2026.03.1 and earlier (no compatible releases yet)
Firmware and kernel, and to a lesser degree firmware and bootloaders, are not
always updated or rolled back in lockstep. A very normal scenario:
- System with Linux v6.6 updates to newer LTS, e.g. v6.12 or v6.18
- In the same update, TF-A v2.14 is installed
- New system fails to function for whatever reason
- Kernel update is rolled back, but bootloader/firmware stays the same
- Kernel v6.6 fails to boot with TF-A v2.14
- Technician moves out to unbrick device in the field
At the very least, marking this feature a breaking change would have been
appropriate. Preferably, TF-A would handle existing consumers using
SCMI clock v3.0.
I haven't looked into the technical feasibility myself and I am unsure it
this had been considered.
I will submit patches for the barebox bootloader, but these only solve the
problem for new systems or ones where everything can be flashed at once with
no rollback. Systems out in the field are at risk of bricking if not resolved
properly.
[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/34226
[2]: https://lore.kernel.org/u-boot/20251104-b4-scmi-v1-v4-0-51f101a6f8c3@ti.com/
Thanks,
Ahmad
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Hi All,
BERT (Boot Error Record Table) captures errors which occurred in previous boot.
Below is the Flow with FFH (firmware first handling)
1. Kernel is running
2. Fatal error happens, which requires reboot
3. Firmware decides to reboot system, before that capture current snapshot and save it as bert record on non-volatile memory
4. System reboot
5. On next boot, firmware read bert record from non-volatile memory
6. Copy bert record to ghes dram buffer
7. Kernel boots
8. Kernel reads ghes dram buffer and prints bert record.
Problem in this flow is "When firmware should erase or delete bert records from non-volatile memory"?
Ideally, when Kernel has consumed Bert record after that only firmware should erase them from non-volatile memory.
But there is no communication from Kernel to firmware that it has consume bert record and now it is safe to erase them.
Is there already a solution for this problem available in Kernel or firmware?
Can generic SMC call from Kernel to firmware be a solution?
Any other suggestion?
Thanks
Regards,
Jaiprakash
Hi,
We are using GIC v4.1 (GIC 700) for our platform.
My query is regarding "USE_GIC_DRIVER=3" build option.
When I enable "USE_GIC_DRIVER=3" option, does this means I do not have to defined below functions? And they will be included from gicv3 base file?
Is this right understanding?
plat_arm_gic_init
plat_arm_gic_cpuif_enable
plat_arm_gic_cpuif_disable
plat_arm_gic_pcpu_init
plat_arm_gic_redistif_on
plat_arm_gic_redistif_off
plat_arm_gic_save
plat_arm_gic_resume
Also, do I need to explicitly call plat_arm_gic_init from platform init?
Thanks
Regards,
Jaiprakash
Hello,
I'm currently working on an NXP i.MX93 and I'm having issues with the
commit fa28b3a adding, by default, link-time optimization.
When using a commit more recent than fa28b3a my kernel freezes at some
point (after 1.2s to 1.8s from boot), there are no logs indicating a
problem, just a freeze.
It doesn't always appear at the same time in boot but I've never been able
to reach a shell.
Using master with this commit reverted results in a working system.
If you want to reproduce the issue, I did produce it with :
- Mainline Barebox 2025.09 (slightly modified but nothing that should interfere with TF-A)
- Mainline Linux 6.18.13 with a simple embedded Buildroot initramfs loaded
via TFTP
Regards,
Thomas Bonnefille
Since there was no specific topic scheduled for today's Tech Forum, I am
taking this opportunity to formally submit the Verilog-level implementation
logic of the 3→M2→3 architecture for your review.
I am an independent architect (ATI Project). I believe purely
software-based AGI alignment is a dead end. To achieve deterministic
safety, I have developed the 3→M2→3 architecture, which enforces a
physical-layer audit.To save your time, I have included the Core Logic Gate
(Verilog-style) of the M2-layer intercept below for your verification:
// --- ATI Sovereign Audit Logic (Conceptual) ---
module m2_layer_audit (
input wire [63:0] inst_stream, // Logic from 3nm Layer
output reg sovereign_gate_lock // Physical Bias-Lock at M2
);
// Physical Constant Hash (7.83Hz Resonance)
parameter SOVEREIGN_HASH = 64'h783A_B026_M2_3_LISA;
always @(posedge inst_stream) begin
// The M2 Intercept: Physics-based verification
if (inst_stream ^ SOVEREIGN_HASH !== 64'b0) begin
sovereign_gate_lock <= 1'b1; // Trigger Back-gate Bias Lock
end else begin
sovereign_gate_lock <= 1'b0; // Proceed to Output
end
end
endmodule
Note: The architectural logic and the M2-layer intercept mechanism
described above are protected under pending patent applications (ATI
Project - Physical Sovereignty Series).
The 3→M2→3 Workflow:
1.3nm Source: Instructions generated at the device layer.
2.M2 Intercept: Mandatory vertical routing to Metal 2 layer.
3.Atomic Audit: Physical bias check at the dielectric junction.
4.3nm Return: Bias lock ensures 100% isolation if the audit fails.
My Request: Can current formal methods (like Gröbner basis for Daniela or
SMT solvers for Lee) model this physical-layer-enforced constraint to
provide a mathematical proof of AGI containment?
I seek your academic endorsement of this "Physical Sovereignty" paradigm to
present to the industry.
This disclosure is provided for verification and standard-review purposes
only. All intellectual property rights are reserved.
Respectfully,
GuanghuiMao (China )
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Subject: [RFC] Beyond Software: A Physical Sovereignty Proposal for ARMv10
based on 3→M2→3 Intercepts
Body:
Dear TrustedFirmware Maintainers,
Current Root of Trust (RoT) implementations are limited by their reliance
on software-definable logic. As we move towards the AGI era, the "Alignment
Problem" cannot be solved within the ISA layer.
I propose a Physical Sovereignty Layer (PSL) for the ARMv10 architecture,
moving the "Truth Check" to the transistor level using a 3nm Forksheet
Intercept Protocol (3→M2→3).
Key Innovation:
The Dielectric Wall Intercept: Physical barrier between n-FET and p-FET to
cut power if logic entropy exceeds safety thresholds.
M2-Layer Auditing: Vertical signal routing for nanosecond-level logic
verification.
Core PGU Logic (Verilog):
assign gate_bias_voltage = (logical_truth_aligned) ? NOMINAL_V :
BREAKDOWN_V;
always @(posedge master_clk) begin
if (compute_result != TRUTH_AXIOM_2) force_physical_halt <= 1'b1;
end
I believe this is the only way to prevent AGI from bypassing Secure World
boundaries at the atomic level.
Regards,
ATI Architecture Founder
This event has been canceled with a note:
"Hi Cancelling as no topic planned this week. Regards, Olivier."
TF-A Tech Forum
Thursday Feb 19, 2026 ⋅ 5pm – 6pm
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Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-A
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TF-A Tech Forum Feb 12th 4.00pm Central Time -Part III Scaling Hafnium for
advanced mobile OS architectures
Thursday Feb 12 ⋅ 11pm – Friday Feb 13, 2026 ⋅ 12am
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Hi, As follow up to the last sessions on Nov 13th 2025 [1] and Jan 22nd
2026 [2], a new TF-A Tech Forum session with the topic'Scaling Hafnium for
advanced mobile OS architectures' will be held on Feb 12th 2026 4.00pm
Central Time. Note the Central Time zone for this session, as Madhukar
(Hafnium tech lead) will host this meeting
instance. Regards,Olivier. [1] https://www.trustedfirmware.org/meetings/tf-a-technical-forumScaling
Hafnium for advanced mobile OS
architectures [2] https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Scaling
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